sound/soc/intel/skylake/skl-sst-dsp.h

   1 /*
   2  * Skylake SST DSP Support
   3  *
   4  * Copyright (C) 2014-15, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as version 2, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  */
  15
  16 #ifndef __SKL_SST_DSP_H__
  17 #define __SKL_SST_DSP_H__
  18
  19 #include <linux/interrupt.h>
  20 #include <sound/memalloc.h>
  21 #include "skl-sst-cldma.h"
  22 #include "skl-tplg-interface.h"
  23 #include "skl-topology.h"
  24
  25 struct sst_dsp;
  26 struct skl_sst;
  27 struct sst_dsp_device;
  28
  29 /* Intel HD Audio General DSP Registers */
  30 #define SKL_ADSP_GEN_BASE               0x0
  31 #define SKL_ADSP_REG_ADSPCS             (SKL_ADSP_GEN_BASE + 0x04)
  32 #define SKL_ADSP_REG_ADSPIC             (SKL_ADSP_GEN_BASE + 0x08)
  33 #define SKL_ADSP_REG_ADSPIS             (SKL_ADSP_GEN_BASE + 0x0C)
  34 #define SKL_ADSP_REG_ADSPIC2            (SKL_ADSP_GEN_BASE + 0x10)
  35 #define SKL_ADSP_REG_ADSPIS2            (SKL_ADSP_GEN_BASE + 0x14)
  36
  37 /* Intel HD Audio Inter-Processor Communication Registers */
  38 #define SKL_ADSP_IPC_BASE               0x40
  39 #define SKL_ADSP_REG_HIPCT              (SKL_ADSP_IPC_BASE + 0x00)
  40 #define SKL_ADSP_REG_HIPCTE             (SKL_ADSP_IPC_BASE + 0x04)
  41 #define SKL_ADSP_REG_HIPCI              (SKL_ADSP_IPC_BASE + 0x08)
  42 #define SKL_ADSP_REG_HIPCIE             (SKL_ADSP_IPC_BASE + 0x0C)
  43 #define SKL_ADSP_REG_HIPCCTL            (SKL_ADSP_IPC_BASE + 0x10)
  44
  45 /*  HIPCI */
  46 #define SKL_ADSP_REG_HIPCI_BUSY         BIT(31)
  47
  48 /* HIPCIE */
  49 #define SKL_ADSP_REG_HIPCIE_DONE        BIT(30)
  50
  51 /* HIPCCTL */
  52 #define SKL_ADSP_REG_HIPCCTL_DONE       BIT(1)
  53 #define SKL_ADSP_REG_HIPCCTL_BUSY       BIT(0)
  54
  55 /* HIPCT */
  56 #define SKL_ADSP_REG_HIPCT_BUSY         BIT(31)
  57
  58 /* FW base IDs */
  59 #define SKL_INSTANCE_ID                 0
  60 #define SKL_BASE_FW_MODULE_ID           0
  61
  62 /* Intel HD Audio SRAM Window 1 */
  63 #define SKL_ADSP_SRAM1_BASE             0xA000
  64
  65 #define SKL_ADSP_MMIO_LEN               0x10000
  66
  67 #define SKL_ADSP_W0_STAT_SZ             0x1000
  68
  69 #define SKL_ADSP_W0_UP_SZ               0x1000
  70
  71 #define SKL_ADSP_W1_SZ                  0x1000
  72
  73 #define SKL_FW_STS_MASK                 0xf
  74
  75 #define SKL_FW_INIT                     0x1
  76 #define SKL_FW_RFW_START                0xf
  77
  78 #define SKL_ADSPIC_IPC                  1
  79 #define SKL_ADSPIS_IPC                  1
  80
  81 /* Core ID of core0 */
  82 #define SKL_DSP_CORE0_ID                0
  83
  84 /* Mask for a given core index, c = 0.. number of supported cores - 1 */
  85 #define SKL_DSP_CORE_MASK(c)            BIT(c)
  86
  87 /*
  88  * Core 0 mask = SKL_DSP_CORE_MASK(0); Defined separately
  89  * since Core0 is primary core and it is used often
  90  */
  91 #define SKL_DSP_CORE0_MASK              BIT(0)
  92
  93 /*
  94  * Mask for a given number of cores
  95  * nc = number of supported cores
  96  */
  97 #define SKL_DSP_CORES_MASK(nc)  GENMASK((nc - 1), 0)
  98
  99 /* ADSPCS - Audio DSP Control & Status */
 100
 101 /*
 102  * Core Reset - asserted high
 103  * CRST Mask for a given core mask pattern, cm
 104  */
 105 #define SKL_ADSPCS_CRST_SHIFT           0
 106 #define SKL_ADSPCS_CRST_MASK(cm)        ((cm) << SKL_ADSPCS_CRST_SHIFT)
 107
 108 /*
 109  * Core run/stall - when set to '1' core is stalled
 110  * CSTALL Mask for a given core mask pattern, cm
 111  */
 112 #define SKL_ADSPCS_CSTALL_SHIFT         8
 113 #define SKL_ADSPCS_CSTALL_MASK(cm)      ((cm) << SKL_ADSPCS_CSTALL_SHIFT)
 114
 115 /*
 116  * Set Power Active - when set to '1' turn cores on
 117  * SPA Mask for a given core mask pattern, cm
 118  */
 119 #define SKL_ADSPCS_SPA_SHIFT            16
 120 #define SKL_ADSPCS_SPA_MASK(cm)         ((cm) << SKL_ADSPCS_SPA_SHIFT)
 121
 122 /*
 123  * Current Power Active - power status of cores, set by hardware
 124  * CPA Mask for a given core mask pattern, cm
 125  */
 126 #define SKL_ADSPCS_CPA_SHIFT            24
 127 #define SKL_ADSPCS_CPA_MASK(cm)         ((cm) << SKL_ADSPCS_CPA_SHIFT)
 128
 129 enum skl_dsp_states {
 130         SKL_DSP_RUNNING = 1,
 131         SKL_DSP_RESET,
 132 };
 133
 134 struct skl_dsp_fw_ops {
 135         int (*load_fw)(struct sst_dsp  *ctx);
 136         /* FW module parser/loader */
 137         int (*load_library)(struct sst_dsp *ctx,
 138                 struct skl_dfw_manifest *minfo);
 139         int (*parse_fw)(struct sst_dsp *ctx);
 140         int (*set_state_D0)(struct sst_dsp *ctx, unsigned int core_id);
 141         int (*set_state_D3)(struct sst_dsp *ctx, unsigned int core_id);
 142         unsigned int (*get_fw_errcode)(struct sst_dsp *ctx);
 143         int (*load_mod)(struct sst_dsp *ctx, u16 mod_id, u8 *mod_name);
 144         int (*unload_mod)(struct sst_dsp *ctx, u16 mod_id);
 145
 146 };
 147
 148 struct skl_dsp_loader_ops {
 149         int stream_tag;
 150
 151         int (*alloc_dma_buf)(struct device *dev,
 152                 struct snd_dma_buffer *dmab, size_t size);
 153         int (*free_dma_buf)(struct device *dev,
 154                 struct snd_dma_buffer *dmab);
 155         int (*prepare)(struct device *dev, unsigned int format,
 156                                 unsigned int byte_size,
 157                                 struct snd_dma_buffer *bufp);
 158         int (*trigger)(struct device *dev, bool start, int stream_tag);
 159
 160         int (*cleanup)(struct device *dev, struct snd_dma_buffer *dmab,
 161                                  int stream_tag);
 162 };
 163
 164 struct skl_load_module_info {
 165         u16 mod_id;
 166         const struct firmware *fw;
 167 };
 168
 169 struct skl_module_table {
 170         struct skl_load_module_info *mod_info;
 171         unsigned int usage_cnt;
 172         struct list_head list;
 173 };
 174
 175 void skl_cldma_process_intr(struct sst_dsp *ctx);
 176 void skl_cldma_int_disable(struct sst_dsp *ctx);
 177 int skl_cldma_prepare(struct sst_dsp *ctx);
 178
 179 void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state);
 180 struct sst_dsp *skl_dsp_ctx_init(struct device *dev,
 181                 struct sst_dsp_device *sst_dev, int irq);
 182 bool is_skl_dsp_running(struct sst_dsp *ctx);
 183
 184 unsigned int skl_dsp_get_enabled_cores(struct sst_dsp *ctx);
 185 void skl_dsp_init_core_state(struct sst_dsp *ctx);
 186 int skl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask);
 187 int skl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask);
 188 int skl_dsp_core_power_up(struct sst_dsp *ctx, unsigned int core_mask);
 189 int skl_dsp_core_power_down(struct sst_dsp *ctx, unsigned int core_mask);
 190 int skl_dsp_core_unset_reset_state(struct sst_dsp *ctx,
 191                                         unsigned int core_mask);
 192 int skl_dsp_start_core(struct sst_dsp *ctx, unsigned int core_mask);
 193
 194 irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id);
 195 int skl_dsp_wake(struct sst_dsp *ctx);
 196 int skl_dsp_sleep(struct sst_dsp *ctx);
 197 void skl_dsp_free(struct sst_dsp *dsp);
 198
 199 int skl_dsp_get_core(struct sst_dsp *ctx, unsigned int core_id);
 200 int skl_dsp_put_core(struct sst_dsp *ctx, unsigned int core_id);
 201
 202 int skl_dsp_boot(struct sst_dsp *ctx);
 203 int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
 204                 const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
 205                 struct skl_sst **dsp);
 206 int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
 207                 const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
 208                 struct skl_sst **dsp);
 209 int skl_sst_init_fw(struct device *dev, struct skl_sst *ctx);
 210 int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx);
 211 void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx);
 212 void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx);
 213
 214 int snd_skl_get_module_info(struct skl_sst *ctx,
 215                                 struct skl_module_cfg *mconfig);
 216 int snd_skl_parse_uuids(struct sst_dsp *ctx, const struct firmware *fw,
 217                                 unsigned int offset, int index);
 218 int skl_get_pvt_id(struct skl_sst *ctx,
 219                                 struct skl_module_cfg *mconfig);
 220 int skl_put_pvt_id(struct skl_sst *ctx,
 221                                 struct skl_module_cfg *mconfig);
 222 int skl_get_pvt_instance_id_map(struct skl_sst *ctx,
 223                                 int module_id, int instance_id);
 224 void skl_freeup_uuid_list(struct skl_sst *ctx);
 225
 226 int skl_dsp_strip_extended_manifest(struct firmware *fw);
 227
 228 #endif /*__SKL_SST_DSP_H__*/