1 // SPDX-License-Identifier: GPL-2.0-only
3 * skl.c - Implementation of ASoC Intel SKL HD Audio driver
5 * Copyright (C) 2014-2015 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
8 * Derived mostly from Intel HDA driver with following copyrights:
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
13 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
16 #include <linux/module.h>
17 #include <linux/pci.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/platform_device.h>
20 #include <linux/firmware.h>
21 #include <linux/delay.h>
22 #include <sound/pcm.h>
23 #include <sound/soc-acpi.h>
24 #include <sound/soc-acpi-intel-match.h>
25 #include <sound/hda_register.h>
26 #include <sound/hdaudio.h>
27 #include <sound/hda_i915.h>
28 #include <sound/hda_codec.h>
30 #include "skl-sst-dsp.h"
31 #include "skl-sst-ipc.h"
32 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
33 #include "../../../soc/codecs/hdac_hda.h"
35 static int skl_pci_binding
;
36 module_param_named(pci_binding
, skl_pci_binding
, int, 0444);
37 MODULE_PARM_DESC(pci_binding
, "PCI binding (0=auto, 1=only legacy, 2=only asoc");
40 * initialize the PCI registers
42 static void skl_update_pci_byte(struct pci_dev
*pci
, unsigned int reg
,
43 unsigned char mask
, unsigned char val
)
47 pci_read_config_byte(pci
, reg
, &data
);
50 pci_write_config_byte(pci
, reg
, data
);
53 static void skl_init_pci(struct skl
*skl
)
55 struct hdac_bus
*bus
= skl_to_bus(skl
);
58 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
59 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
60 * Ensuring these bits are 0 clears playback static on some HD Audio
62 * The PCI register TCSEL is defined in the Intel manuals.
64 dev_dbg(bus
->dev
, "Clearing TCSEL\n");
65 skl_update_pci_byte(skl
->pci
, AZX_PCIREG_TCSEL
, 0x07, 0);
68 static void update_pci_dword(struct pci_dev
*pci
,
69 unsigned int reg
, u32 mask
, u32 val
)
73 pci_read_config_dword(pci
, reg
, &data
);
76 pci_write_config_dword(pci
, reg
, data
);
80 * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits
82 * @dev: device pointer
83 * @enable: enable/disable flag
85 static void skl_enable_miscbdcge(struct device
*dev
, bool enable
)
87 struct pci_dev
*pci
= to_pci_dev(dev
);
90 val
= enable
? AZX_CGCTL_MISCBDCGE_MASK
: 0;
92 update_pci_dword(pci
, AZX_PCIREG_CGCTL
, AZX_CGCTL_MISCBDCGE_MASK
, val
);
96 * skl_clock_power_gating: Enable/Disable clock and power gating
98 * @dev: Device pointer
99 * @enable: Enable/Disable flag
101 static void skl_clock_power_gating(struct device
*dev
, bool enable
)
103 struct pci_dev
*pci
= to_pci_dev(dev
);
104 struct hdac_bus
*bus
= pci_get_drvdata(pci
);
107 /* Update PDCGE bit of CGCTL register */
108 val
= enable
? AZX_CGCTL_ADSPDCGE
: 0;
109 update_pci_dword(pci
, AZX_PCIREG_CGCTL
, AZX_CGCTL_ADSPDCGE
, val
);
111 /* Update L1SEN bit of EM2 register */
112 val
= enable
? AZX_REG_VS_EM2_L1SEN
: 0;
113 snd_hdac_chip_updatel(bus
, VS_EM2
, AZX_REG_VS_EM2_L1SEN
, val
);
115 /* Update ADSPPGD bit of PGCTL register */
116 val
= enable
? 0 : AZX_PGCTL_ADSPPGD
;
117 update_pci_dword(pci
, AZX_PCIREG_PGCTL
, AZX_PGCTL_ADSPPGD
, val
);
121 * While performing reset, controller may not come back properly causing
122 * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset
123 * (init chip) and then again set CGCTL.MISCBDCGE to 1
125 static int skl_init_chip(struct hdac_bus
*bus
, bool full_reset
)
127 struct hdac_ext_link
*hlink
;
130 skl_enable_miscbdcge(bus
->dev
, false);
131 ret
= snd_hdac_bus_init_chip(bus
, full_reset
);
133 /* Reset stream-to-link mapping */
134 list_for_each_entry(hlink
, &bus
->hlink_list
, list
)
135 bus
->io_ops
->reg_writel(0, hlink
->ml_addr
+ AZX_REG_ML_LOSIDV
);
137 skl_enable_miscbdcge(bus
->dev
, true);
142 void skl_update_d0i3c(struct device
*dev
, bool enable
)
144 struct pci_dev
*pci
= to_pci_dev(dev
);
145 struct hdac_bus
*bus
= pci_get_drvdata(pci
);
149 reg
= snd_hdac_chip_readb(bus
, VS_D0I3C
);
150 /* Do not write to D0I3C until command in progress bit is cleared */
151 while ((reg
& AZX_REG_VS_D0I3C_CIP
) && --timeout
) {
153 reg
= snd_hdac_chip_readb(bus
, VS_D0I3C
);
156 /* Highly unlikely. But if it happens, flag error explicitly */
158 dev_err(bus
->dev
, "Before D0I3C update: D0I3C CIP timeout\n");
163 reg
= reg
| AZX_REG_VS_D0I3C_I3
;
165 reg
= reg
& (~AZX_REG_VS_D0I3C_I3
);
167 snd_hdac_chip_writeb(bus
, VS_D0I3C
, reg
);
170 /* Wait for cmd in progress to be cleared before exiting the function */
171 reg
= snd_hdac_chip_readb(bus
, VS_D0I3C
);
172 while ((reg
& AZX_REG_VS_D0I3C_CIP
) && --timeout
) {
174 reg
= snd_hdac_chip_readb(bus
, VS_D0I3C
);
177 /* Highly unlikely. But if it happens, flag error explicitly */
179 dev_err(bus
->dev
, "After D0I3C update: D0I3C CIP timeout\n");
183 dev_dbg(bus
->dev
, "D0I3C register = 0x%x\n",
184 snd_hdac_chip_readb(bus
, VS_D0I3C
));
188 * skl_dum_set - set DUM bit in EM2 register
189 * @bus: HD-audio core bus
191 * Addresses incorrect position reporting for capture streams.
192 * Used on device power up.
194 static void skl_dum_set(struct hdac_bus
*bus
)
196 /* For the DUM bit to be set, CRST needs to be out of reset state */
197 if (!(snd_hdac_chip_readb(bus
, GCTL
) & AZX_GCTL_RESET
)) {
198 skl_enable_miscbdcge(bus
->dev
, false);
199 snd_hdac_bus_exit_link_reset(bus
);
200 skl_enable_miscbdcge(bus
->dev
, true);
203 snd_hdac_chip_updatel(bus
, VS_EM2
, AZX_VS_EM2_DUM
, AZX_VS_EM2_DUM
);
206 /* called from IRQ */
207 static void skl_stream_update(struct hdac_bus
*bus
, struct hdac_stream
*hstr
)
209 snd_pcm_period_elapsed(hstr
->substream
);
212 static irqreturn_t
skl_interrupt(int irq
, void *dev_id
)
214 struct hdac_bus
*bus
= dev_id
;
217 if (!pm_runtime_active(bus
->dev
))
220 spin_lock(&bus
->reg_lock
);
222 status
= snd_hdac_chip_readl(bus
, INTSTS
);
223 if (status
== 0 || status
== 0xffffffff) {
224 spin_unlock(&bus
->reg_lock
);
229 status
= snd_hdac_chip_readb(bus
, RIRBSTS
);
230 if (status
& RIRB_INT_MASK
) {
231 if (status
& RIRB_INT_RESPONSE
)
232 snd_hdac_bus_update_rirb(bus
);
233 snd_hdac_chip_writeb(bus
, RIRBSTS
, RIRB_INT_MASK
);
236 spin_unlock(&bus
->reg_lock
);
238 return snd_hdac_chip_readl(bus
, INTSTS
) ? IRQ_WAKE_THREAD
: IRQ_HANDLED
;
241 static irqreturn_t
skl_threaded_handler(int irq
, void *dev_id
)
243 struct hdac_bus
*bus
= dev_id
;
246 status
= snd_hdac_chip_readl(bus
, INTSTS
);
248 snd_hdac_bus_handle_stream_irq(bus
, status
, skl_stream_update
);
253 static int skl_acquire_irq(struct hdac_bus
*bus
, int do_disconnect
)
255 struct skl
*skl
= bus_to_skl(bus
);
258 ret
= request_threaded_irq(skl
->pci
->irq
, skl_interrupt
,
259 skl_threaded_handler
,
261 KBUILD_MODNAME
, bus
);
264 "unable to grab IRQ %d, disabling device\n",
269 bus
->irq
= skl
->pci
->irq
;
270 pci_intx(skl
->pci
, 1);
275 static int skl_suspend_late(struct device
*dev
)
277 struct pci_dev
*pci
= to_pci_dev(dev
);
278 struct hdac_bus
*bus
= pci_get_drvdata(pci
);
279 struct skl
*skl
= bus_to_skl(bus
);
281 return skl_suspend_late_dsp(skl
);
285 static int _skl_suspend(struct hdac_bus
*bus
)
287 struct skl
*skl
= bus_to_skl(bus
);
288 struct pci_dev
*pci
= to_pci_dev(bus
->dev
);
291 snd_hdac_ext_bus_link_power_down_all(bus
);
293 ret
= skl_suspend_dsp(skl
);
297 snd_hdac_bus_stop_chip(bus
);
298 update_pci_dword(pci
, AZX_PCIREG_PGCTL
,
299 AZX_PGCTL_LSRMD_MASK
, AZX_PGCTL_LSRMD_MASK
);
300 skl_enable_miscbdcge(bus
->dev
, false);
301 snd_hdac_bus_enter_link_reset(bus
);
302 skl_enable_miscbdcge(bus
->dev
, true);
303 skl_cleanup_resources(skl
);
308 static int _skl_resume(struct hdac_bus
*bus
)
310 struct skl
*skl
= bus_to_skl(bus
);
314 skl_init_chip(bus
, true);
316 return skl_resume_dsp(skl
);
320 #ifdef CONFIG_PM_SLEEP
324 static int skl_suspend(struct device
*dev
)
326 struct pci_dev
*pci
= to_pci_dev(dev
);
327 struct hdac_bus
*bus
= pci_get_drvdata(pci
);
328 struct skl
*skl
= bus_to_skl(bus
);
332 * Do not suspend if streams which are marked ignore suspend are
333 * running, we need to save the state for these and continue
335 if (skl
->supend_active
) {
336 /* turn off the links and stop the CORB/RIRB DMA if it is On */
337 snd_hdac_ext_bus_link_power_down_all(bus
);
339 if (bus
->cmd_dma_state
)
340 snd_hdac_bus_stop_cmd_io(bus
);
342 enable_irq_wake(bus
->irq
);
345 ret
= _skl_suspend(bus
);
348 skl
->skl_sst
->fw_loaded
= false;
354 static int skl_resume(struct device
*dev
)
356 struct pci_dev
*pci
= to_pci_dev(dev
);
357 struct hdac_bus
*bus
= pci_get_drvdata(pci
);
358 struct skl
*skl
= bus_to_skl(bus
);
359 struct hdac_ext_link
*hlink
= NULL
;
363 * resume only when we are not in suspend active, otherwise need to
366 if (skl
->supend_active
) {
367 pci_restore_state(pci
);
368 snd_hdac_ext_bus_link_power_up_all(bus
);
369 disable_irq_wake(bus
->irq
);
371 * turn On the links which are On before active suspend
372 * and start the CORB/RIRB DMA if On before
375 list_for_each_entry(hlink
, &bus
->hlink_list
, list
) {
376 if (hlink
->ref_count
)
377 snd_hdac_ext_bus_link_power_up(hlink
);
381 if (bus
->cmd_dma_state
)
382 snd_hdac_bus_init_cmd_io(bus
);
384 ret
= _skl_resume(bus
);
386 /* turn off the links which are off before suspend */
387 list_for_each_entry(hlink
, &bus
->hlink_list
, list
) {
388 if (!hlink
->ref_count
)
389 snd_hdac_ext_bus_link_power_down(hlink
);
392 if (!bus
->cmd_dma_state
)
393 snd_hdac_bus_stop_cmd_io(bus
);
398 #endif /* CONFIG_PM_SLEEP */
401 static int skl_runtime_suspend(struct device
*dev
)
403 struct pci_dev
*pci
= to_pci_dev(dev
);
404 struct hdac_bus
*bus
= pci_get_drvdata(pci
);
406 dev_dbg(bus
->dev
, "in %s\n", __func__
);
408 return _skl_suspend(bus
);
411 static int skl_runtime_resume(struct device
*dev
)
413 struct pci_dev
*pci
= to_pci_dev(dev
);
414 struct hdac_bus
*bus
= pci_get_drvdata(pci
);
416 dev_dbg(bus
->dev
, "in %s\n", __func__
);
418 return _skl_resume(bus
);
420 #endif /* CONFIG_PM */
422 static const struct dev_pm_ops skl_pm
= {
423 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend
, skl_resume
)
424 SET_RUNTIME_PM_OPS(skl_runtime_suspend
, skl_runtime_resume
, NULL
)
425 .suspend_late
= skl_suspend_late
,
431 static int skl_free(struct hdac_bus
*bus
)
433 struct skl
*skl
= bus_to_skl(bus
);
435 skl
->init_done
= 0; /* to be sure */
437 snd_hdac_ext_stop_streams(bus
);
440 free_irq(bus
->irq
, (void *)bus
);
441 snd_hdac_bus_free_stream_pages(bus
);
442 snd_hdac_stream_free_all(bus
);
443 snd_hdac_link_free_all(bus
);
446 iounmap(bus
->remap_addr
);
448 pci_release_regions(skl
->pci
);
449 pci_disable_device(skl
->pci
);
451 snd_hdac_ext_bus_exit(bus
);
453 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI
)) {
454 snd_hdac_display_power(bus
, HDA_CODEC_IDX_CONTROLLER
, false);
455 snd_hdac_i915_exit(bus
);
462 * For each ssp there are 3 clocks (mclk/sclk/sclkfs).
463 * e.g. for ssp0, clocks will be named as
464 * "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs"
465 * So for skl+, there are 6 ssps, so 18 clocks will be created.
467 static struct skl_ssp_clk skl_ssp_clks
[] = {
468 {.name
= "ssp0_mclk"}, {.name
= "ssp1_mclk"}, {.name
= "ssp2_mclk"},
469 {.name
= "ssp3_mclk"}, {.name
= "ssp4_mclk"}, {.name
= "ssp5_mclk"},
470 {.name
= "ssp0_sclk"}, {.name
= "ssp1_sclk"}, {.name
= "ssp2_sclk"},
471 {.name
= "ssp3_sclk"}, {.name
= "ssp4_sclk"}, {.name
= "ssp5_sclk"},
472 {.name
= "ssp0_sclkfs"}, {.name
= "ssp1_sclkfs"},
473 {.name
= "ssp2_sclkfs"},
474 {.name
= "ssp3_sclkfs"}, {.name
= "ssp4_sclkfs"},
475 {.name
= "ssp5_sclkfs"},
478 static struct snd_soc_acpi_mach
*skl_find_hda_machine(struct skl
*skl
,
479 struct snd_soc_acpi_mach
*machines
)
481 struct hdac_bus
*bus
= skl_to_bus(skl
);
482 struct snd_soc_acpi_mach
*mach
;
484 /* check if we have any codecs detected on bus */
485 if (bus
->codec_mask
== 0)
488 /* point to common table */
489 mach
= snd_soc_acpi_intel_hda_machines
;
491 /* all entries in the machine table use the same firmware */
492 mach
->fw_filename
= machines
->fw_filename
;
497 static int skl_find_machine(struct skl
*skl
, void *driver_data
)
499 struct hdac_bus
*bus
= skl_to_bus(skl
);
500 struct snd_soc_acpi_mach
*mach
= driver_data
;
501 struct skl_machine_pdata
*pdata
;
503 mach
= snd_soc_acpi_find_machine(mach
);
505 dev_dbg(bus
->dev
, "No matching I2S machine driver found\n");
506 mach
= skl_find_hda_machine(skl
, driver_data
);
508 dev_err(bus
->dev
, "No matching machine driver found\n");
514 skl
->fw_name
= mach
->fw_filename
;
518 skl
->use_tplg_pcm
= pdata
->use_tplg_pcm
;
519 mach
->mach_params
.dmic_num
= skl_get_dmic_geo(skl
);
525 static int skl_machine_device_register(struct skl
*skl
)
527 struct snd_soc_acpi_mach
*mach
= skl
->mach
;
528 struct hdac_bus
*bus
= skl_to_bus(skl
);
529 struct platform_device
*pdev
;
532 pdev
= platform_device_alloc(mach
->drv_name
, -1);
534 dev_err(bus
->dev
, "platform device alloc failed\n");
538 mach
->mach_params
.platform
= dev_name(bus
->dev
);
539 mach
->mach_params
.codec_mask
= bus
->codec_mask
;
541 ret
= platform_device_add_data(pdev
, (const void *)mach
, sizeof(*mach
));
543 dev_err(bus
->dev
, "failed to add machine device platform data\n");
544 platform_device_put(pdev
);
548 ret
= platform_device_add(pdev
);
550 dev_err(bus
->dev
, "failed to add machine device\n");
551 platform_device_put(pdev
);
561 static void skl_machine_device_unregister(struct skl
*skl
)
564 platform_device_unregister(skl
->i2s_dev
);
567 static int skl_dmic_device_register(struct skl
*skl
)
569 struct hdac_bus
*bus
= skl_to_bus(skl
);
570 struct platform_device
*pdev
;
573 /* SKL has one dmic port, so allocate dmic device for this */
574 pdev
= platform_device_alloc("dmic-codec", -1);
576 dev_err(bus
->dev
, "failed to allocate dmic device\n");
580 ret
= platform_device_add(pdev
);
582 dev_err(bus
->dev
, "failed to add dmic device: %d\n", ret
);
583 platform_device_put(pdev
);
586 skl
->dmic_dev
= pdev
;
591 static void skl_dmic_device_unregister(struct skl
*skl
)
594 platform_device_unregister(skl
->dmic_dev
);
597 static struct skl_clk_parent_src skl_clk_src
[] = {
598 { .clk_id
= SKL_XTAL
, .name
= "xtal" },
599 { .clk_id
= SKL_CARDINAL
, .name
= "cardinal", .rate
= 24576000 },
600 { .clk_id
= SKL_PLL
, .name
= "pll", .rate
= 96000000 },
603 struct skl_clk_parent_src
*skl_get_parent_clk(u8 clk_id
)
607 for (i
= 0; i
< ARRAY_SIZE(skl_clk_src
); i
++) {
608 if (skl_clk_src
[i
].clk_id
== clk_id
)
609 return &skl_clk_src
[i
];
615 static void init_skl_xtal_rate(int pci_id
)
620 skl_clk_src
[0].rate
= 24000000;
624 skl_clk_src
[0].rate
= 19200000;
629 static int skl_clock_device_register(struct skl
*skl
)
631 struct platform_device_info pdevinfo
= {NULL
};
632 struct skl_clk_pdata
*clk_pdata
;
634 clk_pdata
= devm_kzalloc(&skl
->pci
->dev
, sizeof(*clk_pdata
),
639 init_skl_xtal_rate(skl
->pci
->device
);
641 clk_pdata
->parent_clks
= skl_clk_src
;
642 clk_pdata
->ssp_clks
= skl_ssp_clks
;
643 clk_pdata
->num_clks
= ARRAY_SIZE(skl_ssp_clks
);
645 /* Query NHLT to fill the rates and parent */
646 skl_get_clks(skl
, clk_pdata
->ssp_clks
);
647 clk_pdata
->pvt_data
= skl
;
649 /* Register Platform device */
650 pdevinfo
.parent
= &skl
->pci
->dev
;
652 pdevinfo
.name
= "skl-ssp-clk";
653 pdevinfo
.data
= clk_pdata
;
654 pdevinfo
.size_data
= sizeof(*clk_pdata
);
655 skl
->clk_dev
= platform_device_register_full(&pdevinfo
);
656 return PTR_ERR_OR_ZERO(skl
->clk_dev
);
659 static void skl_clock_device_unregister(struct skl
*skl
)
662 platform_device_unregister(skl
->clk_dev
);
665 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
667 #define IDISP_INTEL_VENDOR_ID 0x80860000
670 * load the legacy codec driver
672 static void load_codec_module(struct hda_codec
*codec
)
675 char modalias
[MODULE_NAME_LEN
];
676 const char *mod
= NULL
;
678 snd_hdac_codec_modalias(&codec
->core
, modalias
, sizeof(modalias
));
680 dev_dbg(&codec
->core
.dev
, "loading %s codec module\n", mod
);
685 #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */
688 * Probe the given codec address
690 static int probe_codec(struct hdac_bus
*bus
, int addr
)
692 unsigned int cmd
= (addr
<< 28) | (AC_NODE_ROOT
<< 20) |
693 (AC_VERB_PARAMETERS
<< 8) | AC_PAR_VENDOR_ID
;
694 unsigned int res
= -1;
695 struct skl
*skl
= bus_to_skl(bus
);
696 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
697 struct hdac_hda_priv
*hda_codec
;
700 struct hdac_device
*hdev
;
702 mutex_lock(&bus
->cmd_mutex
);
703 snd_hdac_bus_send_cmd(bus
, cmd
);
704 snd_hdac_bus_get_response(bus
, addr
, &res
);
705 mutex_unlock(&bus
->cmd_mutex
);
708 dev_dbg(bus
->dev
, "codec #%d probed OK: %x\n", addr
, res
);
710 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
711 hda_codec
= devm_kzalloc(&skl
->pci
->dev
, sizeof(*hda_codec
),
716 hda_codec
->codec
.bus
= skl_to_hbus(skl
);
717 hdev
= &hda_codec
->codec
.core
;
719 err
= snd_hdac_ext_bus_device_init(bus
, addr
, hdev
);
723 /* use legacy bus only for HDA codecs, idisp uses ext bus */
724 if ((res
& 0xFFFF0000) != IDISP_INTEL_VENDOR_ID
) {
725 hdev
->type
= HDA_DEV_LEGACY
;
726 load_codec_module(&hda_codec
->codec
);
730 hdev
= devm_kzalloc(&skl
->pci
->dev
, sizeof(*hdev
), GFP_KERNEL
);
734 return snd_hdac_ext_bus_device_init(bus
, addr
, hdev
);
735 #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */
738 /* Codec initialization */
739 static void skl_codec_create(struct hdac_bus
*bus
)
743 max_slots
= HDA_MAX_CODECS
;
745 /* First try to probe all given codec slots */
746 for (c
= 0; c
< max_slots
; c
++) {
747 if ((bus
->codec_mask
& (1 << c
))) {
748 if (probe_codec(bus
, c
) < 0) {
750 * Some BIOSen give you wrong codec addresses
754 "Codec #%d probe error; disabling it...\n", c
);
755 bus
->codec_mask
&= ~(1 << c
);
757 * More badly, accessing to a non-existing
758 * codec often screws up the controller bus,
759 * and disturbs the further communications.
760 * Thus if an error occurs during probing,
761 * better to reset the controller bus to get
762 * back to the sanity state.
764 snd_hdac_bus_stop_chip(bus
);
765 skl_init_chip(bus
, true);
771 static const struct hdac_bus_ops bus_core_ops
= {
772 .command
= snd_hdac_bus_send_cmd
,
773 .get_response
= snd_hdac_bus_get_response
,
776 static int skl_i915_init(struct hdac_bus
*bus
)
781 * The HDMI codec is in GPU so we need to ensure that it is powered
782 * up and ready for probe
784 err
= snd_hdac_i915_init(bus
);
788 snd_hdac_display_power(bus
, HDA_CODEC_IDX_CONTROLLER
, true);
793 static void skl_probe_work(struct work_struct
*work
)
795 struct skl
*skl
= container_of(work
, struct skl
, probe_work
);
796 struct hdac_bus
*bus
= skl_to_bus(skl
);
797 struct hdac_ext_link
*hlink
= NULL
;
800 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI
)) {
801 err
= skl_i915_init(bus
);
806 err
= skl_init_chip(bus
, true);
808 dev_err(bus
->dev
, "Init chip failed with err: %d\n", err
);
812 /* codec detection */
813 if (!bus
->codec_mask
)
814 dev_info(bus
->dev
, "no hda codecs found!\n");
816 /* create codec instances */
817 skl_codec_create(bus
);
819 /* register platform dai and controls */
820 err
= skl_platform_register(bus
->dev
);
822 dev_err(bus
->dev
, "platform register failed: %d\n", err
);
826 err
= skl_machine_device_register(skl
);
828 dev_err(bus
->dev
, "machine register failed: %d\n", err
);
833 * we are done probing so decrement link counts
835 list_for_each_entry(hlink
, &bus
->hlink_list
, list
)
836 snd_hdac_ext_bus_link_put(bus
, hlink
);
838 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI
))
839 snd_hdac_display_power(bus
, HDA_CODEC_IDX_CONTROLLER
, false);
842 pm_runtime_put_noidle(bus
->dev
);
843 pm_runtime_allow(bus
->dev
);
849 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI
))
850 snd_hdac_display_power(bus
, HDA_CODEC_IDX_CONTROLLER
, false);
856 static int skl_create(struct pci_dev
*pci
,
857 const struct hdac_io_ops
*io_ops
,
860 struct hdac_ext_bus_ops
*ext_ops
= NULL
;
862 struct hdac_bus
*bus
;
863 struct hda_bus
*hbus
;
868 err
= pci_enable_device(pci
);
872 skl
= devm_kzalloc(&pci
->dev
, sizeof(*skl
), GFP_KERNEL
);
874 pci_disable_device(pci
);
878 hbus
= skl_to_hbus(skl
);
879 bus
= skl_to_bus(skl
);
881 INIT_LIST_HEAD(&skl
->ppl_list
);
882 INIT_LIST_HEAD(&skl
->bind_list
);
884 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
885 ext_ops
= snd_soc_hdac_hda_get_ops();
887 snd_hdac_ext_bus_init(bus
, &pci
->dev
, &bus_core_ops
, io_ops
, ext_ops
);
890 INIT_WORK(&skl
->probe_work
, skl_probe_work
);
891 bus
->bdl_pos_adj
= 0;
893 mutex_init(&hbus
->prepare_mutex
);
895 hbus
->mixer_assigned
= -1;
896 hbus
->modelname
= "sklbus";
903 static int skl_first_init(struct hdac_bus
*bus
)
905 struct skl
*skl
= bus_to_skl(bus
);
906 struct pci_dev
*pci
= skl
->pci
;
909 int cp_streams
, pb_streams
, start_idx
;
911 err
= pci_request_regions(pci
, "Skylake HD audio");
915 bus
->addr
= pci_resource_start(pci
, 0);
916 bus
->remap_addr
= pci_ioremap_bar(pci
, 0);
917 if (bus
->remap_addr
== NULL
) {
918 dev_err(bus
->dev
, "ioremap error\n");
922 snd_hdac_bus_reset_link(bus
, true);
924 snd_hdac_bus_parse_capabilities(bus
);
926 /* check if PPCAP exists */
928 dev_err(bus
->dev
, "bus ppcap not set, HDaudio or DSP not present?\n");
932 if (skl_acquire_irq(bus
, 0) < 0)
936 synchronize_irq(bus
->irq
);
938 gcap
= snd_hdac_chip_readw(bus
, GCAP
);
939 dev_dbg(bus
->dev
, "chipset global capabilities = 0x%x\n", gcap
);
941 /* read number of streams from GCAP register */
942 cp_streams
= (gcap
>> 8) & 0x0f;
943 pb_streams
= (gcap
>> 12) & 0x0f;
945 if (!pb_streams
&& !cp_streams
) {
946 dev_err(bus
->dev
, "no streams found in GCAP definitions?\n");
950 bus
->num_streams
= cp_streams
+ pb_streams
;
952 /* allow 64bit DMA address if supported by H/W */
953 if (!dma_set_mask(bus
->dev
, DMA_BIT_MASK(64))) {
954 dma_set_coherent_mask(bus
->dev
, DMA_BIT_MASK(64));
956 dma_set_mask(bus
->dev
, DMA_BIT_MASK(32));
957 dma_set_coherent_mask(bus
->dev
, DMA_BIT_MASK(32));
960 /* initialize streams */
961 snd_hdac_ext_stream_init_all
962 (bus
, 0, cp_streams
, SNDRV_PCM_STREAM_CAPTURE
);
963 start_idx
= cp_streams
;
964 snd_hdac_ext_stream_init_all
965 (bus
, start_idx
, pb_streams
, SNDRV_PCM_STREAM_PLAYBACK
);
967 err
= snd_hdac_bus_alloc_stream_pages(bus
);
971 /* initialize chip */
975 return skl_init_chip(bus
, true);
978 static int skl_probe(struct pci_dev
*pci
,
979 const struct pci_device_id
*pci_id
)
982 struct hdac_bus
*bus
= NULL
;
985 switch (skl_pci_binding
) {
986 case SND_SKL_PCI_BIND_AUTO
:
988 * detect DSP by checking class/subclass/prog-id information
989 * class=04 subclass 03 prog-if 00: no DSP, use legacy driver
990 * class=04 subclass 01 prog-if 00: DSP is present
991 * (and may be required e.g. for DMIC or SSP support)
992 * class=04 subclass 03 prog-if 80: use DSP or legacy mode
994 if (pci
->class == 0x040300) {
995 dev_info(&pci
->dev
, "The DSP is not enabled on this platform, aborting probe\n");
998 if (pci
->class != 0x040100 && pci
->class != 0x040380) {
999 dev_err(&pci
->dev
, "Unknown PCI class/subclass/prog-if information (0x%06x) found, aborting probe\n", pci
->class);
1002 dev_info(&pci
->dev
, "DSP detected with PCI class/subclass/prog-if info 0x%06x\n", pci
->class);
1004 case SND_SKL_PCI_BIND_LEGACY
:
1005 dev_info(&pci
->dev
, "Module parameter forced binding with HDaudio legacy, aborting probe\n");
1007 case SND_SKL_PCI_BIND_ASOC
:
1008 dev_info(&pci
->dev
, "Module parameter forced binding with SKL driver, bypassed detection logic\n");
1011 dev_err(&pci
->dev
, "invalid value for skl_pci_binding module parameter, ignored\n");
1015 /* we use ext core ops, so provide NULL for ops here */
1016 err
= skl_create(pci
, NULL
, &skl
);
1020 bus
= skl_to_bus(skl
);
1022 err
= skl_first_init(bus
);
1024 dev_err(bus
->dev
, "skl_first_init failed with err: %d\n", err
);
1028 skl
->pci_id
= pci
->device
;
1030 device_disable_async_suspend(bus
->dev
);
1032 skl
->nhlt
= skl_nhlt_init(bus
->dev
);
1034 if (skl
->nhlt
== NULL
) {
1035 #if !IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
1036 dev_err(bus
->dev
, "no nhlt info found\n");
1040 dev_warn(bus
->dev
, "no nhlt info found, continuing to try to enable HDaudio codec\n");
1044 err
= skl_nhlt_create_sysfs(skl
);
1046 dev_err(bus
->dev
, "skl_nhlt_create_sysfs failed with err: %d\n", err
);
1050 skl_nhlt_update_topology_bin(skl
);
1052 /* create device for dsp clk */
1053 err
= skl_clock_device_register(skl
);
1055 dev_err(bus
->dev
, "skl_clock_device_register failed with err: %d\n", err
);
1060 pci_set_drvdata(skl
->pci
, bus
);
1063 err
= skl_find_machine(skl
, (void *)pci_id
->driver_data
);
1065 dev_err(bus
->dev
, "skl_find_machine failed with err: %d\n", err
);
1069 err
= skl_init_dsp(skl
);
1071 dev_dbg(bus
->dev
, "error failed to register dsp\n");
1074 skl
->skl_sst
->enable_miscbdcge
= skl_enable_miscbdcge
;
1075 skl
->skl_sst
->clock_power_gating
= skl_clock_power_gating
;
1078 snd_hdac_ext_bus_get_ml_capabilities(bus
);
1080 snd_hdac_bus_stop_chip(bus
);
1082 /* create device for soc dmic */
1083 err
= skl_dmic_device_register(skl
);
1085 dev_err(bus
->dev
, "skl_dmic_device_register failed with err: %d\n", err
);
1089 schedule_work(&skl
->probe_work
);
1096 skl_clock_device_unregister(skl
);
1098 skl_nhlt_free(skl
->nhlt
);
1105 static void skl_shutdown(struct pci_dev
*pci
)
1107 struct hdac_bus
*bus
= pci_get_drvdata(pci
);
1108 struct hdac_stream
*s
;
1109 struct hdac_ext_stream
*stream
;
1115 skl
= bus_to_skl(bus
);
1117 if (!skl
->init_done
)
1120 snd_hdac_ext_stop_streams(bus
);
1121 list_for_each_entry(s
, &bus
->stream_list
, list
) {
1122 stream
= stream_to_hdac_ext_stream(s
);
1123 snd_hdac_ext_stream_decouple(bus
, stream
, false);
1126 snd_hdac_bus_stop_chip(bus
);
1129 static void skl_remove(struct pci_dev
*pci
)
1131 struct hdac_bus
*bus
= pci_get_drvdata(pci
);
1132 struct skl
*skl
= bus_to_skl(bus
);
1134 cancel_work_sync(&skl
->probe_work
);
1136 pm_runtime_get_noresume(&pci
->dev
);
1138 /* codec removal, invoke bus_device_remove */
1139 snd_hdac_ext_bus_device_remove(bus
);
1141 skl_platform_unregister(&pci
->dev
);
1143 skl_machine_device_unregister(skl
);
1144 skl_dmic_device_unregister(skl
);
1145 skl_clock_device_unregister(skl
);
1146 skl_nhlt_remove_sysfs(skl
);
1147 skl_nhlt_free(skl
->nhlt
);
1149 dev_set_drvdata(&pci
->dev
, NULL
);
1153 static const struct pci_device_id skl_ids
[] = {
1154 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKL)
1155 /* Sunrise Point-LP */
1156 { PCI_DEVICE(0x8086, 0x9d70),
1157 .driver_data
= (unsigned long)&snd_soc_acpi_intel_skl_machines
},
1159 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_APL)
1161 { PCI_DEVICE(0x8086, 0x5a98),
1162 .driver_data
= (unsigned long)&snd_soc_acpi_intel_bxt_machines
},
1164 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_KBL)
1166 { PCI_DEVICE(0x8086, 0x9D71),
1167 .driver_data
= (unsigned long)&snd_soc_acpi_intel_kbl_machines
},
1169 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_GLK)
1171 { PCI_DEVICE(0x8086, 0x3198),
1172 .driver_data
= (unsigned long)&snd_soc_acpi_intel_glk_machines
},
1174 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CNL)
1176 { PCI_DEVICE(0x8086, 0x9dc8),
1177 .driver_data
= (unsigned long)&snd_soc_acpi_intel_cnl_machines
},
1179 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CFL)
1181 { PCI_DEVICE(0x8086, 0xa348),
1182 .driver_data
= (unsigned long)&snd_soc_acpi_intel_cnl_machines
},
1184 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_LP)
1186 { PCI_DEVICE(0x8086, 0x02c8),
1187 .driver_data
= (unsigned long)&snd_soc_acpi_intel_cnl_machines
},
1189 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_H)
1191 { PCI_DEVICE(0x8086, 0x06c8),
1192 .driver_data
= (unsigned long)&snd_soc_acpi_intel_cnl_machines
},
1196 MODULE_DEVICE_TABLE(pci
, skl_ids
);
1198 /* pci_driver definition */
1199 static struct pci_driver skl_driver
= {
1200 .name
= KBUILD_MODNAME
,
1201 .id_table
= skl_ids
,
1203 .remove
= skl_remove
,
1204 .shutdown
= skl_shutdown
,
1209 module_pci_driver(skl_driver
);
1211 MODULE_LICENSE("GPL v2");
1212 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver");