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1 /*
2 * skl.c - Implementation of ASoC Intel SKL HD Audio driver
3 *
4 * Copyright (C) 2014-2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 *
7 * Derived mostly from Intel HDA driver with following copyrights:
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
22 */
23
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/platform_device.h>
28 #include <linux/firmware.h>
29 #include <sound/pcm.h>
30 #include "../common/sst-acpi.h"
31 #include "skl.h"
32 #include "skl-sst-dsp.h"
33 #include "skl-sst-ipc.h"
34
35 /*
36 * initialize the PCI registers
37 */
38 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg,
39 unsigned char mask, unsigned char val)
40 {
41 unsigned char data;
42
43 pci_read_config_byte(pci, reg, &data);
44 data &= ~mask;
45 data |= (val & mask);
46 pci_write_config_byte(pci, reg, data);
47 }
48
49 static void skl_init_pci(struct skl *skl)
50 {
51 struct hdac_ext_bus *ebus = &skl->ebus;
52
53 /*
54 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
55 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
56 * Ensuring these bits are 0 clears playback static on some HD Audio
57 * codecs.
58 * The PCI register TCSEL is defined in the Intel manuals.
59 */
60 dev_dbg(ebus_to_hbus(ebus)->dev, "Clearing TCSEL\n");
61 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0);
62 }
63
64 static void update_pci_dword(struct pci_dev *pci,
65 unsigned int reg, u32 mask, u32 val)
66 {
67 u32 data = 0;
68
69 pci_read_config_dword(pci, reg, &data);
70 data &= ~mask;
71 data |= (val & mask);
72 pci_write_config_dword(pci, reg, data);
73 }
74
75 /*
76 * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits
77 *
78 * @dev: device pointer
79 * @enable: enable/disable flag
80 */
81 static void skl_enable_miscbdcge(struct device *dev, bool enable)
82 {
83 struct pci_dev *pci = to_pci_dev(dev);
84 u32 val;
85
86 val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0;
87
88 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val);
89 }
90
91 /*
92 * While performing reset, controller may not come back properly causing
93 * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset
94 * (init chip) and then again set CGCTL.MISCBDCGE to 1
95 */
96 static int skl_init_chip(struct hdac_bus *bus, bool full_reset)
97 {
98 int ret;
99
100 skl_enable_miscbdcge(bus->dev, false);
101 ret = snd_hdac_bus_init_chip(bus, full_reset);
102 skl_enable_miscbdcge(bus->dev, true);
103
104 return ret;
105 }
106
107 /* called from IRQ */
108 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)
109 {
110 snd_pcm_period_elapsed(hstr->substream);
111 }
112
113 static irqreturn_t skl_interrupt(int irq, void *dev_id)
114 {
115 struct hdac_ext_bus *ebus = dev_id;
116 struct hdac_bus *bus = ebus_to_hbus(ebus);
117 u32 status;
118
119 if (!pm_runtime_active(bus->dev))
120 return IRQ_NONE;
121
122 spin_lock(&bus->reg_lock);
123
124 status = snd_hdac_chip_readl(bus, INTSTS);
125 if (status == 0 || status == 0xffffffff) {
126 spin_unlock(&bus->reg_lock);
127 return IRQ_NONE;
128 }
129
130 /* clear rirb int */
131 status = snd_hdac_chip_readb(bus, RIRBSTS);
132 if (status & RIRB_INT_MASK) {
133 if (status & RIRB_INT_RESPONSE)
134 snd_hdac_bus_update_rirb(bus);
135 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
136 }
137
138 spin_unlock(&bus->reg_lock);
139
140 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
141 }
142
143 static irqreturn_t skl_threaded_handler(int irq, void *dev_id)
144 {
145 struct hdac_ext_bus *ebus = dev_id;
146 struct hdac_bus *bus = ebus_to_hbus(ebus);
147 u32 status;
148
149 status = snd_hdac_chip_readl(bus, INTSTS);
150
151 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update);
152
153 return IRQ_HANDLED;
154 }
155
156 static int skl_acquire_irq(struct hdac_ext_bus *ebus, int do_disconnect)
157 {
158 struct skl *skl = ebus_to_skl(ebus);
159 struct hdac_bus *bus = ebus_to_hbus(ebus);
160 int ret;
161
162 ret = request_threaded_irq(skl->pci->irq, skl_interrupt,
163 skl_threaded_handler,
164 IRQF_SHARED,
165 KBUILD_MODNAME, ebus);
166 if (ret) {
167 dev_err(bus->dev,
168 "unable to grab IRQ %d, disabling device\n",
169 skl->pci->irq);
170 return ret;
171 }
172
173 bus->irq = skl->pci->irq;
174 pci_intx(skl->pci, 1);
175
176 return 0;
177 }
178
179 #ifdef CONFIG_PM
180 static int _skl_suspend(struct hdac_ext_bus *ebus)
181 {
182 struct skl *skl = ebus_to_skl(ebus);
183 struct hdac_bus *bus = ebus_to_hbus(ebus);
184 int ret;
185
186 snd_hdac_ext_bus_link_power_down_all(ebus);
187
188 ret = skl_suspend_dsp(skl);
189 if (ret < 0)
190 return ret;
191
192 snd_hdac_bus_stop_chip(bus);
193 skl_enable_miscbdcge(bus->dev, false);
194 snd_hdac_bus_enter_link_reset(bus);
195 skl_enable_miscbdcge(bus->dev, true);
196
197 return 0;
198 }
199
200 static int _skl_resume(struct hdac_ext_bus *ebus)
201 {
202 struct skl *skl = ebus_to_skl(ebus);
203 struct hdac_bus *bus = ebus_to_hbus(ebus);
204
205 skl_init_pci(skl);
206 skl_init_chip(bus, true);
207
208 return skl_resume_dsp(skl);
209 }
210 #endif
211
212 #ifdef CONFIG_PM_SLEEP
213 /*
214 * power management
215 */
216 static int skl_suspend(struct device *dev)
217 {
218 struct pci_dev *pci = to_pci_dev(dev);
219 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
220 struct skl *skl = ebus_to_skl(ebus);
221
222 /*
223 * Do not suspend if streams which are marked ignore suspend are
224 * running, we need to save the state for these and continue
225 */
226 if (skl->supend_active) {
227 snd_hdac_ext_bus_link_power_down_all(ebus);
228 pci_save_state(pci);
229 pci_disable_device(pci);
230 return 0;
231 } else {
232 return _skl_suspend(ebus);
233 }
234 }
235
236 static int skl_resume(struct device *dev)
237 {
238 struct pci_dev *pci = to_pci_dev(dev);
239 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
240 struct skl *skl = ebus_to_skl(ebus);
241 int ret;
242
243 /*
244 * resume only when we are not in suspend active, otherwise need to
245 * restore the device
246 */
247 if (skl->supend_active) {
248 pci_restore_state(pci);
249 ret = pci_enable_device(pci);
250 snd_hdac_ext_bus_link_power_up_all(ebus);
251 } else {
252 ret = _skl_resume(ebus);
253 }
254
255 return ret;
256 }
257 #endif /* CONFIG_PM_SLEEP */
258
259 #ifdef CONFIG_PM
260 static int skl_runtime_suspend(struct device *dev)
261 {
262 struct pci_dev *pci = to_pci_dev(dev);
263 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
264 struct hdac_bus *bus = ebus_to_hbus(ebus);
265
266 dev_dbg(bus->dev, "in %s\n", __func__);
267
268 return _skl_suspend(ebus);
269 }
270
271 static int skl_runtime_resume(struct device *dev)
272 {
273 struct pci_dev *pci = to_pci_dev(dev);
274 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
275 struct hdac_bus *bus = ebus_to_hbus(ebus);
276
277 dev_dbg(bus->dev, "in %s\n", __func__);
278
279 return _skl_resume(ebus);
280 }
281 #endif /* CONFIG_PM */
282
283 static const struct dev_pm_ops skl_pm = {
284 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume)
285 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL)
286 };
287
288 /*
289 * destructor
290 */
291 static int skl_free(struct hdac_ext_bus *ebus)
292 {
293 struct skl *skl = ebus_to_skl(ebus);
294 struct hdac_bus *bus = ebus_to_hbus(ebus);
295
296 skl->init_failed = 1; /* to be sure */
297
298 snd_hdac_ext_stop_streams(ebus);
299
300 if (bus->irq >= 0)
301 free_irq(bus->irq, (void *)bus);
302 if (bus->remap_addr)
303 iounmap(bus->remap_addr);
304
305 snd_hdac_bus_free_stream_pages(bus);
306 snd_hdac_stream_free_all(ebus);
307 snd_hdac_link_free_all(ebus);
308 pci_release_regions(skl->pci);
309 pci_disable_device(skl->pci);
310
311 snd_hdac_ext_bus_exit(ebus);
312
313 return 0;
314 }
315
316 static int skl_machine_device_register(struct skl *skl, void *driver_data)
317 {
318 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus);
319 struct platform_device *pdev;
320 struct sst_acpi_mach *mach = driver_data;
321 int ret;
322
323 mach = sst_acpi_find_machine(mach);
324 if (mach == NULL) {
325 dev_err(bus->dev, "No matching machine driver found\n");
326 return -ENODEV;
327 }
328 skl->fw_name = mach->fw_filename;
329
330 pdev = platform_device_alloc(mach->drv_name, -1);
331 if (pdev == NULL) {
332 dev_err(bus->dev, "platform device alloc failed\n");
333 return -EIO;
334 }
335
336 ret = platform_device_add(pdev);
337 if (ret) {
338 dev_err(bus->dev, "failed to add machine device\n");
339 platform_device_put(pdev);
340 return -EIO;
341 }
342 skl->i2s_dev = pdev;
343
344 return 0;
345 }
346
347 static void skl_machine_device_unregister(struct skl *skl)
348 {
349 if (skl->i2s_dev)
350 platform_device_unregister(skl->i2s_dev);
351 }
352
353 static int skl_dmic_device_register(struct skl *skl)
354 {
355 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus);
356 struct platform_device *pdev;
357 int ret;
358
359 /* SKL has one dmic port, so allocate dmic device for this */
360 pdev = platform_device_alloc("dmic-codec", -1);
361 if (!pdev) {
362 dev_err(bus->dev, "failed to allocate dmic device\n");
363 return -ENOMEM;
364 }
365
366 ret = platform_device_add(pdev);
367 if (ret) {
368 dev_err(bus->dev, "failed to add dmic device: %d\n", ret);
369 platform_device_put(pdev);
370 return ret;
371 }
372 skl->dmic_dev = pdev;
373
374 return 0;
375 }
376
377 static void skl_dmic_device_unregister(struct skl *skl)
378 {
379 if (skl->dmic_dev)
380 platform_device_unregister(skl->dmic_dev);
381 }
382
383 /*
384 * Probe the given codec address
385 */
386 static int probe_codec(struct hdac_ext_bus *ebus, int addr)
387 {
388 struct hdac_bus *bus = ebus_to_hbus(ebus);
389 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
390 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
391 unsigned int res;
392
393 mutex_lock(&bus->cmd_mutex);
394 snd_hdac_bus_send_cmd(bus, cmd);
395 snd_hdac_bus_get_response(bus, addr, &res);
396 mutex_unlock(&bus->cmd_mutex);
397 if (res == -1)
398 return -EIO;
399 dev_dbg(bus->dev, "codec #%d probed OK\n", addr);
400
401 return snd_hdac_ext_bus_device_init(ebus, addr);
402 }
403
404 /* Codec initialization */
405 static int skl_codec_create(struct hdac_ext_bus *ebus)
406 {
407 struct hdac_bus *bus = ebus_to_hbus(ebus);
408 int c, max_slots;
409
410 max_slots = HDA_MAX_CODECS;
411
412 /* First try to probe all given codec slots */
413 for (c = 0; c < max_slots; c++) {
414 if ((bus->codec_mask & (1 << c))) {
415 if (probe_codec(ebus, c) < 0) {
416 /*
417 * Some BIOSen give you wrong codec addresses
418 * that don't exist
419 */
420 dev_warn(bus->dev,
421 "Codec #%d probe error; disabling it...\n", c);
422 bus->codec_mask &= ~(1 << c);
423 /*
424 * More badly, accessing to a non-existing
425 * codec often screws up the controller bus,
426 * and disturbs the further communications.
427 * Thus if an error occurs during probing,
428 * better to reset the controller bus to get
429 * back to the sanity state.
430 */
431 snd_hdac_bus_stop_chip(bus);
432 skl_init_chip(bus, true);
433 }
434 }
435 }
436
437 return 0;
438 }
439
440 static const struct hdac_bus_ops bus_core_ops = {
441 .command = snd_hdac_bus_send_cmd,
442 .get_response = snd_hdac_bus_get_response,
443 };
444
445 /*
446 * constructor
447 */
448 static int skl_create(struct pci_dev *pci,
449 const struct hdac_io_ops *io_ops,
450 struct skl **rskl)
451 {
452 struct skl *skl;
453 struct hdac_ext_bus *ebus;
454
455 int err;
456
457 *rskl = NULL;
458
459 err = pci_enable_device(pci);
460 if (err < 0)
461 return err;
462
463 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL);
464 if (!skl) {
465 pci_disable_device(pci);
466 return -ENOMEM;
467 }
468 ebus = &skl->ebus;
469 snd_hdac_ext_bus_init(ebus, &pci->dev, &bus_core_ops, io_ops);
470 ebus->bus.use_posbuf = 1;
471 skl->pci = pci;
472
473 ebus->bus.bdl_pos_adj = 0;
474
475 *rskl = skl;
476
477 return 0;
478 }
479
480 static int skl_first_init(struct hdac_ext_bus *ebus)
481 {
482 struct skl *skl = ebus_to_skl(ebus);
483 struct hdac_bus *bus = ebus_to_hbus(ebus);
484 struct pci_dev *pci = skl->pci;
485 int err;
486 unsigned short gcap;
487 int cp_streams, pb_streams, start_idx;
488
489 err = pci_request_regions(pci, "Skylake HD audio");
490 if (err < 0)
491 return err;
492
493 bus->addr = pci_resource_start(pci, 0);
494 bus->remap_addr = pci_ioremap_bar(pci, 0);
495 if (bus->remap_addr == NULL) {
496 dev_err(bus->dev, "ioremap error\n");
497 return -ENXIO;
498 }
499
500 snd_hdac_ext_bus_parse_capabilities(ebus);
501
502 if (skl_acquire_irq(ebus, 0) < 0)
503 return -EBUSY;
504
505 pci_set_master(pci);
506 synchronize_irq(bus->irq);
507
508 gcap = snd_hdac_chip_readw(bus, GCAP);
509 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap);
510
511 /* allow 64bit DMA address if supported by H/W */
512 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) {
513 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64));
514 } else {
515 dma_set_mask(bus->dev, DMA_BIT_MASK(32));
516 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32));
517 }
518
519 /* read number of streams from GCAP register */
520 cp_streams = (gcap >> 8) & 0x0f;
521 pb_streams = (gcap >> 12) & 0x0f;
522
523 if (!pb_streams && !cp_streams)
524 return -EIO;
525
526 ebus->num_streams = cp_streams + pb_streams;
527
528 /* initialize streams */
529 snd_hdac_ext_stream_init_all
530 (ebus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE);
531 start_idx = cp_streams;
532 snd_hdac_ext_stream_init_all
533 (ebus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK);
534
535 err = snd_hdac_bus_alloc_stream_pages(bus);
536 if (err < 0)
537 return err;
538
539 /* initialize chip */
540 skl_init_pci(skl);
541
542 skl_init_chip(bus, true);
543
544 /* codec detection */
545 if (!bus->codec_mask) {
546 dev_info(bus->dev, "no hda codecs found!\n");
547 }
548
549 return 0;
550 }
551
552 static int skl_probe(struct pci_dev *pci,
553 const struct pci_device_id *pci_id)
554 {
555 struct skl *skl;
556 struct hdac_ext_bus *ebus = NULL;
557 struct hdac_bus *bus = NULL;
558 int err;
559
560 /* we use ext core ops, so provide NULL for ops here */
561 err = skl_create(pci, NULL, &skl);
562 if (err < 0)
563 return err;
564
565 ebus = &skl->ebus;
566 bus = ebus_to_hbus(ebus);
567
568 err = skl_first_init(ebus);
569 if (err < 0)
570 goto out_free;
571
572 skl->nhlt = skl_nhlt_init(bus->dev);
573
574 if (skl->nhlt == NULL)
575 goto out_free;
576
577 pci_set_drvdata(skl->pci, ebus);
578
579 /* check if dsp is there */
580 if (ebus->ppcap) {
581 err = skl_machine_device_register(skl,
582 (void *)pci_id->driver_data);
583 if (err < 0)
584 goto out_free;
585
586 err = skl_init_dsp(skl);
587 if (err < 0) {
588 dev_dbg(bus->dev, "error failed to register dsp\n");
589 goto out_mach_free;
590 }
591 skl->skl_sst->enable_miscbdcge = skl_enable_miscbdcge;
592
593 }
594 if (ebus->mlcap)
595 snd_hdac_ext_bus_get_ml_capabilities(ebus);
596
597 /* create device for soc dmic */
598 err = skl_dmic_device_register(skl);
599 if (err < 0)
600 goto out_dsp_free;
601
602 /* register platform dai and controls */
603 err = skl_platform_register(bus->dev);
604 if (err < 0)
605 goto out_dmic_free;
606
607 /* create codec instances */
608 err = skl_codec_create(ebus);
609 if (err < 0)
610 goto out_unregister;
611
612 /*configure PM */
613 pm_runtime_set_autosuspend_delay(bus->dev, SKL_SUSPEND_DELAY);
614 pm_runtime_use_autosuspend(bus->dev);
615 pm_runtime_put_noidle(bus->dev);
616 pm_runtime_allow(bus->dev);
617
618 return 0;
619
620 out_unregister:
621 skl_platform_unregister(bus->dev);
622 out_dmic_free:
623 skl_dmic_device_unregister(skl);
624 out_dsp_free:
625 skl_free_dsp(skl);
626 out_mach_free:
627 skl_machine_device_unregister(skl);
628 out_free:
629 skl->init_failed = 1;
630 skl_free(ebus);
631
632 return err;
633 }
634
635 static void skl_remove(struct pci_dev *pci)
636 {
637 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
638 struct skl *skl = ebus_to_skl(ebus);
639
640 if (skl->tplg)
641 release_firmware(skl->tplg);
642
643 if (pci_dev_run_wake(pci))
644 pm_runtime_get_noresume(&pci->dev);
645 pci_dev_put(pci);
646 skl_platform_unregister(&pci->dev);
647 skl_free_dsp(skl);
648 skl_machine_device_unregister(skl);
649 skl_dmic_device_unregister(skl);
650 skl_free(ebus);
651 dev_set_drvdata(&pci->dev, NULL);
652 }
653
654 static struct sst_acpi_mach sst_skl_devdata[] = {
655 { "INT343A", "skl_alc286s_i2s", "intel/dsp_fw_release.bin", NULL, NULL, NULL },
656 { "INT343B", "skl_nau88l25_ssm4567_i2s", "intel/dsp_fw_release.bin",
657 NULL, NULL, NULL },
658 { "MX98357A", "skl_nau88l25_max98357a_i2s", "intel/dsp_fw_release.bin",
659 NULL, NULL, NULL },
660 {}
661 };
662
663 /* PCI IDs */
664 static const struct pci_device_id skl_ids[] = {
665 /* Sunrise Point-LP */
666 { PCI_DEVICE(0x8086, 0x9d70),
667 .driver_data = (unsigned long)&sst_skl_devdata},
668 { 0, }
669 };
670 MODULE_DEVICE_TABLE(pci, skl_ids);
671
672 /* pci_driver definition */
673 static struct pci_driver skl_driver = {
674 .name = KBUILD_MODNAME,
675 .id_table = skl_ids,
676 .probe = skl_probe,
677 .remove = skl_remove,
678 .driver = {
679 .pm = &skl_pm,
680 },
681 };
682 module_pci_driver(skl_driver);
683
684 MODULE_LICENSE("GPL v2");
685 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver");