sound/soc/omap/omap-mcbsp.c

   1 /*
   2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
   7  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <sound/core.h>
  30 #include <sound/pcm.h>
  31 #include <sound/pcm_params.h>
  32 #include <sound/initval.h>
  33 #include <sound/soc.h>
  34
  35 #include <plat/dma.h>
  36 #include <plat/mcbsp.h>
  37 #include "mcbsp.h"
  38 #include "omap-mcbsp.h"
  39 #include "omap-pcm.h"
  40
  41 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
  42
  43 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
  44         xhandler_get, xhandler_put) \
  45 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  46         .info = omap_mcbsp_st_info_volsw, \
  47         .get = xhandler_get, .put = xhandler_put, \
  48         .private_value = (unsigned long) &(struct soc_mixer_control) \
  49         {.min = xmin, .max = xmax} }
  50
  51 enum {
  52         OMAP_MCBSP_WORD_8 = 0,
  53         OMAP_MCBSP_WORD_12,
  54         OMAP_MCBSP_WORD_16,
  55         OMAP_MCBSP_WORD_20,
  56         OMAP_MCBSP_WORD_24,
  57         OMAP_MCBSP_WORD_32,
  58 };
  59
  60 /*
  61  * Stream DMA parameters. DMA request line and port address are set runtime
  62  * since they are different between OMAP1 and later OMAPs
  63  */
  64 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
  65 {
  66         struct snd_soc_pcm_runtime *rtd = substream->private_data;
  67         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  68         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  69         struct omap_pcm_dma_data *dma_data;
  70         int words;
  71
  72         dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
  73
  74         /*
  75          * Configure McBSP threshold based on either:
  76          * packet_size, when the sDMA is in packet mode, or based on the
  77          * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
  78          * for mono streams.
  79          */
  80         if (dma_data->packet_size)
  81                 words = dma_data->packet_size;
  82         else if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
  83                 words = snd_pcm_lib_period_bytes(substream) /
  84                                                 (mcbsp->wlen / 8);
  85         else
  86                 words = 1;
  87
  88         /* Configure McBSP internal buffer usage */
  89         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  90                 omap_mcbsp_set_tx_threshold(mcbsp, words);
  91         else
  92                 omap_mcbsp_set_rx_threshold(mcbsp, words);
  93 }
  94
  95 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
  96                                     struct snd_pcm_hw_rule *rule)
  97 {
  98         struct snd_interval *buffer_size = hw_param_interval(params,
  99                                         SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
 100         struct snd_interval *channels = hw_param_interval(params,
 101                                         SNDRV_PCM_HW_PARAM_CHANNELS);
 102         struct omap_mcbsp *mcbsp = rule->private;
 103         struct snd_interval frames;
 104         int size;
 105
 106         snd_interval_any(&frames);
 107         size = mcbsp->pdata->buffer_size;
 108
 109         frames.min = size / channels->min;
 110         frames.integer = 1;
 111         return snd_interval_refine(buffer_size, &frames);
 112 }
 113
 114 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 115                                   struct snd_soc_dai *cpu_dai)
 116 {
 117         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 118         int err = 0;
 119
 120         if (!cpu_dai->active)
 121                 err = omap_mcbsp_request(mcbsp);
 122
 123         /*
 124          * OMAP3 McBSP FIFO is word structured.
 125          * McBSP2 has 1024 + 256 = 1280 word long buffer,
 126          * McBSP1,3,4,5 has 128 word long buffer
 127          * This means that the size of the FIFO depends on the sample format.
 128          * For example on McBSP3:
 129          * 16bit samples: size is 128 * 2 = 256 bytes
 130          * 32bit samples: size is 128 * 4 = 512 bytes
 131          * It is simpler to place constraint for buffer and period based on
 132          * channels.
 133          * McBSP3 as example again (16 or 32 bit samples):
 134          * 1 channel (mono): size is 128 frames (128 words)
 135          * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
 136          * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
 137          */
 138         if (mcbsp->pdata->buffer_size) {
 139                 /*
 140                 * Rule for the buffer size. We should not allow
 141                 * smaller buffer than the FIFO size to avoid underruns.
 142                 * This applies only for the playback stream.
 143                 */
 144                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 145                         snd_pcm_hw_rule_add(substream->runtime, 0,
 146                                             SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 147                                             omap_mcbsp_hwrule_min_buffersize,
 148                                             mcbsp,
 149                                             SNDRV_PCM_HW_PARAM_CHANNELS, -1);
 150
 151                 /* Make sure, that the period size is always even */
 152                 snd_pcm_hw_constraint_step(substream->runtime, 0,
 153                                            SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
 154         }
 155
 156         return err;
 157 }
 158
 159 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
 160                                     struct snd_soc_dai *cpu_dai)
 161 {
 162         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 163
 164         if (!cpu_dai->active) {
 165                 omap_mcbsp_free(mcbsp);
 166                 mcbsp->configured = 0;
 167         }
 168 }
 169
 170 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
 171                                   struct snd_soc_dai *cpu_dai)
 172 {
 173         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 174         int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 175
 176         switch (cmd) {
 177         case SNDRV_PCM_TRIGGER_START:
 178         case SNDRV_PCM_TRIGGER_RESUME:
 179         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 180                 mcbsp->active++;
 181                 omap_mcbsp_start(mcbsp, play, !play);
 182                 break;
 183
 184         case SNDRV_PCM_TRIGGER_STOP:
 185         case SNDRV_PCM_TRIGGER_SUSPEND:
 186         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 187                 omap_mcbsp_stop(mcbsp, play, !play);
 188                 mcbsp->active--;
 189                 break;
 190         default:
 191                 err = -EINVAL;
 192         }
 193
 194         return err;
 195 }
 196
 197 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
 198                         struct snd_pcm_substream *substream,
 199                         struct snd_soc_dai *dai)
 200 {
 201         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 202         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 203         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 204         u16 fifo_use;
 205         snd_pcm_sframes_t delay;
 206
 207         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 208                 fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
 209         else
 210                 fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
 211
 212         /*
 213          * Divide the used locations with the channel count to get the
 214          * FIFO usage in samples (don't care about partial samples in the
 215          * buffer).
 216          */
 217         delay = fifo_use / substream->runtime->channels;
 218
 219         return delay;
 220 }
 221
 222 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 223                                     struct snd_pcm_hw_params *params,
 224                                     struct snd_soc_dai *cpu_dai)
 225 {
 226         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 227         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 228         struct omap_pcm_dma_data *dma_data;
 229         int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
 230         int pkt_size = 0;
 231         unsigned int format, div, framesize, master;
 232
 233         dma_data = &mcbsp->dma_data[substream->stream];
 234         channels = params_channels(params);
 235
 236         switch (params_format(params)) {
 237         case SNDRV_PCM_FORMAT_S16_LE:
 238                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S16;
 239                 wlen = 16;
 240                 break;
 241         case SNDRV_PCM_FORMAT_S32_LE:
 242                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S32;
 243                 wlen = 32;
 244                 break;
 245         default:
 246                 return -EINVAL;
 247         }
 248         if (mcbsp->pdata->buffer_size) {
 249                 dma_data->set_threshold = omap_mcbsp_set_threshold;
 250                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
 251                         int period_words, max_thrsh;
 252
 253                         period_words = params_period_bytes(params) / (wlen / 8);
 254                         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 255                                 max_thrsh = mcbsp->max_tx_thres;
 256                         else
 257                                 max_thrsh = mcbsp->max_rx_thres;
 258                         /*
 259                          * If the period contains less or equal number of words,
 260                          * we are using the original threshold mode setup:
 261                          * McBSP threshold = sDMA frame size = period_size
 262                          * Otherwise we switch to sDMA packet mode:
 263                          * McBSP threshold = sDMA packet size
 264                          * sDMA frame size = period size
 265                          */
 266                         if (period_words > max_thrsh) {
 267                                 int divider = 0;
 268
 269                                 /*
 270                                  * Look for the biggest threshold value, which
 271                                  * divides the period size evenly.
 272                                  */
 273                                 divider = period_words / max_thrsh;
 274                                 if (period_words % max_thrsh)
 275                                         divider++;
 276                                 while (period_words % divider &&
 277                                         divider < period_words)
 278                                         divider++;
 279                                 if (divider == period_words)
 280                                         return -EINVAL;
 281
 282                                 pkt_size = period_words / divider;
 283                                 sync_mode = OMAP_DMA_SYNC_PACKET;
 284                         } else {
 285                                 sync_mode = OMAP_DMA_SYNC_FRAME;
 286                         }
 287                 } else if (channels > 1) {
 288                         /* Use packet mode for non mono streams */
 289                         pkt_size = channels;
 290                         sync_mode = OMAP_DMA_SYNC_PACKET;
 291                 }
 292         }
 293
 294         dma_data->sync_mode = sync_mode;
 295         dma_data->packet_size = pkt_size;
 296
 297         snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
 298
 299         if (mcbsp->configured) {
 300                 /* McBSP already configured by another stream */
 301                 return 0;
 302         }
 303
 304         regs->rcr2      &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
 305         regs->xcr2      &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
 306         regs->rcr1      &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
 307         regs->xcr1      &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
 308         format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 309         wpf = channels;
 310         if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
 311                               format == SND_SOC_DAIFMT_LEFT_J)) {
 312                 /* Use dual-phase frames */
 313                 regs->rcr2      |= RPHASE;
 314                 regs->xcr2      |= XPHASE;
 315                 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
 316                 wpf--;
 317                 regs->rcr2      |= RFRLEN2(wpf - 1);
 318                 regs->xcr2      |= XFRLEN2(wpf - 1);
 319         }
 320
 321         regs->rcr1      |= RFRLEN1(wpf - 1);
 322         regs->xcr1      |= XFRLEN1(wpf - 1);
 323
 324         switch (params_format(params)) {
 325         case SNDRV_PCM_FORMAT_S16_LE:
 326                 /* Set word lengths */
 327                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
 328                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
 329                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
 330                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
 331                 break;
 332         case SNDRV_PCM_FORMAT_S32_LE:
 333                 /* Set word lengths */
 334                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_32);
 335                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_32);
 336                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_32);
 337                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_32);
 338                 break;
 339         default:
 340                 /* Unsupported PCM format */
 341                 return -EINVAL;
 342         }
 343
 344         /* In McBSP master modes, FRAME (i.e. sample rate) is generated
 345          * by _counting_ BCLKs. Calculate frame size in BCLKs */
 346         master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
 347         if (master ==   SND_SOC_DAIFMT_CBS_CFS) {
 348                 div = mcbsp->clk_div ? mcbsp->clk_div : 1;
 349                 framesize = (mcbsp->in_freq / div) / params_rate(params);
 350
 351                 if (framesize < wlen * channels) {
 352                         printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
 353                                         "channels\n", __func__);
 354                         return -EINVAL;
 355                 }
 356         } else
 357                 framesize = wlen * channels;
 358
 359         /* Set FS period and length in terms of bit clock periods */
 360         regs->srgr2     &= ~FPER(0xfff);
 361         regs->srgr1     &= ~FWID(0xff);
 362         switch (format) {
 363         case SND_SOC_DAIFMT_I2S:
 364         case SND_SOC_DAIFMT_LEFT_J:
 365                 regs->srgr2     |= FPER(framesize - 1);
 366                 regs->srgr1     |= FWID((framesize >> 1) - 1);
 367                 break;
 368         case SND_SOC_DAIFMT_DSP_A:
 369         case SND_SOC_DAIFMT_DSP_B:
 370                 regs->srgr2     |= FPER(framesize - 1);
 371                 regs->srgr1     |= FWID(0);
 372                 break;
 373         }
 374
 375         omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
 376         mcbsp->wlen = wlen;
 377         mcbsp->configured = 1;
 378
 379         return 0;
 380 }
 381
 382 /*
 383  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 384  * cache is initialized here
 385  */
 386 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 387                                       unsigned int fmt)
 388 {
 389         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 390         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 391         bool inv_fs = false;
 392
 393         if (mcbsp->configured)
 394                 return 0;
 395
 396         mcbsp->fmt = fmt;
 397         memset(regs, 0, sizeof(*regs));
 398         /* Generic McBSP register settings */
 399         regs->spcr2     |= XINTM(3) | FREE;
 400         regs->spcr1     |= RINTM(3);
 401         /* RFIG and XFIG are not defined in 34xx */
 402         if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) {
 403                 regs->rcr2      |= RFIG;
 404                 regs->xcr2      |= XFIG;
 405         }
 406         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 407                 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
 408                 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
 409         }
 410
 411         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 412         case SND_SOC_DAIFMT_I2S:
 413                 /* 1-bit data delay */
 414                 regs->rcr2      |= RDATDLY(1);
 415                 regs->xcr2      |= XDATDLY(1);
 416                 break;
 417         case SND_SOC_DAIFMT_LEFT_J:
 418                 /* 0-bit data delay */
 419                 regs->rcr2      |= RDATDLY(0);
 420                 regs->xcr2      |= XDATDLY(0);
 421                 regs->spcr1     |= RJUST(2);
 422                 /* Invert FS polarity configuration */
 423                 inv_fs = true;
 424                 break;
 425         case SND_SOC_DAIFMT_DSP_A:
 426                 /* 1-bit data delay */
 427                 regs->rcr2      |= RDATDLY(1);
 428                 regs->xcr2      |= XDATDLY(1);
 429                 /* Invert FS polarity configuration */
 430                 inv_fs = true;
 431                 break;
 432         case SND_SOC_DAIFMT_DSP_B:
 433                 /* 0-bit data delay */
 434                 regs->rcr2      |= RDATDLY(0);
 435                 regs->xcr2      |= XDATDLY(0);
 436                 /* Invert FS polarity configuration */
 437                 inv_fs = true;
 438                 break;
 439         default:
 440                 /* Unsupported data format */
 441                 return -EINVAL;
 442         }
 443
 444         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 445         case SND_SOC_DAIFMT_CBS_CFS:
 446                 /* McBSP master. Set FS and bit clocks as outputs */
 447                 regs->pcr0      |= FSXM | FSRM |
 448                                    CLKXM | CLKRM;
 449                 /* Sample rate generator drives the FS */
 450                 regs->srgr2     |= FSGM;
 451                 break;
 452         case SND_SOC_DAIFMT_CBM_CFM:
 453                 /* McBSP slave */
 454                 break;
 455         default:
 456                 /* Unsupported master/slave configuration */
 457                 return -EINVAL;
 458         }
 459
 460         /* Set bit clock (CLKX/CLKR) and FS polarities */
 461         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 462         case SND_SOC_DAIFMT_NB_NF:
 463                 /*
 464                  * Normal BCLK + FS.
 465                  * FS active low. TX data driven on falling edge of bit clock
 466                  * and RX data sampled on rising edge of bit clock.
 467                  */
 468                 regs->pcr0      |= FSXP | FSRP |
 469                                    CLKXP | CLKRP;
 470                 break;
 471         case SND_SOC_DAIFMT_NB_IF:
 472                 regs->pcr0      |= CLKXP | CLKRP;
 473                 break;
 474         case SND_SOC_DAIFMT_IB_NF:
 475                 regs->pcr0      |= FSXP | FSRP;
 476                 break;
 477         case SND_SOC_DAIFMT_IB_IF:
 478                 break;
 479         default:
 480                 return -EINVAL;
 481         }
 482         if (inv_fs == true)
 483                 regs->pcr0 ^= FSXP | FSRP;
 484
 485         return 0;
 486 }
 487
 488 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
 489                                      int div_id, int div)
 490 {
 491         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 492         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 493
 494         if (div_id != OMAP_MCBSP_CLKGDV)
 495                 return -ENODEV;
 496
 497         mcbsp->clk_div = div;
 498         regs->srgr1     &= ~CLKGDV(0xff);
 499         regs->srgr1     |= CLKGDV(div - 1);
 500
 501         return 0;
 502 }
 503
 504 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 505                                          int clk_id, unsigned int freq,
 506                                          int dir)
 507 {
 508         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 509         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 510         int err = 0;
 511
 512         if (mcbsp->active) {
 513                 if (freq == mcbsp->in_freq)
 514                         return 0;
 515                 else
 516                         return -EBUSY;
 517         }
 518
 519         if (clk_id == OMAP_MCBSP_SYSCLK_CLK ||
 520             clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK ||
 521             clk_id == OMAP_MCBSP_SYSCLK_CLKS_EXT ||
 522             clk_id == OMAP_MCBSP_SYSCLK_CLKX_EXT ||
 523             clk_id == OMAP_MCBSP_SYSCLK_CLKR_EXT) {
 524                 mcbsp->in_freq = freq;
 525                 regs->srgr2     &= ~CLKSM;
 526                 regs->pcr0      &= ~SCLKME;
 527         } else if (cpu_class_is_omap1()) {
 528                 /*
 529                  * McBSP CLKR/FSR signal muxing functions are only available on
 530                  * OMAP2 or newer versions
 531                  */
 532                 return -EINVAL;
 533         }
 534
 535         switch (clk_id) {
 536         case OMAP_MCBSP_SYSCLK_CLK:
 537                 regs->srgr2     |= CLKSM;
 538                 break;
 539         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
 540                 if (cpu_class_is_omap1()) {
 541                         err = -EINVAL;
 542                         break;
 543                 }
 544                 err = omap2_mcbsp_set_clks_src(mcbsp,
 545                                                MCBSP_CLKS_PRCM_SRC);
 546                 break;
 547         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 548                 if (cpu_class_is_omap1()) {
 549                         err = 0;
 550                         break;
 551                 }
 552                 err = omap2_mcbsp_set_clks_src(mcbsp,
 553                                                MCBSP_CLKS_PAD_SRC);
 554                 break;
 555
 556         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
 557                 regs->srgr2     |= CLKSM;
 558         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 559                 regs->pcr0      |= SCLKME;
 560                 break;
 561
 562
 563         case OMAP_MCBSP_CLKR_SRC_CLKR:
 564                 err = omap_mcbsp_6pin_src_mux(mcbsp, CLKR_SRC_CLKR);
 565                 break;
 566         case OMAP_MCBSP_CLKR_SRC_CLKX:
 567                 err = omap_mcbsp_6pin_src_mux(mcbsp, CLKR_SRC_CLKX);
 568                 break;
 569         case OMAP_MCBSP_FSR_SRC_FSR:
 570                 err = omap_mcbsp_6pin_src_mux(mcbsp, FSR_SRC_FSR);
 571                 break;
 572         case OMAP_MCBSP_FSR_SRC_FSX:
 573                 err = omap_mcbsp_6pin_src_mux(mcbsp, FSR_SRC_FSX);
 574                 break;
 575         default:
 576                 err = -ENODEV;
 577         }
 578
 579         return err;
 580 }
 581
 582 static const struct snd_soc_dai_ops mcbsp_dai_ops = {
 583         .startup        = omap_mcbsp_dai_startup,
 584         .shutdown       = omap_mcbsp_dai_shutdown,
 585         .trigger        = omap_mcbsp_dai_trigger,
 586         .delay          = omap_mcbsp_dai_delay,
 587         .hw_params      = omap_mcbsp_dai_hw_params,
 588         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
 589         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
 590         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
 591 };
 592
 593 static int omap_mcbsp_probe(struct snd_soc_dai *dai)
 594 {
 595         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
 596
 597         pm_runtime_enable(mcbsp->dev);
 598
 599         return 0;
 600 }
 601
 602 static int omap_mcbsp_remove(struct snd_soc_dai *dai)
 603 {
 604         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
 605
 606         pm_runtime_disable(mcbsp->dev);
 607
 608         return 0;
 609 }
 610
 611 static struct snd_soc_dai_driver omap_mcbsp_dai = {
 612         .probe = omap_mcbsp_probe,
 613         .remove = omap_mcbsp_remove,
 614         .playback = {
 615                 .channels_min = 1,
 616                 .channels_max = 16,
 617                 .rates = OMAP_MCBSP_RATES,
 618                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
 619         },
 620         .capture = {
 621                 .channels_min = 1,
 622                 .channels_max = 16,
 623                 .rates = OMAP_MCBSP_RATES,
 624                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
 625         },
 626         .ops = &mcbsp_dai_ops,
 627 };
 628
 629 static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
 630                         struct snd_ctl_elem_info *uinfo)
 631 {
 632         struct soc_mixer_control *mc =
 633                 (struct soc_mixer_control *)kcontrol->private_value;
 634         int max = mc->max;
 635         int min = mc->min;
 636
 637         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 638         uinfo->count = 1;
 639         uinfo->value.integer.min = min;
 640         uinfo->value.integer.max = max;
 641         return 0;
 642 }
 643
 644 #define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(channel)                       \
 645 static int                                                              \
 646 omap_mcbsp_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \
 647                                         struct snd_ctl_elem_value *uc)  \
 648 {                                                                       \
 649         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc);            \
 650         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);    \
 651         struct soc_mixer_control *mc =                                  \
 652                 (struct soc_mixer_control *)kc->private_value;          \
 653         int max = mc->max;                                              \
 654         int min = mc->min;                                              \
 655         int val = uc->value.integer.value[0];                           \
 656                                                                         \
 657         if (val < min || val > max)                                     \
 658                 return -EINVAL;                                         \
 659                                                                         \
 660         /* OMAP McBSP implementation uses index values 0..4 */          \
 661         return omap_st_set_chgain(mcbsp, channel, val);                 \
 662 }
 663
 664 #define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(channel)                       \
 665 static int                                                              \
 666 omap_mcbsp_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \
 667                                         struct snd_ctl_elem_value *uc)  \
 668 {                                                                       \
 669         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc);            \
 670         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);    \
 671         s16 chgain;                                                     \
 672                                                                         \
 673         if (omap_st_get_chgain(mcbsp, channel, &chgain))                \
 674                 return -EAGAIN;                                         \
 675                                                                         \
 676         uc->value.integer.value[0] = chgain;                            \
 677         return 0;                                                       \
 678 }
 679
 680 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(0)
 681 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(1)
 682 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(0)
 683 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(1)
 684
 685 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
 686                                 struct snd_ctl_elem_value *ucontrol)
 687 {
 688         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
 689         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 690         u8 value = ucontrol->value.integer.value[0];
 691
 692         if (value == omap_st_is_enabled(mcbsp))
 693                 return 0;
 694
 695         if (value)
 696                 omap_st_enable(mcbsp);
 697         else
 698                 omap_st_disable(mcbsp);
 699
 700         return 1;
 701 }
 702
 703 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
 704                                 struct snd_ctl_elem_value *ucontrol)
 705 {
 706         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
 707         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 708
 709         ucontrol->value.integer.value[0] = omap_st_is_enabled(mcbsp);
 710         return 0;
 711 }
 712
 713 static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = {
 714         SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
 715                         omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
 716         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
 717                                       -32768, 32767,
 718                                       omap_mcbsp_get_st_ch0_volume,
 719                                       omap_mcbsp_set_st_ch0_volume),
 720         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
 721                                       -32768, 32767,
 722                                       omap_mcbsp_get_st_ch1_volume,
 723                                       omap_mcbsp_set_st_ch1_volume),
 724 };
 725
 726 static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = {
 727         SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
 728                         omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
 729         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
 730                                       -32768, 32767,
 731                                       omap_mcbsp_get_st_ch0_volume,
 732                                       omap_mcbsp_set_st_ch0_volume),
 733         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
 734                                       -32768, 32767,
 735                                       omap_mcbsp_get_st_ch1_volume,
 736                                       omap_mcbsp_set_st_ch1_volume),
 737 };
 738
 739 int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd)
 740 {
 741         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 742         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 743
 744         if (!mcbsp->st_data)
 745                 return -ENODEV;
 746
 747         switch (cpu_dai->id) {
 748         case 2: /* McBSP 2 */
 749                 return snd_soc_add_dai_controls(cpu_dai,
 750                                         omap_mcbsp2_st_controls,
 751                                         ARRAY_SIZE(omap_mcbsp2_st_controls));
 752         case 3: /* McBSP 3 */
 753                 return snd_soc_add_dai_controls(cpu_dai,
 754                                         omap_mcbsp3_st_controls,
 755                                         ARRAY_SIZE(omap_mcbsp3_st_controls));
 756         default:
 757                 break;
 758         }
 759
 760         return -EINVAL;
 761 }
 762 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
 763
 764 static __devinit int asoc_mcbsp_probe(struct platform_device *pdev)
 765 {
 766         struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
 767         struct omap_mcbsp *mcbsp;
 768         int ret;
 769
 770         if (!pdata) {
 771                 dev_err(&pdev->dev, "missing platform data.\n");
 772                 return -EINVAL;
 773         }
 774         mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
 775         if (!mcbsp)
 776                 return -ENOMEM;
 777
 778         mcbsp->id = pdev->id;
 779         mcbsp->pdata = pdata;
 780         mcbsp->dev = &pdev->dev;
 781         platform_set_drvdata(pdev, mcbsp);
 782
 783         ret = omap_mcbsp_init(pdev);
 784         if (!ret)
 785                 return snd_soc_register_dai(&pdev->dev, &omap_mcbsp_dai);
 786
 787         return ret;
 788 }
 789
 790 static int __devexit asoc_mcbsp_remove(struct platform_device *pdev)
 791 {
 792         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
 793
 794         snd_soc_unregister_dai(&pdev->dev);
 795
 796         if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 797                 mcbsp->pdata->ops->free(mcbsp->id);
 798
 799         omap_mcbsp_sysfs_remove(mcbsp);
 800
 801         clk_put(mcbsp->fclk);
 802
 803         platform_set_drvdata(pdev, NULL);
 804
 805         return 0;
 806 }
 807
 808 static struct platform_driver asoc_mcbsp_driver = {
 809         .driver = {
 810                         .name = "omap-mcbsp",
 811                         .owner = THIS_MODULE,
 812         },
 813
 814         .probe = asoc_mcbsp_probe,
 815         .remove = __devexit_p(asoc_mcbsp_remove),
 816 };
 817
 818 module_platform_driver(asoc_mcbsp_driver);
 819
 820 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
 821 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 822 MODULE_LICENSE("GPL");