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Merge branch 'for-4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[mirror_ubuntu-jammy-kernel.git] / sound / soc / omap / omap-mcbsp.c
1 /*
2 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
3 *
4 * Copyright (C) 2008 Nokia Corporation
5 *
6 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
7 * Peter Ujfalusi <peter.ujfalusi@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/of.h>
30 #include <linux/of_device.h>
31 #include <sound/core.h>
32 #include <sound/pcm.h>
33 #include <sound/pcm_params.h>
34 #include <sound/initval.h>
35 #include <sound/soc.h>
36 #include <sound/dmaengine_pcm.h>
37
38 #include "omap-mcbsp-priv.h"
39 #include "omap-mcbsp.h"
40 #include "sdma-pcm.h"
41
42 #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
43
44 enum {
45 OMAP_MCBSP_WORD_8 = 0,
46 OMAP_MCBSP_WORD_12,
47 OMAP_MCBSP_WORD_16,
48 OMAP_MCBSP_WORD_20,
49 OMAP_MCBSP_WORD_24,
50 OMAP_MCBSP_WORD_32,
51 };
52
53 static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
54 {
55 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
56 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", MCBSP_READ(mcbsp, DRR2));
57 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", MCBSP_READ(mcbsp, DRR1));
58 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", MCBSP_READ(mcbsp, DXR2));
59 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", MCBSP_READ(mcbsp, DXR1));
60 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", MCBSP_READ(mcbsp, SPCR2));
61 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", MCBSP_READ(mcbsp, SPCR1));
62 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n", MCBSP_READ(mcbsp, RCR2));
63 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n", MCBSP_READ(mcbsp, RCR1));
64 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n", MCBSP_READ(mcbsp, XCR2));
65 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n", MCBSP_READ(mcbsp, XCR1));
66 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", MCBSP_READ(mcbsp, SRGR2));
67 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", MCBSP_READ(mcbsp, SRGR1));
68 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n", MCBSP_READ(mcbsp, PCR0));
69 dev_dbg(mcbsp->dev, "***********************\n");
70 }
71
72 static int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
73 {
74 struct clk *fck_src;
75 const char *src;
76 int r;
77
78 if (fck_src_id == MCBSP_CLKS_PAD_SRC)
79 src = "pad_fck";
80 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
81 src = "prcm_fck";
82 else
83 return -EINVAL;
84
85 fck_src = clk_get(mcbsp->dev, src);
86 if (IS_ERR(fck_src)) {
87 dev_err(mcbsp->dev, "CLKS: could not clk_get() %s\n", src);
88 return -EINVAL;
89 }
90
91 pm_runtime_put_sync(mcbsp->dev);
92
93 r = clk_set_parent(mcbsp->fclk, fck_src);
94 if (r) {
95 dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n",
96 src);
97 clk_put(fck_src);
98 return r;
99 }
100
101 pm_runtime_get_sync(mcbsp->dev);
102
103 clk_put(fck_src);
104
105 return 0;
106 }
107
108 static irqreturn_t omap_mcbsp_irq_handler(int irq, void *data)
109 {
110 struct omap_mcbsp *mcbsp = data;
111 u16 irqst;
112
113 irqst = MCBSP_READ(mcbsp, IRQST);
114 dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
115
116 if (irqst & RSYNCERREN)
117 dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
118 if (irqst & RFSREN)
119 dev_dbg(mcbsp->dev, "RX Frame Sync\n");
120 if (irqst & REOFEN)
121 dev_dbg(mcbsp->dev, "RX End Of Frame\n");
122 if (irqst & RRDYEN)
123 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
124 if (irqst & RUNDFLEN)
125 dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
126 if (irqst & ROVFLEN)
127 dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
128
129 if (irqst & XSYNCERREN)
130 dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
131 if (irqst & XFSXEN)
132 dev_dbg(mcbsp->dev, "TX Frame Sync\n");
133 if (irqst & XEOFEN)
134 dev_dbg(mcbsp->dev, "TX End Of Frame\n");
135 if (irqst & XRDYEN)
136 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
137 if (irqst & XUNDFLEN)
138 dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
139 if (irqst & XOVFLEN)
140 dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
141 if (irqst & XEMPTYEOFEN)
142 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
143
144 MCBSP_WRITE(mcbsp, IRQST, irqst);
145
146 return IRQ_HANDLED;
147 }
148
149 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *data)
150 {
151 struct omap_mcbsp *mcbsp = data;
152 u16 irqst_spcr2;
153
154 irqst_spcr2 = MCBSP_READ(mcbsp, SPCR2);
155 dev_dbg(mcbsp->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
156
157 if (irqst_spcr2 & XSYNC_ERR) {
158 dev_err(mcbsp->dev, "TX Frame Sync Error! : 0x%x\n",
159 irqst_spcr2);
160 /* Writing zero to XSYNC_ERR clears the IRQ */
161 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
162 }
163
164 return IRQ_HANDLED;
165 }
166
167 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *data)
168 {
169 struct omap_mcbsp *mcbsp = data;
170 u16 irqst_spcr1;
171
172 irqst_spcr1 = MCBSP_READ(mcbsp, SPCR1);
173 dev_dbg(mcbsp->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
174
175 if (irqst_spcr1 & RSYNC_ERR) {
176 dev_err(mcbsp->dev, "RX Frame Sync Error! : 0x%x\n",
177 irqst_spcr1);
178 /* Writing zero to RSYNC_ERR clears the IRQ */
179 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
180 }
181
182 return IRQ_HANDLED;
183 }
184
185 /*
186 * omap_mcbsp_config simply write a config to the
187 * appropriate McBSP.
188 * You either call this function or set the McBSP registers
189 * by yourself before calling omap_mcbsp_start().
190 */
191 static void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
192 const struct omap_mcbsp_reg_cfg *config)
193 {
194 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
195 mcbsp->id, mcbsp->phys_base);
196
197 /* We write the given config */
198 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
199 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
200 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
201 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
202 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
203 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
204 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
205 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
206 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
207 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
208 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
209 if (mcbsp->pdata->has_ccr) {
210 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
211 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
212 }
213 /* Enable wakeup behavior */
214 if (mcbsp->pdata->has_wakeup)
215 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
216
217 /* Enable TX/RX sync error interrupts by default */
218 if (mcbsp->irq)
219 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN |
220 RUNDFLEN | ROVFLEN | XUNDFLEN | XOVFLEN);
221 }
222
223 /**
224 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
225 * @mcbsp: omap_mcbsp struct for the McBSP instance
226 * @stream: Stream direction (playback/capture)
227 *
228 * Returns the address of mcbsp data transmit register or data receive register
229 * to be used by DMA for transferring/receiving data
230 */
231 static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
232 unsigned int stream)
233 {
234 int data_reg;
235
236 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
237 if (mcbsp->pdata->reg_size == 2)
238 data_reg = OMAP_MCBSP_REG_DXR1;
239 else
240 data_reg = OMAP_MCBSP_REG_DXR;
241 } else {
242 if (mcbsp->pdata->reg_size == 2)
243 data_reg = OMAP_MCBSP_REG_DRR1;
244 else
245 data_reg = OMAP_MCBSP_REG_DRR;
246 }
247
248 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
249 }
250
251 /*
252 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
253 * The threshold parameter is 1 based, and it is converted (threshold - 1)
254 * for the THRSH2 register.
255 */
256 static void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
257 {
258 if (threshold && threshold <= mcbsp->max_tx_thres)
259 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
260 }
261
262 /*
263 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
264 * The threshold parameter is 1 based, and it is converted (threshold - 1)
265 * for the THRSH1 register.
266 */
267 static void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
268 {
269 if (threshold && threshold <= mcbsp->max_rx_thres)
270 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
271 }
272
273 /*
274 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
275 */
276 static u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
277 {
278 u16 buffstat;
279
280 /* Returns the number of free locations in the buffer */
281 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
282
283 /* Number of slots are different in McBSP ports */
284 return mcbsp->pdata->buffer_size - buffstat;
285 }
286
287 /*
288 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
289 * to reach the threshold value (when the DMA will be triggered to read it)
290 */
291 static u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
292 {
293 u16 buffstat, threshold;
294
295 /* Returns the number of used locations in the buffer */
296 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
297 /* RX threshold */
298 threshold = MCBSP_READ(mcbsp, THRSH1);
299
300 /* Return the number of location till we reach the threshold limit */
301 if (threshold <= buffstat)
302 return 0;
303 else
304 return threshold - buffstat;
305 }
306
307 static int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
308 {
309 void *reg_cache;
310 int err;
311
312 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
313 if (!reg_cache)
314 return -ENOMEM;
315
316 spin_lock(&mcbsp->lock);
317 if (!mcbsp->free) {
318 dev_err(mcbsp->dev, "McBSP%d is currently in use\n", mcbsp->id);
319 err = -EBUSY;
320 goto err_kfree;
321 }
322
323 mcbsp->free = false;
324 mcbsp->reg_cache = reg_cache;
325 spin_unlock(&mcbsp->lock);
326
327 if(mcbsp->pdata->ops && mcbsp->pdata->ops->request)
328 mcbsp->pdata->ops->request(mcbsp->id - 1);
329
330 /*
331 * Make sure that transmitter, receiver and sample-rate generator are
332 * not running before activating IRQs.
333 */
334 MCBSP_WRITE(mcbsp, SPCR1, 0);
335 MCBSP_WRITE(mcbsp, SPCR2, 0);
336
337 if (mcbsp->irq) {
338 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
339 "McBSP", (void *)mcbsp);
340 if (err != 0) {
341 dev_err(mcbsp->dev, "Unable to request IRQ\n");
342 goto err_clk_disable;
343 }
344 } else {
345 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
346 "McBSP TX", (void *)mcbsp);
347 if (err != 0) {
348 dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
349 goto err_clk_disable;
350 }
351
352 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
353 "McBSP RX", (void *)mcbsp);
354 if (err != 0) {
355 dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
356 goto err_free_irq;
357 }
358 }
359
360 return 0;
361 err_free_irq:
362 free_irq(mcbsp->tx_irq, (void *)mcbsp);
363 err_clk_disable:
364 if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
365 mcbsp->pdata->ops->free(mcbsp->id - 1);
366
367 /* Disable wakeup behavior */
368 if (mcbsp->pdata->has_wakeup)
369 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
370
371 spin_lock(&mcbsp->lock);
372 mcbsp->free = true;
373 mcbsp->reg_cache = NULL;
374 err_kfree:
375 spin_unlock(&mcbsp->lock);
376 kfree(reg_cache);
377
378 return err;
379 }
380
381 static void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
382 {
383 void *reg_cache;
384
385 if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
386 mcbsp->pdata->ops->free(mcbsp->id - 1);
387
388 /* Disable wakeup behavior */
389 if (mcbsp->pdata->has_wakeup)
390 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
391
392 /* Disable interrupt requests */
393 if (mcbsp->irq)
394 MCBSP_WRITE(mcbsp, IRQEN, 0);
395
396 if (mcbsp->irq) {
397 free_irq(mcbsp->irq, (void *)mcbsp);
398 } else {
399 free_irq(mcbsp->rx_irq, (void *)mcbsp);
400 free_irq(mcbsp->tx_irq, (void *)mcbsp);
401 }
402
403 reg_cache = mcbsp->reg_cache;
404
405 /*
406 * Select CLKS source from internal source unconditionally before
407 * marking the McBSP port as free.
408 * If the external clock source via MCBSP_CLKS pin has been selected the
409 * system will refuse to enter idle if the CLKS pin source is not reset
410 * back to internal source.
411 */
412 if (!mcbsp_omap1())
413 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
414
415 spin_lock(&mcbsp->lock);
416 if (mcbsp->free)
417 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
418 else
419 mcbsp->free = true;
420 mcbsp->reg_cache = NULL;
421 spin_unlock(&mcbsp->lock);
422
423 kfree(reg_cache);
424 }
425
426 /*
427 * Here we start the McBSP, by enabling transmitter, receiver or both.
428 * If no transmitter or receiver is active prior calling, then sample-rate
429 * generator and frame sync are started.
430 */
431 static void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int stream)
432 {
433 int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
434 int rx = !tx;
435 int enable_srg = 0;
436 u16 w;
437
438 if (mcbsp->st_data)
439 omap_mcbsp_st_start(mcbsp);
440
441 /* Only enable SRG, if McBSP is master */
442 w = MCBSP_READ_CACHE(mcbsp, PCR0);
443 if (w & (FSXM | FSRM | CLKXM | CLKRM))
444 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
445 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
446
447 if (enable_srg) {
448 /* Start the sample generator */
449 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
450 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
451 }
452
453 /* Enable transmitter and receiver */
454 tx &= 1;
455 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
456 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
457
458 rx &= 1;
459 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
460 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
461
462 /*
463 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
464 * REVISIT: 100us may give enough time for two CLKSRG, however
465 * due to some unknown PM related, clock gating etc. reason it
466 * is now at 500us.
467 */
468 udelay(500);
469
470 if (enable_srg) {
471 /* Start frame sync */
472 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
473 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
474 }
475
476 if (mcbsp->pdata->has_ccr) {
477 /* Release the transmitter and receiver */
478 w = MCBSP_READ_CACHE(mcbsp, XCCR);
479 w &= ~(tx ? XDISABLE : 0);
480 MCBSP_WRITE(mcbsp, XCCR, w);
481 w = MCBSP_READ_CACHE(mcbsp, RCCR);
482 w &= ~(rx ? RDISABLE : 0);
483 MCBSP_WRITE(mcbsp, RCCR, w);
484 }
485
486 /* Dump McBSP Regs */
487 omap_mcbsp_dump_reg(mcbsp);
488 }
489
490 static void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int stream)
491 {
492 int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
493 int rx = !tx;
494 int idle;
495 u16 w;
496
497 /* Reset transmitter */
498 tx &= 1;
499 if (mcbsp->pdata->has_ccr) {
500 w = MCBSP_READ_CACHE(mcbsp, XCCR);
501 w |= (tx ? XDISABLE : 0);
502 MCBSP_WRITE(mcbsp, XCCR, w);
503 }
504 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
505 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
506
507 /* Reset receiver */
508 rx &= 1;
509 if (mcbsp->pdata->has_ccr) {
510 w = MCBSP_READ_CACHE(mcbsp, RCCR);
511 w |= (rx ? RDISABLE : 0);
512 MCBSP_WRITE(mcbsp, RCCR, w);
513 }
514 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
515 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
516
517 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
518 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
519
520 if (idle) {
521 /* Reset the sample rate generator */
522 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
523 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
524 }
525
526 if (mcbsp->st_data)
527 omap_mcbsp_st_stop(mcbsp);
528 }
529
530 #define max_thres(m) (mcbsp->pdata->buffer_size)
531 #define valid_threshold(m, val) ((val) <= max_thres(m))
532 #define THRESHOLD_PROP_BUILDER(prop) \
533 static ssize_t prop##_show(struct device *dev, \
534 struct device_attribute *attr, char *buf) \
535 { \
536 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
537 \
538 return sprintf(buf, "%u\n", mcbsp->prop); \
539 } \
540 \
541 static ssize_t prop##_store(struct device *dev, \
542 struct device_attribute *attr, \
543 const char *buf, size_t size) \
544 { \
545 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
546 unsigned long val; \
547 int status; \
548 \
549 status = kstrtoul(buf, 0, &val); \
550 if (status) \
551 return status; \
552 \
553 if (!valid_threshold(mcbsp, val)) \
554 return -EDOM; \
555 \
556 mcbsp->prop = val; \
557 return size; \
558 } \
559 \
560 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store)
561
562 THRESHOLD_PROP_BUILDER(max_tx_thres);
563 THRESHOLD_PROP_BUILDER(max_rx_thres);
564
565 static const char * const dma_op_modes[] = {
566 "element", "threshold",
567 };
568
569 static ssize_t dma_op_mode_show(struct device *dev,
570 struct device_attribute *attr, char *buf)
571 {
572 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
573 int dma_op_mode, i = 0;
574 ssize_t len = 0;
575 const char * const *s;
576
577 dma_op_mode = mcbsp->dma_op_mode;
578
579 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
580 if (dma_op_mode == i)
581 len += sprintf(buf + len, "[%s] ", *s);
582 else
583 len += sprintf(buf + len, "%s ", *s);
584 }
585 len += sprintf(buf + len, "\n");
586
587 return len;
588 }
589
590 static ssize_t dma_op_mode_store(struct device *dev,
591 struct device_attribute *attr, const char *buf,
592 size_t size)
593 {
594 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
595 int i;
596
597 i = sysfs_match_string(dma_op_modes, buf);
598 if (i < 0)
599 return i;
600
601 spin_lock_irq(&mcbsp->lock);
602 if (!mcbsp->free) {
603 size = -EBUSY;
604 goto unlock;
605 }
606 mcbsp->dma_op_mode = i;
607
608 unlock:
609 spin_unlock_irq(&mcbsp->lock);
610
611 return size;
612 }
613
614 static DEVICE_ATTR_RW(dma_op_mode);
615
616 static const struct attribute *additional_attrs[] = {
617 &dev_attr_max_tx_thres.attr,
618 &dev_attr_max_rx_thres.attr,
619 &dev_attr_dma_op_mode.attr,
620 NULL,
621 };
622
623 static const struct attribute_group additional_attr_group = {
624 .attrs = (struct attribute **)additional_attrs,
625 };
626
627 /*
628 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
629 * 730 has only 2 McBSP, and both of them are MPU peripherals.
630 */
631 static int omap_mcbsp_init(struct platform_device *pdev)
632 {
633 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
634 struct resource *res;
635 int ret = 0;
636
637 spin_lock_init(&mcbsp->lock);
638 mcbsp->free = true;
639
640 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
641 if (!res)
642 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
643
644 mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res);
645 if (IS_ERR(mcbsp->io_base))
646 return PTR_ERR(mcbsp->io_base);
647
648 mcbsp->phys_base = res->start;
649 mcbsp->reg_cache_size = resource_size(res);
650
651 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
652 if (!res)
653 mcbsp->phys_dma_base = mcbsp->phys_base;
654 else
655 mcbsp->phys_dma_base = res->start;
656
657 /*
658 * OMAP1, 2 uses two interrupt lines: TX, RX
659 * OMAP2430, OMAP3 SoC have combined IRQ line as well.
660 * OMAP4 and newer SoC only have the combined IRQ line.
661 * Use the combined IRQ if available since it gives better debugging
662 * possibilities.
663 */
664 mcbsp->irq = platform_get_irq_byname(pdev, "common");
665 if (mcbsp->irq == -ENXIO) {
666 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
667
668 if (mcbsp->tx_irq == -ENXIO) {
669 mcbsp->irq = platform_get_irq(pdev, 0);
670 mcbsp->tx_irq = 0;
671 } else {
672 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
673 mcbsp->irq = 0;
674 }
675 }
676
677 if (!pdev->dev.of_node) {
678 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
679 if (!res) {
680 dev_err(&pdev->dev, "invalid tx DMA channel\n");
681 return -ENODEV;
682 }
683 mcbsp->dma_req[0] = res->start;
684 mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0];
685
686 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
687 if (!res) {
688 dev_err(&pdev->dev, "invalid rx DMA channel\n");
689 return -ENODEV;
690 }
691 mcbsp->dma_req[1] = res->start;
692 mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1];
693 } else {
694 mcbsp->dma_data[0].filter_data = "tx";
695 mcbsp->dma_data[1].filter_data = "rx";
696 }
697
698 mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp,
699 SNDRV_PCM_STREAM_PLAYBACK);
700 mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp,
701 SNDRV_PCM_STREAM_CAPTURE);
702
703 mcbsp->fclk = clk_get(&pdev->dev, "fck");
704 if (IS_ERR(mcbsp->fclk)) {
705 ret = PTR_ERR(mcbsp->fclk);
706 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
707 return ret;
708 }
709
710 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
711 if (mcbsp->pdata->buffer_size) {
712 /*
713 * Initially configure the maximum thresholds to a safe value.
714 * The McBSP FIFO usage with these values should not go under
715 * 16 locations.
716 * If the whole FIFO without safety buffer is used, than there
717 * is a possibility that the DMA will be not able to push the
718 * new data on time, causing channel shifts in runtime.
719 */
720 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
721 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
722
723 ret = sysfs_create_group(&mcbsp->dev->kobj,
724 &additional_attr_group);
725 if (ret) {
726 dev_err(mcbsp->dev,
727 "Unable to create additional controls\n");
728 goto err_thres;
729 }
730 }
731
732 ret = omap_mcbsp_st_init(pdev);
733 if (ret)
734 goto err_st;
735
736 return 0;
737
738 err_st:
739 if (mcbsp->pdata->buffer_size)
740 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
741 err_thres:
742 clk_put(mcbsp->fclk);
743 return ret;
744 }
745
746 /*
747 * Stream DMA parameters. DMA request line and port address are set runtime
748 * since they are different between OMAP1 and later OMAPs
749 */
750 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream,
751 unsigned int packet_size)
752 {
753 struct snd_soc_pcm_runtime *rtd = substream->private_data;
754 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
755 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
756 int words;
757
758 /* No need to proceed further if McBSP does not have FIFO */
759 if (mcbsp->pdata->buffer_size == 0)
760 return;
761
762 /*
763 * Configure McBSP threshold based on either:
764 * packet_size, when the sDMA is in packet mode, or based on the
765 * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
766 * for mono streams.
767 */
768 if (packet_size)
769 words = packet_size;
770 else
771 words = 1;
772
773 /* Configure McBSP internal buffer usage */
774 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
775 omap_mcbsp_set_tx_threshold(mcbsp, words);
776 else
777 omap_mcbsp_set_rx_threshold(mcbsp, words);
778 }
779
780 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
781 struct snd_pcm_hw_rule *rule)
782 {
783 struct snd_interval *buffer_size = hw_param_interval(params,
784 SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
785 struct snd_interval *channels = hw_param_interval(params,
786 SNDRV_PCM_HW_PARAM_CHANNELS);
787 struct omap_mcbsp *mcbsp = rule->private;
788 struct snd_interval frames;
789 int size;
790
791 snd_interval_any(&frames);
792 size = mcbsp->pdata->buffer_size;
793
794 frames.min = size / channels->min;
795 frames.integer = 1;
796 return snd_interval_refine(buffer_size, &frames);
797 }
798
799 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
800 struct snd_soc_dai *cpu_dai)
801 {
802 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
803 int err = 0;
804
805 if (!cpu_dai->active)
806 err = omap_mcbsp_request(mcbsp);
807
808 /*
809 * OMAP3 McBSP FIFO is word structured.
810 * McBSP2 has 1024 + 256 = 1280 word long buffer,
811 * McBSP1,3,4,5 has 128 word long buffer
812 * This means that the size of the FIFO depends on the sample format.
813 * For example on McBSP3:
814 * 16bit samples: size is 128 * 2 = 256 bytes
815 * 32bit samples: size is 128 * 4 = 512 bytes
816 * It is simpler to place constraint for buffer and period based on
817 * channels.
818 * McBSP3 as example again (16 or 32 bit samples):
819 * 1 channel (mono): size is 128 frames (128 words)
820 * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
821 * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
822 */
823 if (mcbsp->pdata->buffer_size) {
824 /*
825 * Rule for the buffer size. We should not allow
826 * smaller buffer than the FIFO size to avoid underruns.
827 * This applies only for the playback stream.
828 */
829 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
830 snd_pcm_hw_rule_add(substream->runtime, 0,
831 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
832 omap_mcbsp_hwrule_min_buffersize,
833 mcbsp,
834 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
835
836 /* Make sure, that the period size is always even */
837 snd_pcm_hw_constraint_step(substream->runtime, 0,
838 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
839 }
840
841 return err;
842 }
843
844 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
845 struct snd_soc_dai *cpu_dai)
846 {
847 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
848 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
849 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
850 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
851
852 if (mcbsp->latency[stream2])
853 pm_qos_update_request(&mcbsp->pm_qos_req,
854 mcbsp->latency[stream2]);
855 else if (mcbsp->latency[stream1])
856 pm_qos_remove_request(&mcbsp->pm_qos_req);
857
858 mcbsp->latency[stream1] = 0;
859
860 if (!cpu_dai->active) {
861 omap_mcbsp_free(mcbsp);
862 mcbsp->configured = 0;
863 }
864 }
865
866 static int omap_mcbsp_dai_prepare(struct snd_pcm_substream *substream,
867 struct snd_soc_dai *cpu_dai)
868 {
869 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
870 struct pm_qos_request *pm_qos_req = &mcbsp->pm_qos_req;
871 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
872 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
873 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
874 int latency = mcbsp->latency[stream2];
875
876 /* Prevent omap hardware from hitting off between FIFO fills */
877 if (!latency || mcbsp->latency[stream1] < latency)
878 latency = mcbsp->latency[stream1];
879
880 if (pm_qos_request_active(pm_qos_req))
881 pm_qos_update_request(pm_qos_req, latency);
882 else if (latency)
883 pm_qos_add_request(pm_qos_req, PM_QOS_CPU_DMA_LATENCY, latency);
884
885 return 0;
886 }
887
888 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
889 struct snd_soc_dai *cpu_dai)
890 {
891 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
892
893 switch (cmd) {
894 case SNDRV_PCM_TRIGGER_START:
895 case SNDRV_PCM_TRIGGER_RESUME:
896 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
897 mcbsp->active++;
898 omap_mcbsp_start(mcbsp, substream->stream);
899 break;
900
901 case SNDRV_PCM_TRIGGER_STOP:
902 case SNDRV_PCM_TRIGGER_SUSPEND:
903 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
904 omap_mcbsp_stop(mcbsp, substream->stream);
905 mcbsp->active--;
906 break;
907 default:
908 return -EINVAL;
909 }
910
911 return 0;
912 }
913
914 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
915 struct snd_pcm_substream *substream,
916 struct snd_soc_dai *dai)
917 {
918 struct snd_soc_pcm_runtime *rtd = substream->private_data;
919 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
920 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
921 u16 fifo_use;
922 snd_pcm_sframes_t delay;
923
924 /* No need to proceed further if McBSP does not have FIFO */
925 if (mcbsp->pdata->buffer_size == 0)
926 return 0;
927
928 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
929 fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
930 else
931 fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
932
933 /*
934 * Divide the used locations with the channel count to get the
935 * FIFO usage in samples (don't care about partial samples in the
936 * buffer).
937 */
938 delay = fifo_use / substream->runtime->channels;
939
940 return delay;
941 }
942
943 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
944 struct snd_pcm_hw_params *params,
945 struct snd_soc_dai *cpu_dai)
946 {
947 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
948 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
949 struct snd_dmaengine_dai_dma_data *dma_data;
950 int wlen, channels, wpf;
951 int pkt_size = 0;
952 unsigned int format, div, framesize, master;
953 unsigned int buffer_size = mcbsp->pdata->buffer_size;
954
955 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
956 channels = params_channels(params);
957
958 switch (params_format(params)) {
959 case SNDRV_PCM_FORMAT_S16_LE:
960 wlen = 16;
961 break;
962 case SNDRV_PCM_FORMAT_S32_LE:
963 wlen = 32;
964 break;
965 default:
966 return -EINVAL;
967 }
968 if (buffer_size) {
969 int latency;
970
971 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
972 int period_words, max_thrsh;
973 int divider = 0;
974
975 period_words = params_period_bytes(params) / (wlen / 8);
976 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
977 max_thrsh = mcbsp->max_tx_thres;
978 else
979 max_thrsh = mcbsp->max_rx_thres;
980 /*
981 * Use sDMA packet mode if McBSP is in threshold mode:
982 * If period words less than the FIFO size the packet
983 * size is set to the number of period words, otherwise
984 * Look for the biggest threshold value which divides
985 * the period size evenly.
986 */
987 divider = period_words / max_thrsh;
988 if (period_words % max_thrsh)
989 divider++;
990 while (period_words % divider &&
991 divider < period_words)
992 divider++;
993 if (divider == period_words)
994 return -EINVAL;
995
996 pkt_size = period_words / divider;
997 } else if (channels > 1) {
998 /* Use packet mode for non mono streams */
999 pkt_size = channels;
1000 }
1001
1002 latency = (buffer_size - pkt_size) / channels;
1003 latency = latency * USEC_PER_SEC /
1004 (params->rate_num / params->rate_den);
1005 mcbsp->latency[substream->stream] = latency;
1006
1007 omap_mcbsp_set_threshold(substream, pkt_size);
1008 }
1009
1010 dma_data->maxburst = pkt_size;
1011
1012 if (mcbsp->configured) {
1013 /* McBSP already configured by another stream */
1014 return 0;
1015 }
1016
1017 regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
1018 regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
1019 regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
1020 regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
1021 format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1022 wpf = channels;
1023 if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
1024 format == SND_SOC_DAIFMT_LEFT_J)) {
1025 /* Use dual-phase frames */
1026 regs->rcr2 |= RPHASE;
1027 regs->xcr2 |= XPHASE;
1028 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
1029 wpf--;
1030 regs->rcr2 |= RFRLEN2(wpf - 1);
1031 regs->xcr2 |= XFRLEN2(wpf - 1);
1032 }
1033
1034 regs->rcr1 |= RFRLEN1(wpf - 1);
1035 regs->xcr1 |= XFRLEN1(wpf - 1);
1036
1037 switch (params_format(params)) {
1038 case SNDRV_PCM_FORMAT_S16_LE:
1039 /* Set word lengths */
1040 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
1041 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
1042 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
1043 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
1044 break;
1045 case SNDRV_PCM_FORMAT_S32_LE:
1046 /* Set word lengths */
1047 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32);
1048 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32);
1049 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32);
1050 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32);
1051 break;
1052 default:
1053 /* Unsupported PCM format */
1054 return -EINVAL;
1055 }
1056
1057 /* In McBSP master modes, FRAME (i.e. sample rate) is generated
1058 * by _counting_ BCLKs. Calculate frame size in BCLKs */
1059 master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
1060 if (master == SND_SOC_DAIFMT_CBS_CFS) {
1061 div = mcbsp->clk_div ? mcbsp->clk_div : 1;
1062 framesize = (mcbsp->in_freq / div) / params_rate(params);
1063
1064 if (framesize < wlen * channels) {
1065 printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
1066 "channels\n", __func__);
1067 return -EINVAL;
1068 }
1069 } else
1070 framesize = wlen * channels;
1071
1072 /* Set FS period and length in terms of bit clock periods */
1073 regs->srgr2 &= ~FPER(0xfff);
1074 regs->srgr1 &= ~FWID(0xff);
1075 switch (format) {
1076 case SND_SOC_DAIFMT_I2S:
1077 case SND_SOC_DAIFMT_LEFT_J:
1078 regs->srgr2 |= FPER(framesize - 1);
1079 regs->srgr1 |= FWID((framesize >> 1) - 1);
1080 break;
1081 case SND_SOC_DAIFMT_DSP_A:
1082 case SND_SOC_DAIFMT_DSP_B:
1083 regs->srgr2 |= FPER(framesize - 1);
1084 regs->srgr1 |= FWID(0);
1085 break;
1086 }
1087
1088 omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
1089 mcbsp->wlen = wlen;
1090 mcbsp->configured = 1;
1091
1092 return 0;
1093 }
1094
1095 /*
1096 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
1097 * cache is initialized here
1098 */
1099 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
1100 unsigned int fmt)
1101 {
1102 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1103 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1104 bool inv_fs = false;
1105
1106 if (mcbsp->configured)
1107 return 0;
1108
1109 mcbsp->fmt = fmt;
1110 memset(regs, 0, sizeof(*regs));
1111 /* Generic McBSP register settings */
1112 regs->spcr2 |= XINTM(3) | FREE;
1113 regs->spcr1 |= RINTM(3);
1114 /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
1115 if (!mcbsp->pdata->has_ccr) {
1116 regs->rcr2 |= RFIG;
1117 regs->xcr2 |= XFIG;
1118 }
1119
1120 /* Configure XCCR/RCCR only for revisions which have ccr registers */
1121 if (mcbsp->pdata->has_ccr) {
1122 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
1123 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
1124 }
1125
1126 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1127 case SND_SOC_DAIFMT_I2S:
1128 /* 1-bit data delay */
1129 regs->rcr2 |= RDATDLY(1);
1130 regs->xcr2 |= XDATDLY(1);
1131 break;
1132 case SND_SOC_DAIFMT_LEFT_J:
1133 /* 0-bit data delay */
1134 regs->rcr2 |= RDATDLY(0);
1135 regs->xcr2 |= XDATDLY(0);
1136 regs->spcr1 |= RJUST(2);
1137 /* Invert FS polarity configuration */
1138 inv_fs = true;
1139 break;
1140 case SND_SOC_DAIFMT_DSP_A:
1141 /* 1-bit data delay */
1142 regs->rcr2 |= RDATDLY(1);
1143 regs->xcr2 |= XDATDLY(1);
1144 /* Invert FS polarity configuration */
1145 inv_fs = true;
1146 break;
1147 case SND_SOC_DAIFMT_DSP_B:
1148 /* 0-bit data delay */
1149 regs->rcr2 |= RDATDLY(0);
1150 regs->xcr2 |= XDATDLY(0);
1151 /* Invert FS polarity configuration */
1152 inv_fs = true;
1153 break;
1154 default:
1155 /* Unsupported data format */
1156 return -EINVAL;
1157 }
1158
1159 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1160 case SND_SOC_DAIFMT_CBS_CFS:
1161 /* McBSP master. Set FS and bit clocks as outputs */
1162 regs->pcr0 |= FSXM | FSRM |
1163 CLKXM | CLKRM;
1164 /* Sample rate generator drives the FS */
1165 regs->srgr2 |= FSGM;
1166 break;
1167 case SND_SOC_DAIFMT_CBM_CFS:
1168 /* McBSP slave. FS clock as output */
1169 regs->srgr2 |= FSGM;
1170 regs->pcr0 |= FSXM | FSRM;
1171 break;
1172 case SND_SOC_DAIFMT_CBM_CFM:
1173 /* McBSP slave */
1174 break;
1175 default:
1176 /* Unsupported master/slave configuration */
1177 return -EINVAL;
1178 }
1179
1180 /* Set bit clock (CLKX/CLKR) and FS polarities */
1181 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1182 case SND_SOC_DAIFMT_NB_NF:
1183 /*
1184 * Normal BCLK + FS.
1185 * FS active low. TX data driven on falling edge of bit clock
1186 * and RX data sampled on rising edge of bit clock.
1187 */
1188 regs->pcr0 |= FSXP | FSRP |
1189 CLKXP | CLKRP;
1190 break;
1191 case SND_SOC_DAIFMT_NB_IF:
1192 regs->pcr0 |= CLKXP | CLKRP;
1193 break;
1194 case SND_SOC_DAIFMT_IB_NF:
1195 regs->pcr0 |= FSXP | FSRP;
1196 break;
1197 case SND_SOC_DAIFMT_IB_IF:
1198 break;
1199 default:
1200 return -EINVAL;
1201 }
1202 if (inv_fs == true)
1203 regs->pcr0 ^= FSXP | FSRP;
1204
1205 return 0;
1206 }
1207
1208 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
1209 int div_id, int div)
1210 {
1211 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1212 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1213
1214 if (div_id != OMAP_MCBSP_CLKGDV)
1215 return -ENODEV;
1216
1217 mcbsp->clk_div = div;
1218 regs->srgr1 &= ~CLKGDV(0xff);
1219 regs->srgr1 |= CLKGDV(div - 1);
1220
1221 return 0;
1222 }
1223
1224 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
1225 int clk_id, unsigned int freq,
1226 int dir)
1227 {
1228 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1229 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1230 int err = 0;
1231
1232 if (mcbsp->active) {
1233 if (freq == mcbsp->in_freq)
1234 return 0;
1235 else
1236 return -EBUSY;
1237 }
1238
1239 mcbsp->in_freq = freq;
1240 regs->srgr2 &= ~CLKSM;
1241 regs->pcr0 &= ~SCLKME;
1242
1243 switch (clk_id) {
1244 case OMAP_MCBSP_SYSCLK_CLK:
1245 regs->srgr2 |= CLKSM;
1246 break;
1247 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
1248 if (mcbsp_omap1()) {
1249 err = -EINVAL;
1250 break;
1251 }
1252 err = omap2_mcbsp_set_clks_src(mcbsp,
1253 MCBSP_CLKS_PRCM_SRC);
1254 break;
1255 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
1256 if (mcbsp_omap1()) {
1257 err = 0;
1258 break;
1259 }
1260 err = omap2_mcbsp_set_clks_src(mcbsp,
1261 MCBSP_CLKS_PAD_SRC);
1262 break;
1263
1264 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
1265 regs->srgr2 |= CLKSM;
1266 regs->pcr0 |= SCLKME;
1267 /*
1268 * If McBSP is master but yet the CLKX/CLKR pin drives the SRG,
1269 * disable output on those pins. This enables to inject the
1270 * reference clock through CLKX/CLKR. For this to work
1271 * set_dai_sysclk() _needs_ to be called after set_dai_fmt().
1272 */
1273 regs->pcr0 &= ~CLKXM;
1274 break;
1275 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
1276 regs->pcr0 |= SCLKME;
1277 /* Disable ouput on CLKR pin in master mode */
1278 regs->pcr0 &= ~CLKRM;
1279 break;
1280 default:
1281 err = -ENODEV;
1282 }
1283
1284 return err;
1285 }
1286
1287 static const struct snd_soc_dai_ops mcbsp_dai_ops = {
1288 .startup = omap_mcbsp_dai_startup,
1289 .shutdown = omap_mcbsp_dai_shutdown,
1290 .prepare = omap_mcbsp_dai_prepare,
1291 .trigger = omap_mcbsp_dai_trigger,
1292 .delay = omap_mcbsp_dai_delay,
1293 .hw_params = omap_mcbsp_dai_hw_params,
1294 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
1295 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
1296 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
1297 };
1298
1299 static int omap_mcbsp_probe(struct snd_soc_dai *dai)
1300 {
1301 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1302
1303 pm_runtime_enable(mcbsp->dev);
1304
1305 snd_soc_dai_init_dma_data(dai,
1306 &mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
1307 &mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
1308
1309 return 0;
1310 }
1311
1312 static int omap_mcbsp_remove(struct snd_soc_dai *dai)
1313 {
1314 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1315
1316 pm_runtime_disable(mcbsp->dev);
1317
1318 return 0;
1319 }
1320
1321 static struct snd_soc_dai_driver omap_mcbsp_dai = {
1322 .probe = omap_mcbsp_probe,
1323 .remove = omap_mcbsp_remove,
1324 .playback = {
1325 .channels_min = 1,
1326 .channels_max = 16,
1327 .rates = OMAP_MCBSP_RATES,
1328 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1329 },
1330 .capture = {
1331 .channels_min = 1,
1332 .channels_max = 16,
1333 .rates = OMAP_MCBSP_RATES,
1334 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1335 },
1336 .ops = &mcbsp_dai_ops,
1337 };
1338
1339 static const struct snd_soc_component_driver omap_mcbsp_component = {
1340 .name = "omap-mcbsp",
1341 };
1342
1343 static struct omap_mcbsp_platform_data omap2420_pdata = {
1344 .reg_step = 4,
1345 .reg_size = 2,
1346 };
1347
1348 static struct omap_mcbsp_platform_data omap2430_pdata = {
1349 .reg_step = 4,
1350 .reg_size = 4,
1351 .has_ccr = true,
1352 };
1353
1354 static struct omap_mcbsp_platform_data omap3_pdata = {
1355 .reg_step = 4,
1356 .reg_size = 4,
1357 .has_ccr = true,
1358 .has_wakeup = true,
1359 };
1360
1361 static struct omap_mcbsp_platform_data omap4_pdata = {
1362 .reg_step = 4,
1363 .reg_size = 4,
1364 .has_ccr = true,
1365 .has_wakeup = true,
1366 };
1367
1368 static const struct of_device_id omap_mcbsp_of_match[] = {
1369 {
1370 .compatible = "ti,omap2420-mcbsp",
1371 .data = &omap2420_pdata,
1372 },
1373 {
1374 .compatible = "ti,omap2430-mcbsp",
1375 .data = &omap2430_pdata,
1376 },
1377 {
1378 .compatible = "ti,omap3-mcbsp",
1379 .data = &omap3_pdata,
1380 },
1381 {
1382 .compatible = "ti,omap4-mcbsp",
1383 .data = &omap4_pdata,
1384 },
1385 { },
1386 };
1387 MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
1388
1389 static int asoc_mcbsp_probe(struct platform_device *pdev)
1390 {
1391 struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
1392 struct omap_mcbsp *mcbsp;
1393 const struct of_device_id *match;
1394 int ret;
1395
1396 match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
1397 if (match) {
1398 struct device_node *node = pdev->dev.of_node;
1399 struct omap_mcbsp_platform_data *pdata_quirk = pdata;
1400 int buffer_size;
1401
1402 pdata = devm_kzalloc(&pdev->dev,
1403 sizeof(struct omap_mcbsp_platform_data),
1404 GFP_KERNEL);
1405 if (!pdata)
1406 return -ENOMEM;
1407
1408 memcpy(pdata, match->data, sizeof(*pdata));
1409 if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
1410 pdata->buffer_size = buffer_size;
1411 if (pdata_quirk)
1412 pdata->force_ick_on = pdata_quirk->force_ick_on;
1413 } else if (!pdata) {
1414 dev_err(&pdev->dev, "missing platform data.\n");
1415 return -EINVAL;
1416 }
1417 mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
1418 if (!mcbsp)
1419 return -ENOMEM;
1420
1421 mcbsp->id = pdev->id;
1422 mcbsp->pdata = pdata;
1423 mcbsp->dev = &pdev->dev;
1424 platform_set_drvdata(pdev, mcbsp);
1425
1426 ret = omap_mcbsp_init(pdev);
1427 if (ret)
1428 return ret;
1429
1430 if (mcbsp->pdata->reg_size == 2) {
1431 omap_mcbsp_dai.playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
1432 omap_mcbsp_dai.capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
1433 }
1434
1435 ret = devm_snd_soc_register_component(&pdev->dev,
1436 &omap_mcbsp_component,
1437 &omap_mcbsp_dai, 1);
1438 if (ret)
1439 return ret;
1440
1441 return sdma_pcm_platform_register(&pdev->dev, NULL, NULL);
1442 }
1443
1444 static int asoc_mcbsp_remove(struct platform_device *pdev)
1445 {
1446 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1447
1448 if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
1449 mcbsp->pdata->ops->free(mcbsp->id);
1450
1451 if (pm_qos_request_active(&mcbsp->pm_qos_req))
1452 pm_qos_remove_request(&mcbsp->pm_qos_req);
1453
1454 if (mcbsp->pdata->buffer_size)
1455 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
1456
1457 omap_mcbsp_st_cleanup(pdev);
1458
1459 clk_put(mcbsp->fclk);
1460
1461 return 0;
1462 }
1463
1464 static struct platform_driver asoc_mcbsp_driver = {
1465 .driver = {
1466 .name = "omap-mcbsp",
1467 .of_match_table = omap_mcbsp_of_match,
1468 },
1469
1470 .probe = asoc_mcbsp_probe,
1471 .remove = asoc_mcbsp_remove,
1472 };
1473
1474 module_platform_driver(asoc_mcbsp_driver);
1475
1476 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
1477 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
1478 MODULE_LICENSE("GPL");
1479 MODULE_ALIAS("platform:omap-mcbsp");
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