sound/soc/pxa/pxa-ssp.c

   1 /*
   2  * pxa-ssp.c  --  ALSA Soc Audio Layer
   3  *
   4  * Copyright 2005,2008 Wolfson Microelectronics PLC.
   5  * Author: Liam Girdwood
   6  *         Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  * TODO:
  14  *  o Test network mode for > 16bit sample size
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/slab.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/io.h>
  23
  24 #include <asm/irq.h>
  25
  26 #include <sound/core.h>
  27 #include <sound/pcm.h>
  28 #include <sound/initval.h>
  29 #include <sound/pcm_params.h>
  30 #include <sound/soc.h>
  31 #include <sound/pxa2xx-lib.h>
  32
  33 #include <mach/hardware.h>
  34 #include <mach/dma.h>
  35 #include <mach/audio.h>
  36 #include <plat/ssp.h>
  37
  38 #include "../../arm/pxa2xx-pcm.h"
  39 #include "pxa-ssp.h"
  40
  41 /*
  42  * SSP audio private data
  43  */
  44 struct ssp_priv {
  45         struct ssp_device *ssp;
  46         unsigned int sysclk;
  47         int dai_fmt;
  48 #ifdef CONFIG_PM
  49         uint32_t        cr0;
  50         uint32_t        cr1;
  51         uint32_t        to;
  52         uint32_t        psp;
  53 #endif
  54 };
  55
  56 static void dump_registers(struct ssp_device *ssp)
  57 {
  58         dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
  59                  pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1),
  60                  pxa_ssp_read_reg(ssp, SSTO));
  61
  62         dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
  63                  pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR),
  64                  pxa_ssp_read_reg(ssp, SSACD));
  65 }
  66
  67 static void pxa_ssp_enable(struct ssp_device *ssp)
  68 {
  69         uint32_t sscr0;
  70
  71         sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
  72         __raw_writel(sscr0, ssp->mmio_base + SSCR0);
  73 }
  74
  75 static void pxa_ssp_disable(struct ssp_device *ssp)
  76 {
  77         uint32_t sscr0;
  78
  79         sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
  80         __raw_writel(sscr0, ssp->mmio_base + SSCR0);
  81 }
  82
  83 struct pxa2xx_pcm_dma_data {
  84         struct pxa2xx_pcm_dma_params params;
  85         char name[20];
  86 };
  87
  88 static struct pxa2xx_pcm_dma_params *
  89 pxa_ssp_get_dma_params(struct ssp_device *ssp, int width4, int out)
  90 {
  91         struct pxa2xx_pcm_dma_data *dma;
  92
  93         dma = kzalloc(sizeof(struct pxa2xx_pcm_dma_data), GFP_KERNEL);
  94         if (dma == NULL)
  95                 return NULL;
  96
  97         snprintf(dma->name, 20, "SSP%d PCM %s %s", ssp->port_id,
  98                         width4 ? "32-bit" : "16-bit", out ? "out" : "in");
  99
 100         dma->params.name = dma->name;
 101         dma->params.drcmr = &DRCMR(out ? ssp->drcmr_tx : ssp->drcmr_rx);
 102         dma->params.dcmd = (out ? (DCMD_INCSRCADDR | DCMD_FLOWTRG) :
 103                                   (DCMD_INCTRGADDR | DCMD_FLOWSRC)) |
 104                         (width4 ? DCMD_WIDTH4 : DCMD_WIDTH2) | DCMD_BURST16;
 105         dma->params.dev_addr = ssp->phys_base + SSDR;
 106
 107         return &dma->params;
 108 }
 109
 110 static int pxa_ssp_startup(struct snd_pcm_substream *substream,
 111                            struct snd_soc_dai *cpu_dai)
 112 {
 113         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 114         struct ssp_device *ssp = priv->ssp;
 115         int ret = 0;
 116
 117         if (!cpu_dai->active) {
 118                 clk_enable(ssp->clk);
 119                 pxa_ssp_disable(ssp);
 120         }
 121
 122         kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
 123         snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
 124
 125         return ret;
 126 }
 127
 128 static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
 129                              struct snd_soc_dai *cpu_dai)
 130 {
 131         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 132         struct ssp_device *ssp = priv->ssp;
 133
 134         if (!cpu_dai->active) {
 135                 pxa_ssp_disable(ssp);
 136                 clk_disable(ssp->clk);
 137         }
 138
 139         kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
 140         snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
 141 }
 142
 143 #ifdef CONFIG_PM
 144
 145 static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
 146 {
 147         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 148         struct ssp_device *ssp = priv->ssp;
 149
 150         if (!cpu_dai->active)
 151                 clk_enable(ssp->clk);
 152
 153         priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
 154         priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
 155         priv->to  = __raw_readl(ssp->mmio_base + SSTO);
 156         priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
 157
 158         pxa_ssp_disable(ssp);
 159         clk_disable(ssp->clk);
 160         return 0;
 161 }
 162
 163 static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
 164 {
 165         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 166         struct ssp_device *ssp = priv->ssp;
 167         uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
 168
 169         clk_enable(ssp->clk);
 170
 171         __raw_writel(sssr, ssp->mmio_base + SSSR);
 172         __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
 173         __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
 174         __raw_writel(priv->to,  ssp->mmio_base + SSTO);
 175         __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
 176
 177         if (cpu_dai->active)
 178                 pxa_ssp_enable(ssp);
 179         else
 180                 clk_disable(ssp->clk);
 181
 182         return 0;
 183 }
 184
 185 #else
 186 #define pxa_ssp_suspend NULL
 187 #define pxa_ssp_resume  NULL
 188 #endif
 189
 190 /**
 191  * ssp_set_clkdiv - set SSP clock divider
 192  * @div: serial clock rate divider
 193  */
 194 static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
 195 {
 196         u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
 197
 198         if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) {
 199                 sscr0 &= ~0x0000ff00;
 200                 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
 201         } else {
 202                 sscr0 &= ~0x000fff00;
 203                 sscr0 |= (div - 1) << 8;     /* 1..4096 */
 204         }
 205         pxa_ssp_write_reg(ssp, SSCR0, sscr0);
 206 }
 207
 208 /**
 209  * pxa_ssp_get_clkdiv - get SSP clock divider
 210  */
 211 static u32 pxa_ssp_get_scr(struct ssp_device *ssp)
 212 {
 213         u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
 214         u32 div;
 215
 216         if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP)
 217                 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
 218         else
 219                 div = ((sscr0 >> 8) & 0xfff) + 1;
 220         return div;
 221 }
 222
 223 /*
 224  * Set the SSP ports SYSCLK.
 225  */
 226 static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 227         int clk_id, unsigned int freq, int dir)
 228 {
 229         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 230         struct ssp_device *ssp = priv->ssp;
 231         int val;
 232
 233         u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
 234                 ~(SSCR0_ECS |  SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
 235
 236         dev_dbg(&ssp->pdev->dev,
 237                 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
 238                 cpu_dai->id, clk_id, freq);
 239
 240         switch (clk_id) {
 241         case PXA_SSP_CLK_NET_PLL:
 242                 sscr0 |= SSCR0_MOD;
 243                 break;
 244         case PXA_SSP_CLK_PLL:
 245                 /* Internal PLL is fixed */
 246                 if (cpu_is_pxa25x())
 247                         priv->sysclk = 1843200;
 248                 else
 249                         priv->sysclk = 13000000;
 250                 break;
 251         case PXA_SSP_CLK_EXT:
 252                 priv->sysclk = freq;
 253                 sscr0 |= SSCR0_ECS;
 254                 break;
 255         case PXA_SSP_CLK_NET:
 256                 priv->sysclk = freq;
 257                 sscr0 |= SSCR0_NCS | SSCR0_MOD;
 258                 break;
 259         case PXA_SSP_CLK_AUDIO:
 260                 priv->sysclk = 0;
 261                 pxa_ssp_set_scr(ssp, 1);
 262                 sscr0 |= SSCR0_ACS;
 263                 break;
 264         default:
 265                 return -ENODEV;
 266         }
 267
 268         /* The SSP clock must be disabled when changing SSP clock mode
 269          * on PXA2xx.  On PXA3xx it must be enabled when doing so. */
 270         if (!cpu_is_pxa3xx())
 271                 clk_disable(ssp->clk);
 272         val = pxa_ssp_read_reg(ssp, SSCR0) | sscr0;
 273         pxa_ssp_write_reg(ssp, SSCR0, val);
 274         if (!cpu_is_pxa3xx())
 275                 clk_enable(ssp->clk);
 276
 277         return 0;
 278 }
 279
 280 /*
 281  * Set the SSP clock dividers.
 282  */
 283 static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
 284         int div_id, int div)
 285 {
 286         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 287         struct ssp_device *ssp = priv->ssp;
 288         int val;
 289
 290         switch (div_id) {
 291         case PXA_SSP_AUDIO_DIV_ACDS:
 292                 val = (pxa_ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
 293                 pxa_ssp_write_reg(ssp, SSACD, val);
 294                 break;
 295         case PXA_SSP_AUDIO_DIV_SCDB:
 296                 val = pxa_ssp_read_reg(ssp, SSACD);
 297                 val &= ~SSACD_SCDB;
 298 #if defined(CONFIG_PXA3xx)
 299                 if (cpu_is_pxa3xx())
 300                         val &= ~SSACD_SCDX8;
 301 #endif
 302                 switch (div) {
 303                 case PXA_SSP_CLK_SCDB_1:
 304                         val |= SSACD_SCDB;
 305                         break;
 306                 case PXA_SSP_CLK_SCDB_4:
 307                         break;
 308 #if defined(CONFIG_PXA3xx)
 309                 case PXA_SSP_CLK_SCDB_8:
 310                         if (cpu_is_pxa3xx())
 311                                 val |= SSACD_SCDX8;
 312                         else
 313                                 return -EINVAL;
 314                         break;
 315 #endif
 316                 default:
 317                         return -EINVAL;
 318                 }
 319                 pxa_ssp_write_reg(ssp, SSACD, val);
 320                 break;
 321         case PXA_SSP_DIV_SCR:
 322                 pxa_ssp_set_scr(ssp, div);
 323                 break;
 324         default:
 325                 return -ENODEV;
 326         }
 327
 328         return 0;
 329 }
 330
 331 /*
 332  * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
 333  */
 334 static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
 335         int source, unsigned int freq_in, unsigned int freq_out)
 336 {
 337         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 338         struct ssp_device *ssp = priv->ssp;
 339         u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
 340
 341 #if defined(CONFIG_PXA3xx)
 342         if (cpu_is_pxa3xx())
 343                 pxa_ssp_write_reg(ssp, SSACDD, 0);
 344 #endif
 345
 346         switch (freq_out) {
 347         case 5622000:
 348                 break;
 349         case 11345000:
 350                 ssacd |= (0x1 << 4);
 351                 break;
 352         case 12235000:
 353                 ssacd |= (0x2 << 4);
 354                 break;
 355         case 14857000:
 356                 ssacd |= (0x3 << 4);
 357                 break;
 358         case 32842000:
 359                 ssacd |= (0x4 << 4);
 360                 break;
 361         case 48000000:
 362                 ssacd |= (0x5 << 4);
 363                 break;
 364         case 0:
 365                 /* Disable */
 366                 break;
 367
 368         default:
 369 #ifdef CONFIG_PXA3xx
 370                 /* PXA3xx has a clock ditherer which can be used to generate
 371                  * a wider range of frequencies - calculate a value for it.
 372                  */
 373                 if (cpu_is_pxa3xx()) {
 374                         u32 val;
 375                         u64 tmp = 19968;
 376                         tmp *= 1000000;
 377                         do_div(tmp, freq_out);
 378                         val = tmp;
 379
 380                         val = (val << 16) | 64;
 381                         pxa_ssp_write_reg(ssp, SSACDD, val);
 382
 383                         ssacd |= (0x6 << 4);
 384
 385                         dev_dbg(&ssp->pdev->dev,
 386                                 "Using SSACDD %x to supply %uHz\n",
 387                                 val, freq_out);
 388                         break;
 389                 }
 390 #endif
 391
 392                 return -EINVAL;
 393         }
 394
 395         pxa_ssp_write_reg(ssp, SSACD, ssacd);
 396
 397         return 0;
 398 }
 399
 400 /*
 401  * Set the active slots in TDM/Network mode
 402  */
 403 static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
 404         unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
 405 {
 406         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 407         struct ssp_device *ssp = priv->ssp;
 408         u32 sscr0;
 409
 410         sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
 411         sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
 412
 413         /* set slot width */
 414         if (slot_width > 16)
 415                 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
 416         else
 417                 sscr0 |= SSCR0_DataSize(slot_width);
 418
 419         if (slots > 1) {
 420                 /* enable network mode */
 421                 sscr0 |= SSCR0_MOD;
 422
 423                 /* set number of active slots */
 424                 sscr0 |= SSCR0_SlotsPerFrm(slots);
 425
 426                 /* set active slot mask */
 427                 pxa_ssp_write_reg(ssp, SSTSA, tx_mask);
 428                 pxa_ssp_write_reg(ssp, SSRSA, rx_mask);
 429         }
 430         pxa_ssp_write_reg(ssp, SSCR0, sscr0);
 431
 432         return 0;
 433 }
 434
 435 /*
 436  * Tristate the SSP DAI lines
 437  */
 438 static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
 439         int tristate)
 440 {
 441         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 442         struct ssp_device *ssp = priv->ssp;
 443         u32 sscr1;
 444
 445         sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
 446         if (tristate)
 447                 sscr1 &= ~SSCR1_TTE;
 448         else
 449                 sscr1 |= SSCR1_TTE;
 450         pxa_ssp_write_reg(ssp, SSCR1, sscr1);
 451
 452         return 0;
 453 }
 454
 455 /*
 456  * Set up the SSP DAI format.
 457  * The SSP Port must be inactive before calling this function as the
 458  * physical interface format is changed.
 459  */
 460 static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 461                 unsigned int fmt)
 462 {
 463         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 464         struct ssp_device *ssp = priv->ssp;
 465         u32 sscr0, sscr1, sspsp, scfr;
 466
 467         /* check if we need to change anything at all */
 468         if (priv->dai_fmt == fmt)
 469                 return 0;
 470
 471         /* we can only change the settings if the port is not in use */
 472         if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) {
 473                 dev_err(&ssp->pdev->dev,
 474                         "can't change hardware dai format: stream is in use");
 475                 return -EINVAL;
 476         }
 477
 478         /* reset port settings */
 479         sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
 480                 ~(SSCR0_ECS |  SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
 481         sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
 482         sspsp = 0;
 483
 484         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 485         case SND_SOC_DAIFMT_CBM_CFM:
 486                 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR;
 487                 break;
 488         case SND_SOC_DAIFMT_CBM_CFS:
 489                 sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR;
 490                 break;
 491         case SND_SOC_DAIFMT_CBS_CFS:
 492                 break;
 493         default:
 494                 return -EINVAL;
 495         }
 496
 497         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 498         case SND_SOC_DAIFMT_NB_NF:
 499                 sspsp |= SSPSP_SFRMP;
 500                 break;
 501         case SND_SOC_DAIFMT_NB_IF:
 502                 break;
 503         case SND_SOC_DAIFMT_IB_IF:
 504                 sspsp |= SSPSP_SCMODE(2);
 505                 break;
 506         case SND_SOC_DAIFMT_IB_NF:
 507                 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
 508                 break;
 509         default:
 510                 return -EINVAL;
 511         }
 512
 513         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 514         case SND_SOC_DAIFMT_I2S:
 515                 sscr0 |= SSCR0_PSP;
 516                 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
 517                 /* See hw_params() */
 518                 break;
 519
 520         case SND_SOC_DAIFMT_DSP_A:
 521                 sspsp |= SSPSP_FSRT;
 522         case SND_SOC_DAIFMT_DSP_B:
 523                 sscr0 |= SSCR0_MOD | SSCR0_PSP;
 524                 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
 525                 break;
 526
 527         default:
 528                 return -EINVAL;
 529         }
 530
 531         pxa_ssp_write_reg(ssp, SSCR0, sscr0);
 532         pxa_ssp_write_reg(ssp, SSCR1, sscr1);
 533         pxa_ssp_write_reg(ssp, SSPSP, sspsp);
 534
 535         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 536         case SND_SOC_DAIFMT_CBM_CFM:
 537         case SND_SOC_DAIFMT_CBM_CFS:
 538                 scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR;
 539                 pxa_ssp_write_reg(ssp, SSCR1, scfr);
 540
 541                 while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY)
 542                         cpu_relax();
 543                 break;
 544         }
 545
 546         dump_registers(ssp);
 547
 548         /* Since we are configuring the timings for the format by hand
 549          * we have to defer some things until hw_params() where we
 550          * know parameters like the sample size.
 551          */
 552         priv->dai_fmt = fmt;
 553
 554         return 0;
 555 }
 556
 557 /*
 558  * Set the SSP audio DMA parameters and sample size.
 559  * Can be called multiple times by oss emulation.
 560  */
 561 static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
 562                                 struct snd_pcm_hw_params *params,
 563                                 struct snd_soc_dai *cpu_dai)
 564 {
 565         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 566         struct ssp_device *ssp = priv->ssp;
 567         int chn = params_channels(params);
 568         u32 sscr0;
 569         u32 sspsp;
 570         int width = snd_pcm_format_physical_width(params_format(params));
 571         int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf;
 572         struct pxa2xx_pcm_dma_params *dma_data;
 573
 574         dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
 575
 576         /* generate correct DMA params */
 577         kfree(dma_data);
 578
 579         /* Network mode with one active slot (ttsa == 1) can be used
 580          * to force 16-bit frame width on the wire (for S16_LE), even
 581          * with two channels. Use 16-bit DMA transfers for this case.
 582          */
 583         dma_data = pxa_ssp_get_dma_params(ssp,
 584                         ((chn == 2) && (ttsa != 1)) || (width == 32),
 585                         substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 586
 587         snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
 588
 589         /* we can only change the settings if the port is not in use */
 590         if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
 591                 return 0;
 592
 593         /* clear selected SSP bits */
 594         sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
 595
 596         /* bit size */
 597         switch (params_format(params)) {
 598         case SNDRV_PCM_FORMAT_S16_LE:
 599 #ifdef CONFIG_PXA3xx
 600                 if (cpu_is_pxa3xx())
 601                         sscr0 |= SSCR0_FPCKE;
 602 #endif
 603                 sscr0 |= SSCR0_DataSize(16);
 604                 break;
 605         case SNDRV_PCM_FORMAT_S24_LE:
 606                 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
 607                 break;
 608         case SNDRV_PCM_FORMAT_S32_LE:
 609                 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
 610                 break;
 611         }
 612         pxa_ssp_write_reg(ssp, SSCR0, sscr0);
 613
 614         switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 615         case SND_SOC_DAIFMT_I2S:
 616                sspsp = pxa_ssp_read_reg(ssp, SSPSP);
 617
 618                 if ((pxa_ssp_get_scr(ssp) == 4) && (width == 16)) {
 619                         /* This is a special case where the bitclk is 64fs
 620                         * and we're not dealing with 2*32 bits of audio
 621                         * samples.
 622                         *
 623                         * The SSP values used for that are all found out by
 624                         * trying and failing a lot; some of the registers
 625                         * needed for that mode are only available on PXA3xx.
 626                         */
 627
 628 #ifdef CONFIG_PXA3xx
 629                         if (!cpu_is_pxa3xx())
 630                                 return -EINVAL;
 631
 632                         sspsp |= SSPSP_SFRMWDTH(width * 2);
 633                         sspsp |= SSPSP_SFRMDLY(width * 4);
 634                         sspsp |= SSPSP_EDMYSTOP(3);
 635                         sspsp |= SSPSP_DMYSTOP(3);
 636                         sspsp |= SSPSP_DMYSTRT(1);
 637 #else
 638                         return -EINVAL;
 639 #endif
 640                 } else {
 641                         /* The frame width is the width the LRCLK is
 642                          * asserted for; the delay is expressed in
 643                          * half cycle units.  We need the extra cycle
 644                          * because the data starts clocking out one BCLK
 645                          * after LRCLK changes polarity.
 646                          */
 647                         sspsp |= SSPSP_SFRMWDTH(width + 1);
 648                         sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
 649                         sspsp |= SSPSP_DMYSTRT(1);
 650                 }
 651
 652                 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
 653                 break;
 654         default:
 655                 break;
 656         }
 657
 658         /* When we use a network mode, we always require TDM slots
 659          * - complain loudly and fail if they've not been set up yet.
 660          */
 661         if ((sscr0 & SSCR0_MOD) && !ttsa) {
 662                 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
 663                 return -EINVAL;
 664         }
 665
 666         dump_registers(ssp);
 667
 668         return 0;
 669 }
 670
 671 static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
 672                            struct snd_soc_dai *cpu_dai)
 673 {
 674         int ret = 0;
 675         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 676         struct ssp_device *ssp = priv->ssp;
 677         int val;
 678
 679         switch (cmd) {
 680         case SNDRV_PCM_TRIGGER_RESUME:
 681                 pxa_ssp_enable(ssp);
 682                 break;
 683         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 684                 val = pxa_ssp_read_reg(ssp, SSCR1);
 685                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 686                         val |= SSCR1_TSRE;
 687                 else
 688                         val |= SSCR1_RSRE;
 689                 pxa_ssp_write_reg(ssp, SSCR1, val);
 690                 val = pxa_ssp_read_reg(ssp, SSSR);
 691                 pxa_ssp_write_reg(ssp, SSSR, val);
 692                 break;
 693         case SNDRV_PCM_TRIGGER_START:
 694                 val = pxa_ssp_read_reg(ssp, SSCR1);
 695                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 696                         val |= SSCR1_TSRE;
 697                 else
 698                         val |= SSCR1_RSRE;
 699                 pxa_ssp_write_reg(ssp, SSCR1, val);
 700                 pxa_ssp_enable(ssp);
 701                 break;
 702         case SNDRV_PCM_TRIGGER_STOP:
 703                 val = pxa_ssp_read_reg(ssp, SSCR1);
 704                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 705                         val &= ~SSCR1_TSRE;
 706                 else
 707                         val &= ~SSCR1_RSRE;
 708                 pxa_ssp_write_reg(ssp, SSCR1, val);
 709                 break;
 710         case SNDRV_PCM_TRIGGER_SUSPEND:
 711                 pxa_ssp_disable(ssp);
 712                 break;
 713         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 714                 val = pxa_ssp_read_reg(ssp, SSCR1);
 715                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 716                         val &= ~SSCR1_TSRE;
 717                 else
 718                         val &= ~SSCR1_RSRE;
 719                 pxa_ssp_write_reg(ssp, SSCR1, val);
 720                 break;
 721
 722         default:
 723                 ret = -EINVAL;
 724         }
 725
 726         dump_registers(ssp);
 727
 728         return ret;
 729 }
 730
 731 static int pxa_ssp_probe(struct snd_soc_dai *dai)
 732 {
 733         struct ssp_priv *priv;
 734         int ret;
 735
 736         priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
 737         if (!priv)
 738                 return -ENOMEM;
 739
 740         priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
 741         if (priv->ssp == NULL) {
 742                 ret = -ENODEV;
 743                 goto err_priv;
 744         }
 745
 746         priv->dai_fmt = (unsigned int) -1;
 747         snd_soc_dai_set_drvdata(dai, priv);
 748
 749         return 0;
 750
 751 err_priv:
 752         kfree(priv);
 753         return ret;
 754 }
 755
 756 static int pxa_ssp_remove(struct snd_soc_dai *dai)
 757 {
 758         struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai);
 759
 760         pxa_ssp_free(priv->ssp);
 761         kfree(priv);
 762         return 0;
 763 }
 764
 765 #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
 766                           SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
 767                           SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
 768                           SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
 769
 770 #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 771                             SNDRV_PCM_FMTBIT_S24_LE |   \
 772                             SNDRV_PCM_FMTBIT_S32_LE)
 773
 774 static struct snd_soc_dai_ops pxa_ssp_dai_ops = {
 775         .startup        = pxa_ssp_startup,
 776         .shutdown       = pxa_ssp_shutdown,
 777         .trigger        = pxa_ssp_trigger,
 778         .hw_params      = pxa_ssp_hw_params,
 779         .set_sysclk     = pxa_ssp_set_dai_sysclk,
 780         .set_clkdiv     = pxa_ssp_set_dai_clkdiv,
 781         .set_pll        = pxa_ssp_set_dai_pll,
 782         .set_fmt        = pxa_ssp_set_dai_fmt,
 783         .set_tdm_slot   = pxa_ssp_set_dai_tdm_slot,
 784         .set_tristate   = pxa_ssp_set_dai_tristate,
 785 };
 786
 787 static struct snd_soc_dai_driver pxa_ssp_dai = {
 788                 .probe = pxa_ssp_probe,
 789                 .remove = pxa_ssp_remove,
 790                 .suspend = pxa_ssp_suspend,
 791                 .resume = pxa_ssp_resume,
 792                 .playback = {
 793                         .channels_min = 1,
 794                         .channels_max = 8,
 795                         .rates = PXA_SSP_RATES,
 796                         .formats = PXA_SSP_FORMATS,
 797                 },
 798                 .capture = {
 799                          .channels_min = 1,
 800                          .channels_max = 8,
 801                         .rates = PXA_SSP_RATES,
 802                         .formats = PXA_SSP_FORMATS,
 803                  },
 804                 .ops = &pxa_ssp_dai_ops,
 805 };
 806
 807 static __devinit int asoc_ssp_probe(struct platform_device *pdev)
 808 {
 809         return snd_soc_register_dai(&pdev->dev, &pxa_ssp_dai);
 810 }
 811
 812 static int __devexit asoc_ssp_remove(struct platform_device *pdev)
 813 {
 814         snd_soc_unregister_dai(&pdev->dev);
 815         return 0;
 816 }
 817
 818 static struct platform_driver asoc_ssp_driver = {
 819         .driver = {
 820                         .name = "pxa-ssp-dai",
 821                         .owner = THIS_MODULE,
 822         },
 823
 824         .probe = asoc_ssp_probe,
 825         .remove = __devexit_p(asoc_ssp_remove),
 826 };
 827
 828 static int __init pxa_ssp_init(void)
 829 {
 830         return platform_driver_register(&asoc_ssp_driver);
 831 }
 832 module_init(pxa_ssp_init);
 833
 834 static void __exit pxa_ssp_exit(void)
 835 {
 836         platform_driver_unregister(&asoc_ssp_driver);
 837 }
 838 module_exit(pxa_ssp_exit);
 839
 840 /* Module information */
 841 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
 842 MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
 843 MODULE_LICENSE("GPL");