2 * pxa-ssp.c -- ALSA Soc Audio Layer
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 * o Test network mode for > 16bit sample size
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/clk.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/initval.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/pxa2xx-lib.h>
32 #include <mach/hardware.h>
34 #include <mach/regs-ssp.h>
35 #include <mach/audio.h>
38 #include "pxa2xx-pcm.h"
42 * SSP audio private data
49 struct ssp_state state
;
53 #define PXA2xx_SSP1_BASE 0x41000000
54 #define PXA27x_SSP2_BASE 0x41700000
55 #define PXA27x_SSP3_BASE 0x41900000
56 #define PXA3xx_SSP4_BASE 0x41a00000
58 static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_out
= {
59 .name
= "SSP1 PCM Mono out",
60 .dev_addr
= PXA2xx_SSP1_BASE
+ SSDR
,
62 .dcmd
= DCMD_INCSRCADDR
| DCMD_FLOWTRG
|
63 DCMD_BURST16
| DCMD_WIDTH2
,
66 static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_in
= {
67 .name
= "SSP1 PCM Mono in",
68 .dev_addr
= PXA2xx_SSP1_BASE
+ SSDR
,
70 .dcmd
= DCMD_INCTRGADDR
| DCMD_FLOWSRC
|
71 DCMD_BURST16
| DCMD_WIDTH2
,
74 static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_out
= {
75 .name
= "SSP1 PCM Stereo out",
76 .dev_addr
= PXA2xx_SSP1_BASE
+ SSDR
,
78 .dcmd
= DCMD_INCSRCADDR
| DCMD_FLOWTRG
|
79 DCMD_BURST16
| DCMD_WIDTH4
,
82 static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_in
= {
83 .name
= "SSP1 PCM Stereo in",
84 .dev_addr
= PXA2xx_SSP1_BASE
+ SSDR
,
86 .dcmd
= DCMD_INCTRGADDR
| DCMD_FLOWSRC
|
87 DCMD_BURST16
| DCMD_WIDTH4
,
90 static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_out
= {
91 .name
= "SSP2 PCM Mono out",
92 .dev_addr
= PXA27x_SSP2_BASE
+ SSDR
,
94 .dcmd
= DCMD_INCSRCADDR
| DCMD_FLOWTRG
|
95 DCMD_BURST16
| DCMD_WIDTH2
,
98 static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_in
= {
99 .name
= "SSP2 PCM Mono in",
100 .dev_addr
= PXA27x_SSP2_BASE
+ SSDR
,
102 .dcmd
= DCMD_INCTRGADDR
| DCMD_FLOWSRC
|
103 DCMD_BURST16
| DCMD_WIDTH2
,
106 static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_out
= {
107 .name
= "SSP2 PCM Stereo out",
108 .dev_addr
= PXA27x_SSP2_BASE
+ SSDR
,
110 .dcmd
= DCMD_INCSRCADDR
| DCMD_FLOWTRG
|
111 DCMD_BURST16
| DCMD_WIDTH4
,
114 static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_in
= {
115 .name
= "SSP2 PCM Stereo in",
116 .dev_addr
= PXA27x_SSP2_BASE
+ SSDR
,
118 .dcmd
= DCMD_INCTRGADDR
| DCMD_FLOWSRC
|
119 DCMD_BURST16
| DCMD_WIDTH4
,
122 static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_out
= {
123 .name
= "SSP3 PCM Mono out",
124 .dev_addr
= PXA27x_SSP3_BASE
+ SSDR
,
126 .dcmd
= DCMD_INCSRCADDR
| DCMD_FLOWTRG
|
127 DCMD_BURST16
| DCMD_WIDTH2
,
130 static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_in
= {
131 .name
= "SSP3 PCM Mono in",
132 .dev_addr
= PXA27x_SSP3_BASE
+ SSDR
,
134 .dcmd
= DCMD_INCTRGADDR
| DCMD_FLOWSRC
|
135 DCMD_BURST16
| DCMD_WIDTH2
,
138 static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_out
= {
139 .name
= "SSP3 PCM Stereo out",
140 .dev_addr
= PXA27x_SSP3_BASE
+ SSDR
,
142 .dcmd
= DCMD_INCSRCADDR
| DCMD_FLOWTRG
|
143 DCMD_BURST16
| DCMD_WIDTH4
,
146 static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_in
= {
147 .name
= "SSP3 PCM Stereo in",
148 .dev_addr
= PXA27x_SSP3_BASE
+ SSDR
,
150 .dcmd
= DCMD_INCTRGADDR
| DCMD_FLOWSRC
|
151 DCMD_BURST16
| DCMD_WIDTH4
,
154 static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_out
= {
155 .name
= "SSP4 PCM Mono out",
156 .dev_addr
= PXA3xx_SSP4_BASE
+ SSDR
,
158 .dcmd
= DCMD_INCSRCADDR
| DCMD_FLOWTRG
|
159 DCMD_BURST16
| DCMD_WIDTH2
,
162 static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_in
= {
163 .name
= "SSP4 PCM Mono in",
164 .dev_addr
= PXA3xx_SSP4_BASE
+ SSDR
,
166 .dcmd
= DCMD_INCTRGADDR
| DCMD_FLOWSRC
|
167 DCMD_BURST16
| DCMD_WIDTH2
,
170 static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_out
= {
171 .name
= "SSP4 PCM Stereo out",
172 .dev_addr
= PXA3xx_SSP4_BASE
+ SSDR
,
174 .dcmd
= DCMD_INCSRCADDR
| DCMD_FLOWTRG
|
175 DCMD_BURST16
| DCMD_WIDTH4
,
178 static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_in
= {
179 .name
= "SSP4 PCM Stereo in",
180 .dev_addr
= PXA3xx_SSP4_BASE
+ SSDR
,
182 .dcmd
= DCMD_INCTRGADDR
| DCMD_FLOWSRC
|
183 DCMD_BURST16
| DCMD_WIDTH4
,
186 static void dump_registers(struct ssp_device
*ssp
)
188 dev_dbg(&ssp
->pdev
->dev
, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
189 ssp_read_reg(ssp
, SSCR0
), ssp_read_reg(ssp
, SSCR1
),
190 ssp_read_reg(ssp
, SSTO
));
192 dev_dbg(&ssp
->pdev
->dev
, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
193 ssp_read_reg(ssp
, SSPSP
), ssp_read_reg(ssp
, SSSR
),
194 ssp_read_reg(ssp
, SSACD
));
197 static struct pxa2xx_pcm_dma_params
*ssp_dma_params
[4][4] = {
199 &pxa_ssp1_pcm_mono_out
, &pxa_ssp1_pcm_mono_in
,
200 &pxa_ssp1_pcm_stereo_out
, &pxa_ssp1_pcm_stereo_in
,
203 &pxa_ssp2_pcm_mono_out
, &pxa_ssp2_pcm_mono_in
,
204 &pxa_ssp2_pcm_stereo_out
, &pxa_ssp2_pcm_stereo_in
,
207 &pxa_ssp3_pcm_mono_out
, &pxa_ssp3_pcm_mono_in
,
208 &pxa_ssp3_pcm_stereo_out
, &pxa_ssp3_pcm_stereo_in
,
211 &pxa_ssp4_pcm_mono_out
, &pxa_ssp4_pcm_mono_in
,
212 &pxa_ssp4_pcm_stereo_out
, &pxa_ssp4_pcm_stereo_in
,
216 static int pxa_ssp_startup(struct snd_pcm_substream
*substream
,
217 struct snd_soc_dai
*dai
)
219 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
220 struct snd_soc_dai
*cpu_dai
= rtd
->dai
->cpu_dai
;
221 struct ssp_priv
*priv
= cpu_dai
->private_data
;
224 if (!cpu_dai
->active
) {
225 priv
->dev
.port
= cpu_dai
->id
+ 1;
226 priv
->dev
.irq
= NO_IRQ
;
227 clk_enable(priv
->dev
.ssp
->clk
);
228 ssp_disable(&priv
->dev
);
233 static void pxa_ssp_shutdown(struct snd_pcm_substream
*substream
,
234 struct snd_soc_dai
*dai
)
236 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
237 struct snd_soc_dai
*cpu_dai
= rtd
->dai
->cpu_dai
;
238 struct ssp_priv
*priv
= cpu_dai
->private_data
;
240 if (!cpu_dai
->active
) {
241 ssp_disable(&priv
->dev
);
242 clk_disable(priv
->dev
.ssp
->clk
);
248 static int pxa_ssp_suspend(struct snd_soc_dai
*cpu_dai
)
250 struct ssp_priv
*priv
= cpu_dai
->private_data
;
252 if (!cpu_dai
->active
)
255 ssp_save_state(&priv
->dev
, &priv
->state
);
256 clk_disable(priv
->dev
.ssp
->clk
);
260 static int pxa_ssp_resume(struct snd_soc_dai
*cpu_dai
)
262 struct ssp_priv
*priv
= cpu_dai
->private_data
;
264 if (!cpu_dai
->active
)
267 clk_enable(priv
->dev
.ssp
->clk
);
268 ssp_restore_state(&priv
->dev
, &priv
->state
);
269 ssp_enable(&priv
->dev
);
275 #define pxa_ssp_suspend NULL
276 #define pxa_ssp_resume NULL
280 * ssp_set_clkdiv - set SSP clock divider
281 * @div: serial clock rate divider
283 static void ssp_set_scr(struct ssp_device
*ssp
, u32 div
)
285 u32 sscr0
= ssp_read_reg(ssp
, SSCR0
);
287 if (cpu_is_pxa25x() && ssp
->type
== PXA25x_SSP
) {
288 sscr0
&= ~0x0000ff00;
289 sscr0
|= ((div
- 2)/2) << 8; /* 2..512 */
291 sscr0
&= ~0x000fff00;
292 sscr0
|= (div
- 1) << 8; /* 1..4096 */
294 ssp_write_reg(ssp
, SSCR0
, sscr0
);
298 * ssp_get_clkdiv - get SSP clock divider
300 static u32
ssp_get_scr(struct ssp_device
*ssp
)
302 u32 sscr0
= ssp_read_reg(ssp
, SSCR0
);
305 if (cpu_is_pxa25x() && ssp
->type
== PXA25x_SSP
)
306 div
= ((sscr0
>> 8) & 0xff) * 2 + 2;
308 div
= ((sscr0
>> 8) & 0xfff) + 1;
313 * Set the SSP ports SYSCLK.
315 static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai
*cpu_dai
,
316 int clk_id
, unsigned int freq
, int dir
)
318 struct ssp_priv
*priv
= cpu_dai
->private_data
;
319 struct ssp_device
*ssp
= priv
->dev
.ssp
;
322 u32 sscr0
= ssp_read_reg(ssp
, SSCR0
) &
323 ~(SSCR0_ECS
| SSCR0_NCS
| SSCR0_MOD
| SSCR0_ACS
);
325 dev_dbg(&ssp
->pdev
->dev
,
326 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %d\n",
327 cpu_dai
->id
, clk_id
, freq
);
330 case PXA_SSP_CLK_NET_PLL
:
333 case PXA_SSP_CLK_PLL
:
334 /* Internal PLL is fixed */
336 priv
->sysclk
= 1843200;
338 priv
->sysclk
= 13000000;
340 case PXA_SSP_CLK_EXT
:
344 case PXA_SSP_CLK_NET
:
346 sscr0
|= SSCR0_NCS
| SSCR0_MOD
;
348 case PXA_SSP_CLK_AUDIO
:
357 /* The SSP clock must be disabled when changing SSP clock mode
358 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
359 if (!cpu_is_pxa3xx())
360 clk_disable(priv
->dev
.ssp
->clk
);
361 val
= ssp_read_reg(ssp
, SSCR0
) | sscr0
;
362 ssp_write_reg(ssp
, SSCR0
, val
);
363 if (!cpu_is_pxa3xx())
364 clk_enable(priv
->dev
.ssp
->clk
);
370 * Set the SSP clock dividers.
372 static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai
*cpu_dai
,
375 struct ssp_priv
*priv
= cpu_dai
->private_data
;
376 struct ssp_device
*ssp
= priv
->dev
.ssp
;
380 case PXA_SSP_AUDIO_DIV_ACDS
:
381 val
= (ssp_read_reg(ssp
, SSACD
) & ~0x7) | SSACD_ACDS(div
);
382 ssp_write_reg(ssp
, SSACD
, val
);
384 case PXA_SSP_AUDIO_DIV_SCDB
:
385 val
= ssp_read_reg(ssp
, SSACD
);
387 #if defined(CONFIG_PXA3xx)
392 case PXA_SSP_CLK_SCDB_1
:
395 case PXA_SSP_CLK_SCDB_4
:
397 #if defined(CONFIG_PXA3xx)
398 case PXA_SSP_CLK_SCDB_8
:
408 ssp_write_reg(ssp
, SSACD
, val
);
410 case PXA_SSP_DIV_SCR
:
411 ssp_set_scr(ssp
, div
);
421 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
423 static int pxa_ssp_set_dai_pll(struct snd_soc_dai
*cpu_dai
,
424 int pll_id
, unsigned int freq_in
, unsigned int freq_out
)
426 struct ssp_priv
*priv
= cpu_dai
->private_data
;
427 struct ssp_device
*ssp
= priv
->dev
.ssp
;
428 u32 ssacd
= ssp_read_reg(ssp
, SSACD
) & ~0x70;
430 #if defined(CONFIG_PXA3xx)
432 ssp_write_reg(ssp
, SSACDD
, 0);
459 /* PXA3xx has a clock ditherer which can be used to generate
460 * a wider range of frequencies - calculate a value for it.
462 if (cpu_is_pxa3xx()) {
466 do_div(tmp
, freq_out
);
469 val
= (val
<< 16) | 64;;
470 ssp_write_reg(ssp
, SSACDD
, val
);
474 dev_dbg(&ssp
->pdev
->dev
,
475 "Using SSACDD %x to supply %dHz\n",
484 ssp_write_reg(ssp
, SSACD
, ssacd
);
490 * Set the active slots in TDM/Network mode
492 static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai
*cpu_dai
,
493 unsigned int mask
, int slots
)
495 struct ssp_priv
*priv
= cpu_dai
->private_data
;
496 struct ssp_device
*ssp
= priv
->dev
.ssp
;
499 sscr0
= ssp_read_reg(ssp
, SSCR0
) & ~SSCR0_SlotsPerFrm(7);
501 /* set number of active slots */
502 sscr0
|= SSCR0_SlotsPerFrm(slots
);
503 ssp_write_reg(ssp
, SSCR0
, sscr0
);
505 /* set active slot mask */
506 ssp_write_reg(ssp
, SSTSA
, mask
);
507 ssp_write_reg(ssp
, SSRSA
, mask
);
512 * Tristate the SSP DAI lines
514 static int pxa_ssp_set_dai_tristate(struct snd_soc_dai
*cpu_dai
,
517 struct ssp_priv
*priv
= cpu_dai
->private_data
;
518 struct ssp_device
*ssp
= priv
->dev
.ssp
;
521 sscr1
= ssp_read_reg(ssp
, SSCR1
);
526 ssp_write_reg(ssp
, SSCR1
, sscr1
);
532 * Set up the SSP DAI format.
533 * The SSP Port must be inactive before calling this function as the
534 * physical interface format is changed.
536 static int pxa_ssp_set_dai_fmt(struct snd_soc_dai
*cpu_dai
,
539 struct ssp_priv
*priv
= cpu_dai
->private_data
;
540 struct ssp_device
*ssp
= priv
->dev
.ssp
;
545 /* check if we need to change anything at all */
546 if (priv
->dai_fmt
== fmt
)
549 /* we can only change the settings if the port is not in use */
550 if (ssp_read_reg(ssp
, SSCR0
) & SSCR0_SSE
) {
551 dev_err(&ssp
->pdev
->dev
,
552 "can't change hardware dai format: stream is in use");
556 /* reset port settings */
557 sscr0
= ssp_read_reg(ssp
, SSCR0
) &
558 (SSCR0_ECS
| SSCR0_NCS
| SSCR0_MOD
| SSCR0_ACS
);
559 sscr1
= SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
562 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
563 case SND_SOC_DAIFMT_CBM_CFM
:
564 sscr1
|= SSCR1_SCLKDIR
| SSCR1_SFRMDIR
;
566 case SND_SOC_DAIFMT_CBM_CFS
:
567 sscr1
|= SSCR1_SCLKDIR
;
569 case SND_SOC_DAIFMT_CBS_CFS
:
575 ssp_write_reg(ssp
, SSCR0
, sscr0
);
576 ssp_write_reg(ssp
, SSCR1
, sscr1
);
577 ssp_write_reg(ssp
, SSPSP
, sspsp
);
579 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
580 case SND_SOC_DAIFMT_I2S
:
582 sscr1
|= SSCR1_RWOT
| SSCR1_TRAIL
;
584 /* See hw_params() */
585 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
586 case SND_SOC_DAIFMT_NB_NF
:
587 sspsp
|= SSPSP_SFRMP
;
589 case SND_SOC_DAIFMT_NB_IF
:
591 case SND_SOC_DAIFMT_IB_IF
:
592 sspsp
|= SSPSP_SCMODE(3);
599 case SND_SOC_DAIFMT_DSP_A
:
601 case SND_SOC_DAIFMT_DSP_B
:
602 sscr0
|= SSCR0_MOD
| SSCR0_PSP
;
603 sscr1
|= SSCR1_TRAIL
| SSCR1_RWOT
;
605 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
606 case SND_SOC_DAIFMT_NB_NF
:
607 sspsp
|= SSPSP_SFRMP
;
609 case SND_SOC_DAIFMT_IB_IF
:
620 ssp_write_reg(ssp
, SSCR0
, sscr0
);
621 ssp_write_reg(ssp
, SSCR1
, sscr1
);
622 ssp_write_reg(ssp
, SSPSP
, sspsp
);
626 /* Since we are configuring the timings for the format by hand
627 * we have to defer some things until hw_params() where we
628 * know parameters like the sample size.
636 * Set the SSP audio DMA parameters and sample size.
637 * Can be called multiple times by oss emulation.
639 static int pxa_ssp_hw_params(struct snd_pcm_substream
*substream
,
640 struct snd_pcm_hw_params
*params
,
641 struct snd_soc_dai
*dai
)
643 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
644 struct snd_soc_dai
*cpu_dai
= rtd
->dai
->cpu_dai
;
645 struct ssp_priv
*priv
= cpu_dai
->private_data
;
646 struct ssp_device
*ssp
= priv
->dev
.ssp
;
647 int dma
= 0, chn
= params_channels(params
);
650 int width
= snd_pcm_format_physical_width(params_format(params
));
651 int ttsa
= ssp_read_reg(ssp
, SSTSA
) & 0xf;
653 /* select correct DMA params */
654 if (substream
->stream
!= SNDRV_PCM_STREAM_PLAYBACK
)
655 dma
= 1; /* capture DMA offset is 1,3 */
656 /* Network mode with one active slot (ttsa == 1) can be used
657 * to force 16-bit frame width on the wire (for S16_LE), even
658 * with two channels. Use 16-bit DMA transfers for this case.
660 if (((chn
== 2) && (ttsa
!= 1)) || (width
== 32))
661 dma
+= 2; /* 32-bit DMA offset is 2, 16-bit is 0 */
663 cpu_dai
->dma_data
= ssp_dma_params
[cpu_dai
->id
][dma
];
665 dev_dbg(&ssp
->pdev
->dev
, "pxa_ssp_hw_params: dma %d\n", dma
);
667 /* we can only change the settings if the port is not in use */
668 if (ssp_read_reg(ssp
, SSCR0
) & SSCR0_SSE
)
671 /* clear selected SSP bits */
672 sscr0
= ssp_read_reg(ssp
, SSCR0
) & ~(SSCR0_DSS
| SSCR0_EDSS
);
673 ssp_write_reg(ssp
, SSCR0
, sscr0
);
676 sscr0
= ssp_read_reg(ssp
, SSCR0
);
677 switch (params_format(params
)) {
678 case SNDRV_PCM_FORMAT_S16_LE
:
681 sscr0
|= SSCR0_FPCKE
;
683 sscr0
|= SSCR0_DataSize(16);
685 case SNDRV_PCM_FORMAT_S24_LE
:
686 sscr0
|= (SSCR0_EDSS
| SSCR0_DataSize(8));
688 case SNDRV_PCM_FORMAT_S32_LE
:
689 sscr0
|= (SSCR0_EDSS
| SSCR0_DataSize(16));
692 ssp_write_reg(ssp
, SSCR0
, sscr0
);
694 switch (priv
->dai_fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
695 case SND_SOC_DAIFMT_I2S
:
696 sspsp
= ssp_read_reg(ssp
, SSPSP
);
698 if ((ssp_get_scr(ssp
) == 4) && (width
== 16)) {
699 /* This is a special case where the bitclk is 64fs
700 * and we're not dealing with 2*32 bits of audio
703 * The SSP values used for that are all found out by
704 * trying and failing a lot; some of the registers
705 * needed for that mode are only available on PXA3xx.
709 if (!cpu_is_pxa3xx())
712 sspsp
|= SSPSP_SFRMWDTH(width
* 2);
713 sspsp
|= SSPSP_SFRMDLY(width
* 4);
714 sspsp
|= SSPSP_EDMYSTOP(3);
715 sspsp
|= SSPSP_DMYSTOP(3);
716 sspsp
|= SSPSP_DMYSTRT(1);
721 /* The frame width is the width the LRCLK is
722 * asserted for; the delay is expressed in
723 * half cycle units. We need the extra cycle
724 * because the data starts clocking out one BCLK
725 * after LRCLK changes polarity.
727 sspsp
|= SSPSP_SFRMWDTH(width
+ 1);
728 sspsp
|= SSPSP_SFRMDLY((width
+ 1) * 2);
729 sspsp
|= SSPSP_DMYSTRT(1);
732 ssp_write_reg(ssp
, SSPSP
, sspsp
);
738 /* When we use a network mode, we always require TDM slots
739 * - complain loudly and fail if they've not been set up yet.
741 if ((sscr0
& SSCR0_MOD
) && !ttsa
) {
742 dev_err(&ssp
->pdev
->dev
, "No TDM timeslot configured\n");
751 static int pxa_ssp_trigger(struct snd_pcm_substream
*substream
, int cmd
,
752 struct snd_soc_dai
*dai
)
754 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
755 struct snd_soc_dai
*cpu_dai
= rtd
->dai
->cpu_dai
;
757 struct ssp_priv
*priv
= cpu_dai
->private_data
;
758 struct ssp_device
*ssp
= priv
->dev
.ssp
;
762 case SNDRV_PCM_TRIGGER_RESUME
:
763 ssp_enable(&priv
->dev
);
765 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
766 val
= ssp_read_reg(ssp
, SSCR1
);
767 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
771 ssp_write_reg(ssp
, SSCR1
, val
);
772 val
= ssp_read_reg(ssp
, SSSR
);
773 ssp_write_reg(ssp
, SSSR
, val
);
775 case SNDRV_PCM_TRIGGER_START
:
776 val
= ssp_read_reg(ssp
, SSCR1
);
777 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
781 ssp_write_reg(ssp
, SSCR1
, val
);
782 ssp_enable(&priv
->dev
);
784 case SNDRV_PCM_TRIGGER_STOP
:
785 val
= ssp_read_reg(ssp
, SSCR1
);
786 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
790 ssp_write_reg(ssp
, SSCR1
, val
);
792 case SNDRV_PCM_TRIGGER_SUSPEND
:
793 ssp_disable(&priv
->dev
);
795 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
796 val
= ssp_read_reg(ssp
, SSCR1
);
797 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
801 ssp_write_reg(ssp
, SSCR1
, val
);
813 static int pxa_ssp_probe(struct platform_device
*pdev
,
814 struct snd_soc_dai
*dai
)
816 struct ssp_priv
*priv
;
819 priv
= kzalloc(sizeof(struct ssp_priv
), GFP_KERNEL
);
823 priv
->dev
.ssp
= ssp_request(dai
->id
+ 1, "SoC audio");
824 if (priv
->dev
.ssp
== NULL
) {
829 priv
->dai_fmt
= (unsigned int) -1;
830 dai
->private_data
= priv
;
839 static void pxa_ssp_remove(struct platform_device
*pdev
,
840 struct snd_soc_dai
*dai
)
842 struct ssp_priv
*priv
= dai
->private_data
;
843 ssp_free(priv
->dev
.ssp
);
846 #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
847 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
848 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
849 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
851 #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
852 SNDRV_PCM_FMTBIT_S24_LE | \
853 SNDRV_PCM_FMTBIT_S32_LE)
855 static struct snd_soc_dai_ops pxa_ssp_dai_ops
= {
856 .startup
= pxa_ssp_startup
,
857 .shutdown
= pxa_ssp_shutdown
,
858 .trigger
= pxa_ssp_trigger
,
859 .hw_params
= pxa_ssp_hw_params
,
860 .set_sysclk
= pxa_ssp_set_dai_sysclk
,
861 .set_clkdiv
= pxa_ssp_set_dai_clkdiv
,
862 .set_pll
= pxa_ssp_set_dai_pll
,
863 .set_fmt
= pxa_ssp_set_dai_fmt
,
864 .set_tdm_slot
= pxa_ssp_set_dai_tdm_slot
,
865 .set_tristate
= pxa_ssp_set_dai_tristate
,
868 struct snd_soc_dai pxa_ssp_dai
[] = {
870 .name
= "pxa2xx-ssp1",
872 .probe
= pxa_ssp_probe
,
873 .remove
= pxa_ssp_remove
,
874 .suspend
= pxa_ssp_suspend
,
875 .resume
= pxa_ssp_resume
,
879 .rates
= PXA_SSP_RATES
,
880 .formats
= PXA_SSP_FORMATS
,
885 .rates
= PXA_SSP_RATES
,
886 .formats
= PXA_SSP_FORMATS
,
888 .ops
= &pxa_ssp_dai_ops
,
890 { .name
= "pxa2xx-ssp2",
892 .probe
= pxa_ssp_probe
,
893 .remove
= pxa_ssp_remove
,
894 .suspend
= pxa_ssp_suspend
,
895 .resume
= pxa_ssp_resume
,
899 .rates
= PXA_SSP_RATES
,
900 .formats
= PXA_SSP_FORMATS
,
905 .rates
= PXA_SSP_RATES
,
906 .formats
= PXA_SSP_FORMATS
,
908 .ops
= &pxa_ssp_dai_ops
,
911 .name
= "pxa2xx-ssp3",
913 .probe
= pxa_ssp_probe
,
914 .remove
= pxa_ssp_remove
,
915 .suspend
= pxa_ssp_suspend
,
916 .resume
= pxa_ssp_resume
,
920 .rates
= PXA_SSP_RATES
,
921 .formats
= PXA_SSP_FORMATS
,
926 .rates
= PXA_SSP_RATES
,
927 .formats
= PXA_SSP_FORMATS
,
929 .ops
= &pxa_ssp_dai_ops
,
932 .name
= "pxa2xx-ssp4",
934 .probe
= pxa_ssp_probe
,
935 .remove
= pxa_ssp_remove
,
936 .suspend
= pxa_ssp_suspend
,
937 .resume
= pxa_ssp_resume
,
941 .rates
= PXA_SSP_RATES
,
942 .formats
= PXA_SSP_FORMATS
,
947 .rates
= PXA_SSP_RATES
,
948 .formats
= PXA_SSP_FORMATS
,
950 .ops
= &pxa_ssp_dai_ops
,
953 EXPORT_SYMBOL_GPL(pxa_ssp_dai
);
955 static int __init
pxa_ssp_init(void)
957 return snd_soc_register_dais(pxa_ssp_dai
, ARRAY_SIZE(pxa_ssp_dai
));
959 module_init(pxa_ssp_init
);
961 static void __exit
pxa_ssp_exit(void)
963 snd_soc_unregister_dais(pxa_ssp_dai
, ARRAY_SIZE(pxa_ssp_dai
));
965 module_exit(pxa_ssp_exit
);
967 /* Module information */
968 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
969 MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
970 MODULE_LICENSE("GPL");