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1 /* linux/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h
3 * Copyright 2007 Simtec Electronics <linux@simtec.co.uk>
4 * http://armlinux.simtec.co.uk/
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * S3C2412 IIS register definition
13 #ifndef __ASM_ARCH_REGS_S3C2412_IIS_H
14 #define __ASM_ARCH_REGS_S3C2412_IIS_H
16 #define S3C2412_IISCON (0x00)
17 #define S3C2412_IISMOD (0x04)
18 #define S3C2412_IISFIC (0x08)
19 #define S3C2412_IISPSR (0x0C)
20 #define S3C2412_IISTXD (0x10)
21 #define S3C2412_IISRXD (0x14)
23 #define S3C2412_IISCON_LRINDEX (1 << 11)
24 #define S3C2412_IISCON_TXFIFO_EMPTY (1 << 10)
25 #define S3C2412_IISCON_RXFIFO_EMPTY (1 << 9)
26 #define S3C2412_IISCON_TXFIFO_FULL (1 << 8)
27 #define S3C2412_IISCON_RXFIFO_FULL (1 << 7)
28 #define S3C2412_IISCON_TXDMA_PAUSE (1 << 6)
29 #define S3C2412_IISCON_RXDMA_PAUSE (1 << 5)
30 #define S3C2412_IISCON_TXCH_PAUSE (1 << 4)
31 #define S3C2412_IISCON_RXCH_PAUSE (1 << 3)
32 #define S3C2412_IISCON_TXDMA_ACTIVE (1 << 2)
33 #define S3C2412_IISCON_RXDMA_ACTIVE (1 << 1)
34 #define S3C2412_IISCON_IIS_ACTIVE (1 << 0)
36 #define S3C64XX_IISMOD_BLC_16BIT (0 << 13)
37 #define S3C64XX_IISMOD_BLC_8BIT (1 << 13)
38 #define S3C64XX_IISMOD_BLC_24BIT (2 << 13)
39 #define S3C64XX_IISMOD_BLC_MASK (3 << 13)
41 #define S3C64XX_IISMOD_IMS_PCLK (0 << 10)
42 #define S3C64XX_IISMOD_IMS_SYSMUX (1 << 10)
44 #define S3C2412_IISMOD_MASTER_INTERNAL (0 << 10)
45 #define S3C2412_IISMOD_MASTER_EXTERNAL (1 << 10)
46 #define S3C2412_IISMOD_SLAVE (2 << 10)
47 #define S3C2412_IISMOD_MASTER_MASK (3 << 10)
48 #define S3C2412_IISMOD_MODE_TXONLY (0 << 8)
49 #define S3C2412_IISMOD_MODE_RXONLY (1 << 8)
50 #define S3C2412_IISMOD_MODE_TXRX (2 << 8)
51 #define S3C2412_IISMOD_MODE_MASK (3 << 8)
52 #define S3C2412_IISMOD_LR_LLOW (0 << 7)
53 #define S3C2412_IISMOD_LR_RLOW (1 << 7)
54 #define S3C2412_IISMOD_SDF_IIS (0 << 5)
55 #define S3C2412_IISMOD_SDF_MSB (1 << 5)
56 #define S3C2412_IISMOD_SDF_LSB (2 << 5)
57 #define S3C2412_IISMOD_SDF_MASK (3 << 5)
58 #define S3C2412_IISMOD_RCLK_256FS (0 << 3)
59 #define S3C2412_IISMOD_RCLK_512FS (1 << 3)
60 #define S3C2412_IISMOD_RCLK_384FS (2 << 3)
61 #define S3C2412_IISMOD_RCLK_768FS (3 << 3)
62 #define S3C2412_IISMOD_RCLK_MASK (3 << 3)
63 #define S3C2412_IISMOD_BCLK_32FS (0 << 1)
64 #define S3C2412_IISMOD_BCLK_48FS (1 << 1)
65 #define S3C2412_IISMOD_BCLK_16FS (2 << 1)
66 #define S3C2412_IISMOD_BCLK_24FS (3 << 1)
67 #define S3C2412_IISMOD_BCLK_MASK (3 << 1)
68 #define S3C2412_IISMOD_8BIT (1 << 0)
70 #define S3C64XX_IISMOD_CDCLKCON (1 << 12)
72 #define S3C2412_IISPSR_PSREN (1 << 15)
74 #define S3C2412_IISFIC_TXFLUSH (1 << 15)
75 #define S3C2412_IISFIC_RXFLUSH (1 << 7)
76 #define S3C2412_IISFIC_TXCOUNT(x) (((x) >> 8) & 0xf)
77 #define S3C2412_IISFIC_RXCOUNT(x) (((x) >> 0) & 0xf)
81 #endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */