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Merge branch 'docs-next' of git://git.lwn.net/linux-2.6
[mirror_ubuntu-hirsute-kernel.git] / sound / soc / sh / fsi.c
1 /*
2 * Fifo-attached Serial Interface (FSI) support for SH7724
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ssi.c
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/delay.h>
19 #include <linux/list.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/io.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/initval.h>
26 #include <sound/soc.h>
27 #include <sound/pcm_params.h>
28 #include <sound/sh_fsi.h>
29 #include <asm/atomic.h>
30
31 #define DO_FMT 0x0000
32 #define DOFF_CTL 0x0004
33 #define DOFF_ST 0x0008
34 #define DI_FMT 0x000C
35 #define DIFF_CTL 0x0010
36 #define DIFF_ST 0x0014
37 #define CKG1 0x0018
38 #define CKG2 0x001C
39 #define DIDT 0x0020
40 #define DODT 0x0024
41 #define MUTE_ST 0x0028
42 #define REG_END MUTE_ST
43
44
45 #define CPU_INT_ST 0x01F4
46 #define CPU_IEMSK 0x01F8
47 #define CPU_IMSK 0x01FC
48 #define INT_ST 0x0200
49 #define IEMSK 0x0204
50 #define IMSK 0x0208
51 #define MUTE 0x020C
52 #define CLK_RST 0x0210
53 #define SOFT_RST 0x0214
54 #define FIFO_SZ 0x0218
55 #define MREG_START CPU_INT_ST
56 #define MREG_END FIFO_SZ
57
58 /* DO_FMT */
59 /* DI_FMT */
60 #define CR_FMT(param) ((param) << 4)
61 # define CR_MONO 0x0
62 # define CR_MONO_D 0x1
63 # define CR_PCM 0x2
64 # define CR_I2S 0x3
65 # define CR_TDM 0x4
66 # define CR_TDM_D 0x5
67
68 /* DOFF_CTL */
69 /* DIFF_CTL */
70 #define IRQ_HALF 0x00100000
71 #define FIFO_CLR 0x00000001
72
73 /* DOFF_ST */
74 #define ERR_OVER 0x00000010
75 #define ERR_UNDER 0x00000001
76 #define ST_ERR (ERR_OVER | ERR_UNDER)
77
78 /* CLK_RST */
79 #define B_CLK 0x00000010
80 #define A_CLK 0x00000001
81
82 /* INT_ST */
83 #define INT_B_IN (1 << 12)
84 #define INT_B_OUT (1 << 8)
85 #define INT_A_IN (1 << 4)
86 #define INT_A_OUT (1 << 0)
87
88 /* SOFT_RST */
89 #define PBSR (1 << 12) /* Port B Software Reset */
90 #define PASR (1 << 8) /* Port A Software Reset */
91 #define IR (1 << 4) /* Interrupt Reset */
92 #define FSISR (1 << 0) /* Software Reset */
93
94 /* FIFO_SZ */
95 #define OUT_SZ_MASK 0x7
96 #define BO_SZ_SHIFT 8
97 #define AO_SZ_SHIFT 0
98
99 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
100
101 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
102
103 /************************************************************************
104
105
106 struct
107
108
109 ************************************************************************/
110 struct fsi_priv {
111 void __iomem *base;
112 struct snd_pcm_substream *substream;
113 struct fsi_master *master;
114
115 int fifo_max;
116 int chan;
117
118 int byte_offset;
119 int period_len;
120 int buffer_len;
121 int periods;
122 };
123
124 struct fsi_regs {
125 u32 int_st;
126 u32 iemsk;
127 u32 imsk;
128 };
129
130 struct fsi_master {
131 void __iomem *base;
132 int irq;
133 struct fsi_priv fsia;
134 struct fsi_priv fsib;
135 struct fsi_regs *regs;
136 struct sh_fsi_platform_info *info;
137 spinlock_t lock;
138 };
139
140 /************************************************************************
141
142
143 basic read write function
144
145
146 ************************************************************************/
147 static void __fsi_reg_write(u32 reg, u32 data)
148 {
149 /* valid data area is 24bit */
150 data &= 0x00ffffff;
151
152 __raw_writel(data, reg);
153 }
154
155 static u32 __fsi_reg_read(u32 reg)
156 {
157 return __raw_readl(reg);
158 }
159
160 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
161 {
162 u32 val = __fsi_reg_read(reg);
163
164 val &= ~mask;
165 val |= data & mask;
166
167 __fsi_reg_write(reg, val);
168 }
169
170 static void fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data)
171 {
172 if (reg > REG_END)
173 return;
174
175 __fsi_reg_write((u32)(fsi->base + reg), data);
176 }
177
178 static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg)
179 {
180 if (reg > REG_END)
181 return 0;
182
183 return __fsi_reg_read((u32)(fsi->base + reg));
184 }
185
186 static void fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data)
187 {
188 if (reg > REG_END)
189 return;
190
191 __fsi_reg_mask_set((u32)(fsi->base + reg), mask, data);
192 }
193
194 static void fsi_master_write(struct fsi_master *master, u32 reg, u32 data)
195 {
196 unsigned long flags;
197
198 if ((reg < MREG_START) ||
199 (reg > MREG_END))
200 return;
201
202 spin_lock_irqsave(&master->lock, flags);
203 __fsi_reg_write((u32)(master->base + reg), data);
204 spin_unlock_irqrestore(&master->lock, flags);
205 }
206
207 static u32 fsi_master_read(struct fsi_master *master, u32 reg)
208 {
209 u32 ret;
210 unsigned long flags;
211
212 if ((reg < MREG_START) ||
213 (reg > MREG_END))
214 return 0;
215
216 spin_lock_irqsave(&master->lock, flags);
217 ret = __fsi_reg_read((u32)(master->base + reg));
218 spin_unlock_irqrestore(&master->lock, flags);
219
220 return ret;
221 }
222
223 static void fsi_master_mask_set(struct fsi_master *master,
224 u32 reg, u32 mask, u32 data)
225 {
226 unsigned long flags;
227
228 if ((reg < MREG_START) ||
229 (reg > MREG_END))
230 return;
231
232 spin_lock_irqsave(&master->lock, flags);
233 __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
234 spin_unlock_irqrestore(&master->lock, flags);
235 }
236
237 /************************************************************************
238
239
240 basic function
241
242
243 ************************************************************************/
244 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
245 {
246 return fsi->master;
247 }
248
249 static int fsi_is_port_a(struct fsi_priv *fsi)
250 {
251 return fsi->master->base == fsi->base;
252 }
253
254 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
255 {
256 struct snd_soc_pcm_runtime *rtd = substream->private_data;
257 struct snd_soc_dai_link *machine = rtd->dai;
258
259 return machine->cpu_dai;
260 }
261
262 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
263 {
264 struct snd_soc_dai *dai = fsi_get_dai(substream);
265
266 return dai->private_data;
267 }
268
269 static u32 fsi_get_info_flags(struct fsi_priv *fsi)
270 {
271 int is_porta = fsi_is_port_a(fsi);
272 struct fsi_master *master = fsi_get_master(fsi);
273
274 return is_porta ? master->info->porta_flags :
275 master->info->portb_flags;
276 }
277
278 static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play)
279 {
280 u32 mode;
281 u32 flags = fsi_get_info_flags(fsi);
282
283 mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE;
284
285 /* return
286 * 1 : master mode
287 * 0 : slave mode
288 */
289
290 return (mode & flags) != mode;
291 }
292
293 static u32 fsi_port_ab_io_bit(struct fsi_priv *fsi, int is_play)
294 {
295 int is_porta = fsi_is_port_a(fsi);
296 u32 data;
297
298 if (is_porta)
299 data = is_play ? (1 << 0) : (1 << 4);
300 else
301 data = is_play ? (1 << 8) : (1 << 12);
302
303 return data;
304 }
305
306 static void fsi_stream_push(struct fsi_priv *fsi,
307 struct snd_pcm_substream *substream,
308 u32 buffer_len,
309 u32 period_len)
310 {
311 fsi->substream = substream;
312 fsi->buffer_len = buffer_len;
313 fsi->period_len = period_len;
314 fsi->byte_offset = 0;
315 fsi->periods = 0;
316 }
317
318 static void fsi_stream_pop(struct fsi_priv *fsi)
319 {
320 fsi->substream = NULL;
321 fsi->buffer_len = 0;
322 fsi->period_len = 0;
323 fsi->byte_offset = 0;
324 fsi->periods = 0;
325 }
326
327 static int fsi_get_fifo_residue(struct fsi_priv *fsi, int is_play)
328 {
329 u32 status;
330 u32 reg = is_play ? DOFF_ST : DIFF_ST;
331 int residue;
332
333 status = fsi_reg_read(fsi, reg);
334 residue = 0x1ff & (status >> 8);
335 residue *= fsi->chan;
336
337 return residue;
338 }
339
340 /************************************************************************
341
342
343 irq function
344
345
346 ************************************************************************/
347 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
348 {
349 u32 data = fsi_port_ab_io_bit(fsi, is_play);
350 struct fsi_master *master = fsi_get_master(fsi);
351
352 fsi_master_mask_set(master, master->regs->imsk, data, data);
353 fsi_master_mask_set(master, master->regs->iemsk, data, data);
354 }
355
356 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
357 {
358 u32 data = fsi_port_ab_io_bit(fsi, is_play);
359 struct fsi_master *master = fsi_get_master(fsi);
360
361 fsi_master_mask_set(master, master->regs->imsk, data, 0);
362 fsi_master_mask_set(master, master->regs->iemsk, data, 0);
363 }
364
365 static u32 fsi_irq_get_status(struct fsi_master *master)
366 {
367 return fsi_master_read(master, master->regs->int_st);
368 }
369
370 static void fsi_irq_clear_all_status(struct fsi_master *master)
371 {
372 fsi_master_write(master, master->regs->int_st, 0x0000000);
373 }
374
375 static void fsi_irq_clear_status(struct fsi_priv *fsi)
376 {
377 u32 data = 0;
378 struct fsi_master *master = fsi_get_master(fsi);
379
380 data |= fsi_port_ab_io_bit(fsi, 0);
381 data |= fsi_port_ab_io_bit(fsi, 1);
382
383 /* clear interrupt factor */
384 fsi_master_mask_set(master, master->regs->int_st, data, 0);
385 }
386
387 /************************************************************************
388
389
390 ctrl function
391
392
393 ************************************************************************/
394 static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable)
395 {
396 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4);
397 struct fsi_master *master = fsi_get_master(fsi);
398
399 if (enable)
400 fsi_master_mask_set(master, CLK_RST, val, val);
401 else
402 fsi_master_mask_set(master, CLK_RST, val, 0);
403 }
404
405 static void fsi_fifo_init(struct fsi_priv *fsi,
406 int is_play,
407 struct snd_soc_dai *dai)
408 {
409 struct fsi_master *master = fsi_get_master(fsi);
410 u32 ctrl, shift, i;
411
412 /* get on-chip RAM capacity */
413 shift = fsi_master_read(master, FIFO_SZ);
414 shift >>= fsi_is_port_a(fsi) ? AO_SZ_SHIFT : BO_SZ_SHIFT;
415 shift &= OUT_SZ_MASK;
416 fsi->fifo_max = 256 << shift;
417 dev_dbg(dai->dev, "fifo = %d words\n", fsi->fifo_max);
418
419 /*
420 * The maximum number of sample data varies depending
421 * on the number of channels selected for the format.
422 *
423 * FIFOs are used in 4-channel units in 3-channel mode
424 * and in 8-channel units in 5- to 7-channel mode
425 * meaning that more FIFOs than the required size of DPRAM
426 * are used.
427 *
428 * ex) if 256 words of DP-RAM is connected
429 * 1 channel: 256 (256 x 1 = 256)
430 * 2 channels: 128 (128 x 2 = 256)
431 * 3 channels: 64 ( 64 x 3 = 192)
432 * 4 channels: 64 ( 64 x 4 = 256)
433 * 5 channels: 32 ( 32 x 5 = 160)
434 * 6 channels: 32 ( 32 x 6 = 192)
435 * 7 channels: 32 ( 32 x 7 = 224)
436 * 8 channels: 32 ( 32 x 8 = 256)
437 */
438 for (i = 1; i < fsi->chan; i <<= 1)
439 fsi->fifo_max >>= 1;
440 dev_dbg(dai->dev, "%d channel %d store\n", fsi->chan, fsi->fifo_max);
441
442 ctrl = is_play ? DOFF_CTL : DIFF_CTL;
443
444 /* set interrupt generation factor */
445 fsi_reg_write(fsi, ctrl, IRQ_HALF);
446
447 /* clear FIFO */
448 fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR);
449 }
450
451 static void fsi_soft_all_reset(struct fsi_master *master)
452 {
453 /* port AB reset */
454 fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0);
455 mdelay(10);
456
457 /* soft reset */
458 fsi_master_mask_set(master, SOFT_RST, FSISR, 0);
459 fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR);
460 mdelay(10);
461 }
462
463 /* playback interrupt */
464 static int fsi_data_push(struct fsi_priv *fsi, int startup)
465 {
466 struct snd_pcm_runtime *runtime;
467 struct snd_pcm_substream *substream = NULL;
468 u32 status;
469 int send;
470 int fifo_free;
471 int width;
472 u8 *start;
473 int i, over_period;
474
475 if (!fsi ||
476 !fsi->substream ||
477 !fsi->substream->runtime)
478 return -EINVAL;
479
480 over_period = 0;
481 substream = fsi->substream;
482 runtime = substream->runtime;
483
484 /* FSI FIFO has limit.
485 * So, this driver can not send periods data at a time
486 */
487 if (fsi->byte_offset >=
488 fsi->period_len * (fsi->periods + 1)) {
489
490 over_period = 1;
491 fsi->periods = (fsi->periods + 1) % runtime->periods;
492
493 if (0 == fsi->periods)
494 fsi->byte_offset = 0;
495 }
496
497 /* get 1 channel data width */
498 width = frames_to_bytes(runtime, 1) / fsi->chan;
499
500 /* get send size for alsa */
501 send = (fsi->buffer_len - fsi->byte_offset) / width;
502
503 /* get FIFO free size */
504 fifo_free = (fsi->fifo_max * fsi->chan) - fsi_get_fifo_residue(fsi, 1);
505
506 /* size check */
507 if (fifo_free < send)
508 send = fifo_free;
509
510 start = runtime->dma_area;
511 start += fsi->byte_offset;
512
513 switch (width) {
514 case 2:
515 for (i = 0; i < send; i++)
516 fsi_reg_write(fsi, DODT,
517 ((u32)*((u16 *)start + i) << 8));
518 break;
519 case 4:
520 for (i = 0; i < send; i++)
521 fsi_reg_write(fsi, DODT, *((u32 *)start + i));
522 break;
523 default:
524 return -EINVAL;
525 }
526
527 fsi->byte_offset += send * width;
528
529 status = fsi_reg_read(fsi, DOFF_ST);
530 if (!startup) {
531 struct snd_soc_dai *dai = fsi_get_dai(substream);
532
533 if (status & ERR_OVER)
534 dev_err(dai->dev, "over run\n");
535 if (status & ERR_UNDER)
536 dev_err(dai->dev, "under run\n");
537 }
538 fsi_reg_write(fsi, DOFF_ST, 0);
539
540 fsi_irq_enable(fsi, 1);
541
542 if (over_period)
543 snd_pcm_period_elapsed(substream);
544
545 return 0;
546 }
547
548 static int fsi_data_pop(struct fsi_priv *fsi, int startup)
549 {
550 struct snd_pcm_runtime *runtime;
551 struct snd_pcm_substream *substream = NULL;
552 u32 status;
553 int free;
554 int fifo_fill;
555 int width;
556 u8 *start;
557 int i, over_period;
558
559 if (!fsi ||
560 !fsi->substream ||
561 !fsi->substream->runtime)
562 return -EINVAL;
563
564 over_period = 0;
565 substream = fsi->substream;
566 runtime = substream->runtime;
567
568 /* FSI FIFO has limit.
569 * So, this driver can not send periods data at a time
570 */
571 if (fsi->byte_offset >=
572 fsi->period_len * (fsi->periods + 1)) {
573
574 over_period = 1;
575 fsi->periods = (fsi->periods + 1) % runtime->periods;
576
577 if (0 == fsi->periods)
578 fsi->byte_offset = 0;
579 }
580
581 /* get 1 channel data width */
582 width = frames_to_bytes(runtime, 1) / fsi->chan;
583
584 /* get free space for alsa */
585 free = (fsi->buffer_len - fsi->byte_offset) / width;
586
587 /* get recv size */
588 fifo_fill = fsi_get_fifo_residue(fsi, 0);
589
590 if (free < fifo_fill)
591 fifo_fill = free;
592
593 start = runtime->dma_area;
594 start += fsi->byte_offset;
595
596 switch (width) {
597 case 2:
598 for (i = 0; i < fifo_fill; i++)
599 *((u16 *)start + i) =
600 (u16)(fsi_reg_read(fsi, DIDT) >> 8);
601 break;
602 case 4:
603 for (i = 0; i < fifo_fill; i++)
604 *((u32 *)start + i) = fsi_reg_read(fsi, DIDT);
605 break;
606 default:
607 return -EINVAL;
608 }
609
610 fsi->byte_offset += fifo_fill * width;
611
612 status = fsi_reg_read(fsi, DIFF_ST);
613 if (!startup) {
614 struct snd_soc_dai *dai = fsi_get_dai(substream);
615
616 if (status & ERR_OVER)
617 dev_err(dai->dev, "over run\n");
618 if (status & ERR_UNDER)
619 dev_err(dai->dev, "under run\n");
620 }
621 fsi_reg_write(fsi, DIFF_ST, 0);
622
623 fsi_irq_enable(fsi, 0);
624
625 if (over_period)
626 snd_pcm_period_elapsed(substream);
627
628 return 0;
629 }
630
631 static irqreturn_t fsi_interrupt(int irq, void *data)
632 {
633 struct fsi_master *master = data;
634 u32 int_st = fsi_irq_get_status(master);
635
636 /* clear irq status */
637 fsi_master_mask_set(master, SOFT_RST, IR, 0);
638 fsi_master_mask_set(master, SOFT_RST, IR, IR);
639
640 if (int_st & INT_A_OUT)
641 fsi_data_push(&master->fsia, 0);
642 if (int_st & INT_B_OUT)
643 fsi_data_push(&master->fsib, 0);
644 if (int_st & INT_A_IN)
645 fsi_data_pop(&master->fsia, 0);
646 if (int_st & INT_B_IN)
647 fsi_data_pop(&master->fsib, 0);
648
649 fsi_irq_clear_all_status(master);
650
651 return IRQ_HANDLED;
652 }
653
654 /************************************************************************
655
656
657 dai ops
658
659
660 ************************************************************************/
661 static int fsi_dai_startup(struct snd_pcm_substream *substream,
662 struct snd_soc_dai *dai)
663 {
664 struct fsi_priv *fsi = fsi_get_priv(substream);
665 const char *msg;
666 u32 flags = fsi_get_info_flags(fsi);
667 u32 fmt;
668 u32 reg;
669 u32 data;
670 int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
671 int is_master;
672 int ret = 0;
673
674 pm_runtime_get_sync(dai->dev);
675
676 /* CKG1 */
677 data = is_play ? (1 << 0) : (1 << 4);
678 is_master = fsi_is_master_mode(fsi, is_play);
679 if (is_master)
680 fsi_reg_mask_set(fsi, CKG1, data, data);
681 else
682 fsi_reg_mask_set(fsi, CKG1, data, 0);
683
684 /* clock inversion (CKG2) */
685 data = 0;
686 switch (SH_FSI_INVERSION_MASK & flags) {
687 case SH_FSI_LRM_INV:
688 data = 1 << 12;
689 break;
690 case SH_FSI_BRM_INV:
691 data = 1 << 8;
692 break;
693 case SH_FSI_LRS_INV:
694 data = 1 << 4;
695 break;
696 case SH_FSI_BRS_INV:
697 data = 1 << 0;
698 break;
699 }
700 fsi_reg_write(fsi, CKG2, data);
701
702 /* do fmt, di fmt */
703 data = 0;
704 reg = is_play ? DO_FMT : DI_FMT;
705 fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags);
706 switch (fmt) {
707 case SH_FSI_FMT_MONO:
708 msg = "MONO";
709 data = CR_FMT(CR_MONO);
710 fsi->chan = 1;
711 break;
712 case SH_FSI_FMT_MONO_DELAY:
713 msg = "MONO Delay";
714 data = CR_FMT(CR_MONO_D);
715 fsi->chan = 1;
716 break;
717 case SH_FSI_FMT_PCM:
718 msg = "PCM";
719 data = CR_FMT(CR_PCM);
720 fsi->chan = 2;
721 break;
722 case SH_FSI_FMT_I2S:
723 msg = "I2S";
724 data = CR_FMT(CR_I2S);
725 fsi->chan = 2;
726 break;
727 case SH_FSI_FMT_TDM:
728 msg = "TDM";
729 data = CR_FMT(CR_TDM) | (fsi->chan - 1);
730 fsi->chan = is_play ?
731 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
732 break;
733 case SH_FSI_FMT_TDM_DELAY:
734 msg = "TDM Delay";
735 data = CR_FMT(CR_TDM_D) | (fsi->chan - 1);
736 fsi->chan = is_play ?
737 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
738 break;
739 default:
740 dev_err(dai->dev, "unknown format.\n");
741 return -EINVAL;
742 }
743 fsi_reg_write(fsi, reg, data);
744
745 /*
746 * clear clk reset if master mode
747 */
748 if (is_master)
749 fsi_clk_ctrl(fsi, 1);
750
751 /* irq clear */
752 fsi_irq_disable(fsi, is_play);
753 fsi_irq_clear_status(fsi);
754
755 /* fifo init */
756 fsi_fifo_init(fsi, is_play, dai);
757
758 return ret;
759 }
760
761 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
762 struct snd_soc_dai *dai)
763 {
764 struct fsi_priv *fsi = fsi_get_priv(substream);
765 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
766
767 fsi_irq_disable(fsi, is_play);
768 fsi_clk_ctrl(fsi, 0);
769
770 pm_runtime_put_sync(dai->dev);
771 }
772
773 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
774 struct snd_soc_dai *dai)
775 {
776 struct fsi_priv *fsi = fsi_get_priv(substream);
777 struct snd_pcm_runtime *runtime = substream->runtime;
778 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
779 int ret = 0;
780
781 switch (cmd) {
782 case SNDRV_PCM_TRIGGER_START:
783 fsi_stream_push(fsi, substream,
784 frames_to_bytes(runtime, runtime->buffer_size),
785 frames_to_bytes(runtime, runtime->period_size));
786 ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1);
787 break;
788 case SNDRV_PCM_TRIGGER_STOP:
789 fsi_irq_disable(fsi, is_play);
790 fsi_stream_pop(fsi);
791 break;
792 }
793
794 return ret;
795 }
796
797 static struct snd_soc_dai_ops fsi_dai_ops = {
798 .startup = fsi_dai_startup,
799 .shutdown = fsi_dai_shutdown,
800 .trigger = fsi_dai_trigger,
801 };
802
803 /************************************************************************
804
805
806 pcm ops
807
808
809 ************************************************************************/
810 static struct snd_pcm_hardware fsi_pcm_hardware = {
811 .info = SNDRV_PCM_INFO_INTERLEAVED |
812 SNDRV_PCM_INFO_MMAP |
813 SNDRV_PCM_INFO_MMAP_VALID |
814 SNDRV_PCM_INFO_PAUSE,
815 .formats = FSI_FMTS,
816 .rates = FSI_RATES,
817 .rate_min = 8000,
818 .rate_max = 192000,
819 .channels_min = 1,
820 .channels_max = 2,
821 .buffer_bytes_max = 64 * 1024,
822 .period_bytes_min = 32,
823 .period_bytes_max = 8192,
824 .periods_min = 1,
825 .periods_max = 32,
826 .fifo_size = 256,
827 };
828
829 static int fsi_pcm_open(struct snd_pcm_substream *substream)
830 {
831 struct snd_pcm_runtime *runtime = substream->runtime;
832 int ret = 0;
833
834 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
835
836 ret = snd_pcm_hw_constraint_integer(runtime,
837 SNDRV_PCM_HW_PARAM_PERIODS);
838
839 return ret;
840 }
841
842 static int fsi_hw_params(struct snd_pcm_substream *substream,
843 struct snd_pcm_hw_params *hw_params)
844 {
845 return snd_pcm_lib_malloc_pages(substream,
846 params_buffer_bytes(hw_params));
847 }
848
849 static int fsi_hw_free(struct snd_pcm_substream *substream)
850 {
851 return snd_pcm_lib_free_pages(substream);
852 }
853
854 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
855 {
856 struct snd_pcm_runtime *runtime = substream->runtime;
857 struct fsi_priv *fsi = fsi_get_priv(substream);
858 long location;
859
860 location = (fsi->byte_offset - 1);
861 if (location < 0)
862 location = 0;
863
864 return bytes_to_frames(runtime, location);
865 }
866
867 static struct snd_pcm_ops fsi_pcm_ops = {
868 .open = fsi_pcm_open,
869 .ioctl = snd_pcm_lib_ioctl,
870 .hw_params = fsi_hw_params,
871 .hw_free = fsi_hw_free,
872 .pointer = fsi_pointer,
873 };
874
875 /************************************************************************
876
877
878 snd_soc_platform
879
880
881 ************************************************************************/
882 #define PREALLOC_BUFFER (32 * 1024)
883 #define PREALLOC_BUFFER_MAX (32 * 1024)
884
885 static void fsi_pcm_free(struct snd_pcm *pcm)
886 {
887 snd_pcm_lib_preallocate_free_for_all(pcm);
888 }
889
890 static int fsi_pcm_new(struct snd_card *card,
891 struct snd_soc_dai *dai,
892 struct snd_pcm *pcm)
893 {
894 /*
895 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
896 * in MMAP mode (i.e. aplay -M)
897 */
898 return snd_pcm_lib_preallocate_pages_for_all(
899 pcm,
900 SNDRV_DMA_TYPE_CONTINUOUS,
901 snd_dma_continuous_data(GFP_KERNEL),
902 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
903 }
904
905 /************************************************************************
906
907
908 alsa struct
909
910
911 ************************************************************************/
912 struct snd_soc_dai fsi_soc_dai[] = {
913 {
914 .name = "FSIA",
915 .id = 0,
916 .playback = {
917 .rates = FSI_RATES,
918 .formats = FSI_FMTS,
919 .channels_min = 1,
920 .channels_max = 8,
921 },
922 .capture = {
923 .rates = FSI_RATES,
924 .formats = FSI_FMTS,
925 .channels_min = 1,
926 .channels_max = 8,
927 },
928 .ops = &fsi_dai_ops,
929 },
930 {
931 .name = "FSIB",
932 .id = 1,
933 .playback = {
934 .rates = FSI_RATES,
935 .formats = FSI_FMTS,
936 .channels_min = 1,
937 .channels_max = 8,
938 },
939 .capture = {
940 .rates = FSI_RATES,
941 .formats = FSI_FMTS,
942 .channels_min = 1,
943 .channels_max = 8,
944 },
945 .ops = &fsi_dai_ops,
946 },
947 };
948 EXPORT_SYMBOL_GPL(fsi_soc_dai);
949
950 struct snd_soc_platform fsi_soc_platform = {
951 .name = "fsi-pcm",
952 .pcm_ops = &fsi_pcm_ops,
953 .pcm_new = fsi_pcm_new,
954 .pcm_free = fsi_pcm_free,
955 };
956 EXPORT_SYMBOL_GPL(fsi_soc_platform);
957
958 /************************************************************************
959
960
961 platform function
962
963
964 ************************************************************************/
965 static int fsi_probe(struct platform_device *pdev)
966 {
967 struct fsi_master *master;
968 const struct platform_device_id *id_entry;
969 struct resource *res;
970 unsigned int irq;
971 int ret;
972
973 if (0 != pdev->id) {
974 dev_err(&pdev->dev, "current fsi support id 0 only now\n");
975 return -ENODEV;
976 }
977
978 id_entry = pdev->id_entry;
979 if (!id_entry) {
980 dev_err(&pdev->dev, "unknown fsi device\n");
981 return -ENODEV;
982 }
983
984 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
985 irq = platform_get_irq(pdev, 0);
986 if (!res || (int)irq <= 0) {
987 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
988 ret = -ENODEV;
989 goto exit;
990 }
991
992 master = kzalloc(sizeof(*master), GFP_KERNEL);
993 if (!master) {
994 dev_err(&pdev->dev, "Could not allocate master\n");
995 ret = -ENOMEM;
996 goto exit;
997 }
998
999 master->base = ioremap_nocache(res->start, resource_size(res));
1000 if (!master->base) {
1001 ret = -ENXIO;
1002 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1003 goto exit_kfree;
1004 }
1005
1006 master->irq = irq;
1007 master->info = pdev->dev.platform_data;
1008 master->fsia.base = master->base;
1009 master->fsia.master = master;
1010 master->fsib.base = master->base + 0x40;
1011 master->fsib.master = master;
1012 master->regs = (struct fsi_regs *)id_entry->driver_data;
1013 spin_lock_init(&master->lock);
1014
1015 pm_runtime_enable(&pdev->dev);
1016 pm_runtime_resume(&pdev->dev);
1017
1018 fsi_soc_dai[0].dev = &pdev->dev;
1019 fsi_soc_dai[0].private_data = &master->fsia;
1020 fsi_soc_dai[1].dev = &pdev->dev;
1021 fsi_soc_dai[1].private_data = &master->fsib;
1022
1023 fsi_soft_all_reset(master);
1024
1025 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED,
1026 id_entry->name, master);
1027 if (ret) {
1028 dev_err(&pdev->dev, "irq request err\n");
1029 goto exit_iounmap;
1030 }
1031
1032 ret = snd_soc_register_platform(&fsi_soc_platform);
1033 if (ret < 0) {
1034 dev_err(&pdev->dev, "cannot snd soc register\n");
1035 goto exit_free_irq;
1036 }
1037
1038 return snd_soc_register_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
1039
1040 exit_free_irq:
1041 free_irq(irq, master);
1042 exit_iounmap:
1043 iounmap(master->base);
1044 pm_runtime_disable(&pdev->dev);
1045 exit_kfree:
1046 kfree(master);
1047 master = NULL;
1048 exit:
1049 return ret;
1050 }
1051
1052 static int fsi_remove(struct platform_device *pdev)
1053 {
1054 struct fsi_master *master;
1055
1056 master = fsi_get_master(fsi_soc_dai[0].private_data);
1057
1058 snd_soc_unregister_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
1059 snd_soc_unregister_platform(&fsi_soc_platform);
1060
1061 pm_runtime_disable(&pdev->dev);
1062
1063 free_irq(master->irq, master);
1064
1065 iounmap(master->base);
1066 kfree(master);
1067
1068 fsi_soc_dai[0].dev = NULL;
1069 fsi_soc_dai[0].private_data = NULL;
1070 fsi_soc_dai[1].dev = NULL;
1071 fsi_soc_dai[1].private_data = NULL;
1072
1073 return 0;
1074 }
1075
1076 static int fsi_runtime_nop(struct device *dev)
1077 {
1078 /* Runtime PM callback shared between ->runtime_suspend()
1079 * and ->runtime_resume(). Simply returns success.
1080 *
1081 * This driver re-initializes all registers after
1082 * pm_runtime_get_sync() anyway so there is no need
1083 * to save and restore registers here.
1084 */
1085 return 0;
1086 }
1087
1088 static struct dev_pm_ops fsi_pm_ops = {
1089 .runtime_suspend = fsi_runtime_nop,
1090 .runtime_resume = fsi_runtime_nop,
1091 };
1092
1093 static struct fsi_regs fsi_regs = {
1094 .int_st = INT_ST,
1095 .iemsk = IEMSK,
1096 .imsk = IMSK,
1097 };
1098
1099 static struct fsi_regs fsi2_regs = {
1100 .int_st = CPU_INT_ST,
1101 .iemsk = CPU_IEMSK,
1102 .imsk = CPU_IMSK,
1103 };
1104
1105 static struct platform_device_id fsi_id_table[] = {
1106 { "sh_fsi", (kernel_ulong_t)&fsi_regs },
1107 { "sh_fsi2", (kernel_ulong_t)&fsi2_regs },
1108 };
1109
1110 static struct platform_driver fsi_driver = {
1111 .driver = {
1112 .name = "sh_fsi",
1113 .pm = &fsi_pm_ops,
1114 },
1115 .probe = fsi_probe,
1116 .remove = fsi_remove,
1117 .id_table = fsi_id_table,
1118 };
1119
1120 static int __init fsi_mobile_init(void)
1121 {
1122 return platform_driver_register(&fsi_driver);
1123 }
1124
1125 static void __exit fsi_mobile_exit(void)
1126 {
1127 platform_driver_unregister(&fsi_driver);
1128 }
1129 module_init(fsi_mobile_init);
1130 module_exit(fsi_mobile_exit);
1131
1132 MODULE_LICENSE("GPL");
1133 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1134 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
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