]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blob - sound/soc/sh/fsi.c
projects / mirror_ubuntu-hirsute-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Add a document describing the padata interface
[mirror_ubuntu-hirsute-kernel.git] / sound / soc / sh / fsi.c
1 /*
2 * Fifo-attached Serial Interface (FSI) support for SH7724
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ssi.c
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/delay.h>
19 #include <linux/list.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/io.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/initval.h>
26 #include <sound/soc.h>
27 #include <sound/pcm_params.h>
28 #include <sound/sh_fsi.h>
29 #include <asm/atomic.h>
30
31 #define DO_FMT 0x0000
32 #define DOFF_CTL 0x0004
33 #define DOFF_ST 0x0008
34 #define DI_FMT 0x000C
35 #define DIFF_CTL 0x0010
36 #define DIFF_ST 0x0014
37 #define CKG1 0x0018
38 #define CKG2 0x001C
39 #define DIDT 0x0020
40 #define DODT 0x0024
41 #define MUTE_ST 0x0028
42 #define REG_END MUTE_ST
43
44 #define INT_ST 0x0200
45 #define IEMSK 0x0204
46 #define IMSK 0x0208
47 #define MUTE 0x020C
48 #define CLK_RST 0x0210
49 #define SOFT_RST 0x0214
50 #define MREG_START INT_ST
51 #define MREG_END SOFT_RST
52
53 /* DO_FMT */
54 /* DI_FMT */
55 #define CR_FMT(param) ((param) << 4)
56 # define CR_MONO 0x0
57 # define CR_MONO_D 0x1
58 # define CR_PCM 0x2
59 # define CR_I2S 0x3
60 # define CR_TDM 0x4
61 # define CR_TDM_D 0x5
62
63 /* DOFF_CTL */
64 /* DIFF_CTL */
65 #define IRQ_HALF 0x00100000
66 #define FIFO_CLR 0x00000001
67
68 /* DOFF_ST */
69 #define ERR_OVER 0x00000010
70 #define ERR_UNDER 0x00000001
71 #define ST_ERR (ERR_OVER | ERR_UNDER)
72
73 /* CLK_RST */
74 #define B_CLK 0x00000010
75 #define A_CLK 0x00000001
76
77 /* INT_ST */
78 #define INT_B_IN (1 << 12)
79 #define INT_B_OUT (1 << 8)
80 #define INT_A_IN (1 << 4)
81 #define INT_A_OUT (1 << 0)
82
83 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
84
85 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
86
87 /************************************************************************
88
89
90 struct
91
92
93 ************************************************************************/
94 struct fsi_priv {
95 void __iomem *base;
96 struct snd_pcm_substream *substream;
97 struct fsi_master *master;
98
99 int fifo_max;
100 int chan;
101
102 int byte_offset;
103 int period_len;
104 int buffer_len;
105 int periods;
106 };
107
108 struct fsi_master {
109 void __iomem *base;
110 int irq;
111 struct fsi_priv fsia;
112 struct fsi_priv fsib;
113 struct sh_fsi_platform_info *info;
114 spinlock_t lock;
115 };
116
117 /************************************************************************
118
119
120 basic read write function
121
122
123 ************************************************************************/
124 static void __fsi_reg_write(u32 reg, u32 data)
125 {
126 /* valid data area is 24bit */
127 data &= 0x00ffffff;
128
129 __raw_writel(data, reg);
130 }
131
132 static u32 __fsi_reg_read(u32 reg)
133 {
134 return __raw_readl(reg);
135 }
136
137 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
138 {
139 u32 val = __fsi_reg_read(reg);
140
141 val &= ~mask;
142 val |= data & mask;
143
144 __fsi_reg_write(reg, val);
145 }
146
147 static void fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data)
148 {
149 if (reg > REG_END)
150 return;
151
152 __fsi_reg_write((u32)(fsi->base + reg), data);
153 }
154
155 static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg)
156 {
157 if (reg > REG_END)
158 return 0;
159
160 return __fsi_reg_read((u32)(fsi->base + reg));
161 }
162
163 static void fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data)
164 {
165 if (reg > REG_END)
166 return;
167
168 __fsi_reg_mask_set((u32)(fsi->base + reg), mask, data);
169 }
170
171 static void fsi_master_write(struct fsi_master *master, u32 reg, u32 data)
172 {
173 unsigned long flags;
174
175 if ((reg < MREG_START) ||
176 (reg > MREG_END))
177 return;
178
179 spin_lock_irqsave(&master->lock, flags);
180 __fsi_reg_write((u32)(master->base + reg), data);
181 spin_unlock_irqrestore(&master->lock, flags);
182 }
183
184 static u32 fsi_master_read(struct fsi_master *master, u32 reg)
185 {
186 u32 ret;
187 unsigned long flags;
188
189 if ((reg < MREG_START) ||
190 (reg > MREG_END))
191 return 0;
192
193 spin_lock_irqsave(&master->lock, flags);
194 ret = __fsi_reg_read((u32)(master->base + reg));
195 spin_unlock_irqrestore(&master->lock, flags);
196
197 return ret;
198 }
199
200 static void fsi_master_mask_set(struct fsi_master *master,
201 u32 reg, u32 mask, u32 data)
202 {
203 unsigned long flags;
204
205 if ((reg < MREG_START) ||
206 (reg > MREG_END))
207 return;
208
209 spin_lock_irqsave(&master->lock, flags);
210 __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
211 spin_unlock_irqrestore(&master->lock, flags);
212 }
213
214 /************************************************************************
215
216
217 basic function
218
219
220 ************************************************************************/
221 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
222 {
223 return fsi->master;
224 }
225
226 static int fsi_is_port_a(struct fsi_priv *fsi)
227 {
228 return fsi->master->base == fsi->base;
229 }
230
231 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
232 {
233 struct snd_soc_pcm_runtime *rtd = substream->private_data;
234 struct snd_soc_dai_link *machine = rtd->dai;
235
236 return machine->cpu_dai;
237 }
238
239 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
240 {
241 struct snd_soc_dai *dai = fsi_get_dai(substream);
242
243 return dai->private_data;
244 }
245
246 static u32 fsi_get_info_flags(struct fsi_priv *fsi)
247 {
248 int is_porta = fsi_is_port_a(fsi);
249 struct fsi_master *master = fsi_get_master(fsi);
250
251 return is_porta ? master->info->porta_flags :
252 master->info->portb_flags;
253 }
254
255 static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play)
256 {
257 u32 mode;
258 u32 flags = fsi_get_info_flags(fsi);
259
260 mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE;
261
262 /* return
263 * 1 : master mode
264 * 0 : slave mode
265 */
266
267 return (mode & flags) != mode;
268 }
269
270 static u32 fsi_port_ab_io_bit(struct fsi_priv *fsi, int is_play)
271 {
272 int is_porta = fsi_is_port_a(fsi);
273 u32 data;
274
275 if (is_porta)
276 data = is_play ? (1 << 0) : (1 << 4);
277 else
278 data = is_play ? (1 << 8) : (1 << 12);
279
280 return data;
281 }
282
283 static void fsi_stream_push(struct fsi_priv *fsi,
284 struct snd_pcm_substream *substream,
285 u32 buffer_len,
286 u32 period_len)
287 {
288 fsi->substream = substream;
289 fsi->buffer_len = buffer_len;
290 fsi->period_len = period_len;
291 fsi->byte_offset = 0;
292 fsi->periods = 0;
293 }
294
295 static void fsi_stream_pop(struct fsi_priv *fsi)
296 {
297 fsi->substream = NULL;
298 fsi->buffer_len = 0;
299 fsi->period_len = 0;
300 fsi->byte_offset = 0;
301 fsi->periods = 0;
302 }
303
304 static int fsi_get_fifo_residue(struct fsi_priv *fsi, int is_play)
305 {
306 u32 status;
307 u32 reg = is_play ? DOFF_ST : DIFF_ST;
308 int residue;
309
310 status = fsi_reg_read(fsi, reg);
311 residue = 0x1ff & (status >> 8);
312 residue *= fsi->chan;
313
314 return residue;
315 }
316
317 /************************************************************************
318
319
320 ctrl function
321
322
323 ************************************************************************/
324 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
325 {
326 u32 data = fsi_port_ab_io_bit(fsi, is_play);
327 struct fsi_master *master = fsi_get_master(fsi);
328
329 fsi_master_mask_set(master, IMSK, data, data);
330 fsi_master_mask_set(master, IEMSK, data, data);
331 }
332
333 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
334 {
335 u32 data = fsi_port_ab_io_bit(fsi, is_play);
336 struct fsi_master *master = fsi_get_master(fsi);
337
338 fsi_master_mask_set(master, IMSK, data, 0);
339 fsi_master_mask_set(master, IEMSK, data, 0);
340 }
341
342 static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable)
343 {
344 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4);
345 struct fsi_master *master = fsi_get_master(fsi);
346
347 if (enable)
348 fsi_master_mask_set(master, CLK_RST, val, val);
349 else
350 fsi_master_mask_set(master, CLK_RST, val, 0);
351 }
352
353 static void fsi_irq_init(struct fsi_priv *fsi, int is_play)
354 {
355 u32 data;
356 u32 ctrl;
357
358 data = fsi_port_ab_io_bit(fsi, is_play);
359 ctrl = is_play ? DOFF_CTL : DIFF_CTL;
360
361 /* set IMSK */
362 fsi_irq_disable(fsi, is_play);
363
364 /* set interrupt generation factor */
365 fsi_reg_write(fsi, ctrl, IRQ_HALF);
366
367 /* clear FIFO */
368 fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR);
369
370 /* clear interrupt factor */
371 fsi_master_mask_set(fsi_get_master(fsi), INT_ST, data, 0);
372 }
373
374 static void fsi_soft_all_reset(struct fsi_master *master)
375 {
376 u32 status = fsi_master_read(master, SOFT_RST);
377
378 /* port AB reset */
379 status &= 0x000000ff;
380 fsi_master_write(master, SOFT_RST, status);
381 mdelay(10);
382
383 /* soft reset */
384 status &= 0x000000f0;
385 fsi_master_write(master, SOFT_RST, status);
386 status |= 0x00000001;
387 fsi_master_write(master, SOFT_RST, status);
388 mdelay(10);
389 }
390
391 /* playback interrupt */
392 static int fsi_data_push(struct fsi_priv *fsi, int startup)
393 {
394 struct snd_pcm_runtime *runtime;
395 struct snd_pcm_substream *substream = NULL;
396 u32 status;
397 int send;
398 int fifo_free;
399 int width;
400 u8 *start;
401 int i, over_period;
402
403 if (!fsi ||
404 !fsi->substream ||
405 !fsi->substream->runtime)
406 return -EINVAL;
407
408 over_period = 0;
409 substream = fsi->substream;
410 runtime = substream->runtime;
411
412 /* FSI FIFO has limit.
413 * So, this driver can not send periods data at a time
414 */
415 if (fsi->byte_offset >=
416 fsi->period_len * (fsi->periods + 1)) {
417
418 over_period = 1;
419 fsi->periods = (fsi->periods + 1) % runtime->periods;
420
421 if (0 == fsi->periods)
422 fsi->byte_offset = 0;
423 }
424
425 /* get 1 channel data width */
426 width = frames_to_bytes(runtime, 1) / fsi->chan;
427
428 /* get send size for alsa */
429 send = (fsi->buffer_len - fsi->byte_offset) / width;
430
431 /* get FIFO free size */
432 fifo_free = (fsi->fifo_max * fsi->chan) - fsi_get_fifo_residue(fsi, 1);
433
434 /* size check */
435 if (fifo_free < send)
436 send = fifo_free;
437
438 start = runtime->dma_area;
439 start += fsi->byte_offset;
440
441 switch (width) {
442 case 2:
443 for (i = 0; i < send; i++)
444 fsi_reg_write(fsi, DODT,
445 ((u32)*((u16 *)start + i) << 8));
446 break;
447 case 4:
448 for (i = 0; i < send; i++)
449 fsi_reg_write(fsi, DODT, *((u32 *)start + i));
450 break;
451 default:
452 return -EINVAL;
453 }
454
455 fsi->byte_offset += send * width;
456
457 status = fsi_reg_read(fsi, DOFF_ST);
458 if (!startup) {
459 struct snd_soc_dai *dai = fsi_get_dai(substream);
460
461 if (status & ERR_OVER)
462 dev_err(dai->dev, "over run\n");
463 if (status & ERR_UNDER)
464 dev_err(dai->dev, "under run\n");
465 }
466 fsi_reg_write(fsi, DOFF_ST, 0);
467
468 fsi_irq_enable(fsi, 1);
469
470 if (over_period)
471 snd_pcm_period_elapsed(substream);
472
473 return 0;
474 }
475
476 static int fsi_data_pop(struct fsi_priv *fsi, int startup)
477 {
478 struct snd_pcm_runtime *runtime;
479 struct snd_pcm_substream *substream = NULL;
480 u32 status;
481 int free;
482 int fifo_fill;
483 int width;
484 u8 *start;
485 int i, over_period;
486
487 if (!fsi ||
488 !fsi->substream ||
489 !fsi->substream->runtime)
490 return -EINVAL;
491
492 over_period = 0;
493 substream = fsi->substream;
494 runtime = substream->runtime;
495
496 /* FSI FIFO has limit.
497 * So, this driver can not send periods data at a time
498 */
499 if (fsi->byte_offset >=
500 fsi->period_len * (fsi->periods + 1)) {
501
502 over_period = 1;
503 fsi->periods = (fsi->periods + 1) % runtime->periods;
504
505 if (0 == fsi->periods)
506 fsi->byte_offset = 0;
507 }
508
509 /* get 1 channel data width */
510 width = frames_to_bytes(runtime, 1) / fsi->chan;
511
512 /* get free space for alsa */
513 free = (fsi->buffer_len - fsi->byte_offset) / width;
514
515 /* get recv size */
516 fifo_fill = fsi_get_fifo_residue(fsi, 0);
517
518 if (free < fifo_fill)
519 fifo_fill = free;
520
521 start = runtime->dma_area;
522 start += fsi->byte_offset;
523
524 switch (width) {
525 case 2:
526 for (i = 0; i < fifo_fill; i++)
527 *((u16 *)start + i) =
528 (u16)(fsi_reg_read(fsi, DIDT) >> 8);
529 break;
530 case 4:
531 for (i = 0; i < fifo_fill; i++)
532 *((u32 *)start + i) = fsi_reg_read(fsi, DIDT);
533 break;
534 default:
535 return -EINVAL;
536 }
537
538 fsi->byte_offset += fifo_fill * width;
539
540 status = fsi_reg_read(fsi, DIFF_ST);
541 if (!startup) {
542 struct snd_soc_dai *dai = fsi_get_dai(substream);
543
544 if (status & ERR_OVER)
545 dev_err(dai->dev, "over run\n");
546 if (status & ERR_UNDER)
547 dev_err(dai->dev, "under run\n");
548 }
549 fsi_reg_write(fsi, DIFF_ST, 0);
550
551 fsi_irq_enable(fsi, 0);
552
553 if (over_period)
554 snd_pcm_period_elapsed(substream);
555
556 return 0;
557 }
558
559 static irqreturn_t fsi_interrupt(int irq, void *data)
560 {
561 struct fsi_master *master = data;
562 u32 status = fsi_master_read(master, SOFT_RST) & ~0x00000010;
563 u32 int_st = fsi_master_read(master, INT_ST);
564
565 /* clear irq status */
566 fsi_master_write(master, SOFT_RST, status);
567 fsi_master_write(master, SOFT_RST, status | 0x00000010);
568
569 if (int_st & INT_A_OUT)
570 fsi_data_push(&master->fsia, 0);
571 if (int_st & INT_B_OUT)
572 fsi_data_push(&master->fsib, 0);
573 if (int_st & INT_A_IN)
574 fsi_data_pop(&master->fsia, 0);
575 if (int_st & INT_B_IN)
576 fsi_data_pop(&master->fsib, 0);
577
578 fsi_master_write(master, INT_ST, 0x0000000);
579
580 return IRQ_HANDLED;
581 }
582
583 /************************************************************************
584
585
586 dai ops
587
588
589 ************************************************************************/
590 static int fsi_dai_startup(struct snd_pcm_substream *substream,
591 struct snd_soc_dai *dai)
592 {
593 struct fsi_priv *fsi = fsi_get_priv(substream);
594 const char *msg;
595 u32 flags = fsi_get_info_flags(fsi);
596 u32 fmt;
597 u32 reg;
598 u32 data;
599 int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
600 int is_master;
601 int ret = 0;
602
603 pm_runtime_get_sync(dai->dev);
604
605 /* CKG1 */
606 data = is_play ? (1 << 0) : (1 << 4);
607 is_master = fsi_is_master_mode(fsi, is_play);
608 if (is_master)
609 fsi_reg_mask_set(fsi, CKG1, data, data);
610 else
611 fsi_reg_mask_set(fsi, CKG1, data, 0);
612
613 /* clock inversion (CKG2) */
614 data = 0;
615 switch (SH_FSI_INVERSION_MASK & flags) {
616 case SH_FSI_LRM_INV:
617 data = 1 << 12;
618 break;
619 case SH_FSI_BRM_INV:
620 data = 1 << 8;
621 break;
622 case SH_FSI_LRS_INV:
623 data = 1 << 4;
624 break;
625 case SH_FSI_BRS_INV:
626 data = 1 << 0;
627 break;
628 }
629 fsi_reg_write(fsi, CKG2, data);
630
631 /* do fmt, di fmt */
632 data = 0;
633 reg = is_play ? DO_FMT : DI_FMT;
634 fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags);
635 switch (fmt) {
636 case SH_FSI_FMT_MONO:
637 msg = "MONO";
638 data = CR_FMT(CR_MONO);
639 fsi->chan = 1;
640 break;
641 case SH_FSI_FMT_MONO_DELAY:
642 msg = "MONO Delay";
643 data = CR_FMT(CR_MONO_D);
644 fsi->chan = 1;
645 break;
646 case SH_FSI_FMT_PCM:
647 msg = "PCM";
648 data = CR_FMT(CR_PCM);
649 fsi->chan = 2;
650 break;
651 case SH_FSI_FMT_I2S:
652 msg = "I2S";
653 data = CR_FMT(CR_I2S);
654 fsi->chan = 2;
655 break;
656 case SH_FSI_FMT_TDM:
657 msg = "TDM";
658 data = CR_FMT(CR_TDM) | (fsi->chan - 1);
659 fsi->chan = is_play ?
660 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
661 break;
662 case SH_FSI_FMT_TDM_DELAY:
663 msg = "TDM Delay";
664 data = CR_FMT(CR_TDM_D) | (fsi->chan - 1);
665 fsi->chan = is_play ?
666 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
667 break;
668 default:
669 dev_err(dai->dev, "unknown format.\n");
670 return -EINVAL;
671 }
672
673 switch (fsi->chan) {
674 case 1:
675 fsi->fifo_max = 256;
676 break;
677 case 2:
678 fsi->fifo_max = 128;
679 break;
680 case 3:
681 case 4:
682 fsi->fifo_max = 64;
683 break;
684 case 5:
685 case 6:
686 case 7:
687 case 8:
688 fsi->fifo_max = 32;
689 break;
690 default:
691 dev_err(dai->dev, "channel size error.\n");
692 return -EINVAL;
693 }
694
695 fsi_reg_write(fsi, reg, data);
696
697 /*
698 * clear clk reset if master mode
699 */
700 if (is_master)
701 fsi_clk_ctrl(fsi, 1);
702
703 /* irq setting */
704 fsi_irq_init(fsi, is_play);
705
706 return ret;
707 }
708
709 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
710 struct snd_soc_dai *dai)
711 {
712 struct fsi_priv *fsi = fsi_get_priv(substream);
713 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
714
715 fsi_irq_disable(fsi, is_play);
716 fsi_clk_ctrl(fsi, 0);
717
718 pm_runtime_put_sync(dai->dev);
719 }
720
721 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
722 struct snd_soc_dai *dai)
723 {
724 struct fsi_priv *fsi = fsi_get_priv(substream);
725 struct snd_pcm_runtime *runtime = substream->runtime;
726 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
727 int ret = 0;
728
729 switch (cmd) {
730 case SNDRV_PCM_TRIGGER_START:
731 fsi_stream_push(fsi, substream,
732 frames_to_bytes(runtime, runtime->buffer_size),
733 frames_to_bytes(runtime, runtime->period_size));
734 ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1);
735 break;
736 case SNDRV_PCM_TRIGGER_STOP:
737 fsi_irq_disable(fsi, is_play);
738 fsi_stream_pop(fsi);
739 break;
740 }
741
742 return ret;
743 }
744
745 static struct snd_soc_dai_ops fsi_dai_ops = {
746 .startup = fsi_dai_startup,
747 .shutdown = fsi_dai_shutdown,
748 .trigger = fsi_dai_trigger,
749 };
750
751 /************************************************************************
752
753
754 pcm ops
755
756
757 ************************************************************************/
758 static struct snd_pcm_hardware fsi_pcm_hardware = {
759 .info = SNDRV_PCM_INFO_INTERLEAVED |
760 SNDRV_PCM_INFO_MMAP |
761 SNDRV_PCM_INFO_MMAP_VALID |
762 SNDRV_PCM_INFO_PAUSE,
763 .formats = FSI_FMTS,
764 .rates = FSI_RATES,
765 .rate_min = 8000,
766 .rate_max = 192000,
767 .channels_min = 1,
768 .channels_max = 2,
769 .buffer_bytes_max = 64 * 1024,
770 .period_bytes_min = 32,
771 .period_bytes_max = 8192,
772 .periods_min = 1,
773 .periods_max = 32,
774 .fifo_size = 256,
775 };
776
777 static int fsi_pcm_open(struct snd_pcm_substream *substream)
778 {
779 struct snd_pcm_runtime *runtime = substream->runtime;
780 int ret = 0;
781
782 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
783
784 ret = snd_pcm_hw_constraint_integer(runtime,
785 SNDRV_PCM_HW_PARAM_PERIODS);
786
787 return ret;
788 }
789
790 static int fsi_hw_params(struct snd_pcm_substream *substream,
791 struct snd_pcm_hw_params *hw_params)
792 {
793 return snd_pcm_lib_malloc_pages(substream,
794 params_buffer_bytes(hw_params));
795 }
796
797 static int fsi_hw_free(struct snd_pcm_substream *substream)
798 {
799 return snd_pcm_lib_free_pages(substream);
800 }
801
802 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
803 {
804 struct snd_pcm_runtime *runtime = substream->runtime;
805 struct fsi_priv *fsi = fsi_get_priv(substream);
806 long location;
807
808 location = (fsi->byte_offset - 1);
809 if (location < 0)
810 location = 0;
811
812 return bytes_to_frames(runtime, location);
813 }
814
815 static struct snd_pcm_ops fsi_pcm_ops = {
816 .open = fsi_pcm_open,
817 .ioctl = snd_pcm_lib_ioctl,
818 .hw_params = fsi_hw_params,
819 .hw_free = fsi_hw_free,
820 .pointer = fsi_pointer,
821 };
822
823 /************************************************************************
824
825
826 snd_soc_platform
827
828
829 ************************************************************************/
830 #define PREALLOC_BUFFER (32 * 1024)
831 #define PREALLOC_BUFFER_MAX (32 * 1024)
832
833 static void fsi_pcm_free(struct snd_pcm *pcm)
834 {
835 snd_pcm_lib_preallocate_free_for_all(pcm);
836 }
837
838 static int fsi_pcm_new(struct snd_card *card,
839 struct snd_soc_dai *dai,
840 struct snd_pcm *pcm)
841 {
842 /*
843 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
844 * in MMAP mode (i.e. aplay -M)
845 */
846 return snd_pcm_lib_preallocate_pages_for_all(
847 pcm,
848 SNDRV_DMA_TYPE_CONTINUOUS,
849 snd_dma_continuous_data(GFP_KERNEL),
850 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
851 }
852
853 /************************************************************************
854
855
856 alsa struct
857
858
859 ************************************************************************/
860 struct snd_soc_dai fsi_soc_dai[] = {
861 {
862 .name = "FSIA",
863 .id = 0,
864 .playback = {
865 .rates = FSI_RATES,
866 .formats = FSI_FMTS,
867 .channels_min = 1,
868 .channels_max = 8,
869 },
870 .capture = {
871 .rates = FSI_RATES,
872 .formats = FSI_FMTS,
873 .channels_min = 1,
874 .channels_max = 8,
875 },
876 .ops = &fsi_dai_ops,
877 },
878 {
879 .name = "FSIB",
880 .id = 1,
881 .playback = {
882 .rates = FSI_RATES,
883 .formats = FSI_FMTS,
884 .channels_min = 1,
885 .channels_max = 8,
886 },
887 .capture = {
888 .rates = FSI_RATES,
889 .formats = FSI_FMTS,
890 .channels_min = 1,
891 .channels_max = 8,
892 },
893 .ops = &fsi_dai_ops,
894 },
895 };
896 EXPORT_SYMBOL_GPL(fsi_soc_dai);
897
898 struct snd_soc_platform fsi_soc_platform = {
899 .name = "fsi-pcm",
900 .pcm_ops = &fsi_pcm_ops,
901 .pcm_new = fsi_pcm_new,
902 .pcm_free = fsi_pcm_free,
903 };
904 EXPORT_SYMBOL_GPL(fsi_soc_platform);
905
906 /************************************************************************
907
908
909 platform function
910
911
912 ************************************************************************/
913 static int fsi_probe(struct platform_device *pdev)
914 {
915 struct fsi_master *master;
916 struct resource *res;
917 unsigned int irq;
918 int ret;
919
920 if (0 != pdev->id) {
921 dev_err(&pdev->dev, "current fsi support id 0 only now\n");
922 return -ENODEV;
923 }
924
925 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
926 irq = platform_get_irq(pdev, 0);
927 if (!res || (int)irq <= 0) {
928 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
929 ret = -ENODEV;
930 goto exit;
931 }
932
933 master = kzalloc(sizeof(*master), GFP_KERNEL);
934 if (!master) {
935 dev_err(&pdev->dev, "Could not allocate master\n");
936 ret = -ENOMEM;
937 goto exit;
938 }
939
940 master->base = ioremap_nocache(res->start, resource_size(res));
941 if (!master->base) {
942 ret = -ENXIO;
943 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
944 goto exit_kfree;
945 }
946
947 master->irq = irq;
948 master->info = pdev->dev.platform_data;
949 master->fsia.base = master->base;
950 master->fsia.master = master;
951 master->fsib.base = master->base + 0x40;
952 master->fsib.master = master;
953 spin_lock_init(&master->lock);
954
955 pm_runtime_enable(&pdev->dev);
956 pm_runtime_resume(&pdev->dev);
957
958 fsi_soc_dai[0].dev = &pdev->dev;
959 fsi_soc_dai[0].private_data = &master->fsia;
960 fsi_soc_dai[1].dev = &pdev->dev;
961 fsi_soc_dai[1].private_data = &master->fsib;
962
963 fsi_soft_all_reset(master);
964
965 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED, "fsi", master);
966 if (ret) {
967 dev_err(&pdev->dev, "irq request err\n");
968 goto exit_iounmap;
969 }
970
971 ret = snd_soc_register_platform(&fsi_soc_platform);
972 if (ret < 0) {
973 dev_err(&pdev->dev, "cannot snd soc register\n");
974 goto exit_free_irq;
975 }
976
977 return snd_soc_register_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
978
979 exit_free_irq:
980 free_irq(irq, master);
981 exit_iounmap:
982 iounmap(master->base);
983 pm_runtime_disable(&pdev->dev);
984 exit_kfree:
985 kfree(master);
986 master = NULL;
987 exit:
988 return ret;
989 }
990
991 static int fsi_remove(struct platform_device *pdev)
992 {
993 struct fsi_master *master;
994
995 master = fsi_get_master(fsi_soc_dai[0].private_data);
996
997 snd_soc_unregister_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
998 snd_soc_unregister_platform(&fsi_soc_platform);
999
1000 pm_runtime_disable(&pdev->dev);
1001
1002 free_irq(master->irq, master);
1003
1004 iounmap(master->base);
1005 kfree(master);
1006
1007 fsi_soc_dai[0].dev = NULL;
1008 fsi_soc_dai[0].private_data = NULL;
1009 fsi_soc_dai[1].dev = NULL;
1010 fsi_soc_dai[1].private_data = NULL;
1011
1012 return 0;
1013 }
1014
1015 static int fsi_runtime_nop(struct device *dev)
1016 {
1017 /* Runtime PM callback shared between ->runtime_suspend()
1018 * and ->runtime_resume(). Simply returns success.
1019 *
1020 * This driver re-initializes all registers after
1021 * pm_runtime_get_sync() anyway so there is no need
1022 * to save and restore registers here.
1023 */
1024 return 0;
1025 }
1026
1027 static struct dev_pm_ops fsi_pm_ops = {
1028 .runtime_suspend = fsi_runtime_nop,
1029 .runtime_resume = fsi_runtime_nop,
1030 };
1031
1032 static struct platform_driver fsi_driver = {
1033 .driver = {
1034 .name = "sh_fsi",
1035 .pm = &fsi_pm_ops,
1036 },
1037 .probe = fsi_probe,
1038 .remove = fsi_remove,
1039 };
1040
1041 static int __init fsi_mobile_init(void)
1042 {
1043 return platform_driver_register(&fsi_driver);
1044 }
1045
1046 static void __exit fsi_mobile_exit(void)
1047 {
1048 platform_driver_unregister(&fsi_driver);
1049 }
1050 module_init(fsi_mobile_init);
1051 module_exit(fsi_mobile_exit);
1052
1053 MODULE_LICENSE("GPL");
1054 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1055 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
Ubuntu Hirsute Linux kernel mirror