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[mirror_ubuntu-zesty-kernel.git] / sound / soc / sh / fsi.c
1 /*
2 * Fifo-attached Serial Interface (FSI) support for SH7724
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ssi.c
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/delay.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <sound/soc.h>
20 #include <sound/sh_fsi.h>
21
22 /* PortA/PortB register */
23 #define REG_DO_FMT 0x0000
24 #define REG_DOFF_CTL 0x0004
25 #define REG_DOFF_ST 0x0008
26 #define REG_DI_FMT 0x000C
27 #define REG_DIFF_CTL 0x0010
28 #define REG_DIFF_ST 0x0014
29 #define REG_CKG1 0x0018
30 #define REG_CKG2 0x001C
31 #define REG_DIDT 0x0020
32 #define REG_DODT 0x0024
33 #define REG_MUTE_ST 0x0028
34 #define REG_OUT_SEL 0x0030
35
36 /* master register */
37 #define MST_CLK_RST 0x0210
38 #define MST_SOFT_RST 0x0214
39 #define MST_FIFO_SZ 0x0218
40
41 /* core register (depend on FSI version) */
42 #define A_MST_CTLR 0x0180
43 #define B_MST_CTLR 0x01A0
44 #define CPU_INT_ST 0x01F4
45 #define CPU_IEMSK 0x01F8
46 #define CPU_IMSK 0x01FC
47 #define INT_ST 0x0200
48 #define IEMSK 0x0204
49 #define IMSK 0x0208
50
51 /* DO_FMT */
52 /* DI_FMT */
53 #define CR_BWS_24 (0x0 << 20) /* FSI2 */
54 #define CR_BWS_16 (0x1 << 20) /* FSI2 */
55 #define CR_BWS_20 (0x2 << 20) /* FSI2 */
56
57 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
58 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
59 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
60
61 #define CR_MONO (0x0 << 4)
62 #define CR_MONO_D (0x1 << 4)
63 #define CR_PCM (0x2 << 4)
64 #define CR_I2S (0x3 << 4)
65 #define CR_TDM (0x4 << 4)
66 #define CR_TDM_D (0x5 << 4)
67
68 /* DOFF_CTL */
69 /* DIFF_CTL */
70 #define IRQ_HALF 0x00100000
71 #define FIFO_CLR 0x00000001
72
73 /* DOFF_ST */
74 #define ERR_OVER 0x00000010
75 #define ERR_UNDER 0x00000001
76 #define ST_ERR (ERR_OVER | ERR_UNDER)
77
78 /* CKG1 */
79 #define ACKMD_MASK 0x00007000
80 #define BPFMD_MASK 0x00000700
81
82 /* A/B MST_CTLR */
83 #define BP (1 << 4) /* Fix the signal of Biphase output */
84 #define SE (1 << 0) /* Fix the master clock */
85
86 /* CLK_RST */
87 #define B_CLK 0x00000010
88 #define A_CLK 0x00000001
89
90 /* IO SHIFT / MACRO */
91 #define BI_SHIFT 12
92 #define BO_SHIFT 8
93 #define AI_SHIFT 4
94 #define AO_SHIFT 0
95 #define AB_IO(param, shift) (param << shift)
96
97 /* SOFT_RST */
98 #define PBSR (1 << 12) /* Port B Software Reset */
99 #define PASR (1 << 8) /* Port A Software Reset */
100 #define IR (1 << 4) /* Interrupt Reset */
101 #define FSISR (1 << 0) /* Software Reset */
102
103 /* OUT_SEL (FSI2) */
104 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
105 /* 1: Biphase and serial */
106
107 /* FIFO_SZ */
108 #define FIFO_SZ_MASK 0x7
109
110 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
111
112 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
113
114 /*
115 * FSI driver use below type name for variable
116 *
117 * xxx_len : data length
118 * xxx_width : data width
119 * xxx_offset : data offset
120 * xxx_num : number of data
121 */
122
123 /*
124 * struct
125 */
126
127 struct fsi_stream {
128 struct snd_pcm_substream *substream;
129
130 int fifo_max_num;
131 int chan_num;
132
133 int buff_offset;
134 int buff_len;
135 int period_len;
136 int period_num;
137 };
138
139 struct fsi_priv {
140 void __iomem *base;
141 struct fsi_master *master;
142
143 struct fsi_stream playback;
144 struct fsi_stream capture;
145
146 long rate;
147 };
148
149 struct fsi_core {
150 int ver;
151
152 u32 int_st;
153 u32 iemsk;
154 u32 imsk;
155 u32 a_mclk;
156 u32 b_mclk;
157 };
158
159 struct fsi_master {
160 void __iomem *base;
161 int irq;
162 struct fsi_priv fsia;
163 struct fsi_priv fsib;
164 struct fsi_core *core;
165 struct sh_fsi_platform_info *info;
166 spinlock_t lock;
167 };
168
169 /*
170 * basic read write function
171 */
172
173 static void __fsi_reg_write(u32 reg, u32 data)
174 {
175 /* valid data area is 24bit */
176 data &= 0x00ffffff;
177
178 __raw_writel(data, reg);
179 }
180
181 static u32 __fsi_reg_read(u32 reg)
182 {
183 return __raw_readl(reg);
184 }
185
186 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
187 {
188 u32 val = __fsi_reg_read(reg);
189
190 val &= ~mask;
191 val |= data & mask;
192
193 __fsi_reg_write(reg, val);
194 }
195
196 #define fsi_reg_write(p, r, d)\
197 __fsi_reg_write((u32)(p->base + REG_##r), d)
198
199 #define fsi_reg_read(p, r)\
200 __fsi_reg_read((u32)(p->base + REG_##r))
201
202 #define fsi_reg_mask_set(p, r, m, d)\
203 __fsi_reg_mask_set((u32)(p->base + REG_##r), m, d)
204
205 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
206 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
207 static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
208 {
209 u32 ret;
210 unsigned long flags;
211
212 spin_lock_irqsave(&master->lock, flags);
213 ret = __fsi_reg_read((u32)(master->base + reg));
214 spin_unlock_irqrestore(&master->lock, flags);
215
216 return ret;
217 }
218
219 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
220 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
221 static void _fsi_master_mask_set(struct fsi_master *master,
222 u32 reg, u32 mask, u32 data)
223 {
224 unsigned long flags;
225
226 spin_lock_irqsave(&master->lock, flags);
227 __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
228 spin_unlock_irqrestore(&master->lock, flags);
229 }
230
231 /*
232 * basic function
233 */
234
235 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
236 {
237 return fsi->master;
238 }
239
240 static int fsi_is_port_a(struct fsi_priv *fsi)
241 {
242 return fsi->master->base == fsi->base;
243 }
244
245 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
246 {
247 struct snd_soc_pcm_runtime *rtd = substream->private_data;
248
249 return rtd->cpu_dai;
250 }
251
252 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
253 {
254 struct snd_soc_dai *dai = fsi_get_dai(substream);
255 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
256
257 if (dai->id == 0)
258 return &master->fsia;
259 else
260 return &master->fsib;
261 }
262
263 static u32 fsi_get_info_flags(struct fsi_priv *fsi)
264 {
265 int is_porta = fsi_is_port_a(fsi);
266 struct fsi_master *master = fsi_get_master(fsi);
267
268 return is_porta ? master->info->porta_flags :
269 master->info->portb_flags;
270 }
271
272 static inline int fsi_stream_is_play(int stream)
273 {
274 return stream == SNDRV_PCM_STREAM_PLAYBACK;
275 }
276
277 static inline int fsi_is_play(struct snd_pcm_substream *substream)
278 {
279 return fsi_stream_is_play(substream->stream);
280 }
281
282 static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi,
283 int is_play)
284 {
285 return is_play ? &fsi->playback : &fsi->capture;
286 }
287
288 static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play)
289 {
290 u32 mode;
291 u32 flags = fsi_get_info_flags(fsi);
292
293 mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE;
294
295 /* return
296 * 1 : master mode
297 * 0 : slave mode
298 */
299
300 return (mode & flags) != mode;
301 }
302
303 static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play)
304 {
305 int is_porta = fsi_is_port_a(fsi);
306 u32 shift;
307
308 if (is_porta)
309 shift = is_play ? AO_SHIFT : AI_SHIFT;
310 else
311 shift = is_play ? BO_SHIFT : BI_SHIFT;
312
313 return shift;
314 }
315
316 static void fsi_stream_push(struct fsi_priv *fsi,
317 int is_play,
318 struct snd_pcm_substream *substream,
319 u32 buffer_len,
320 u32 period_len)
321 {
322 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
323
324 io->substream = substream;
325 io->buff_len = buffer_len;
326 io->buff_offset = 0;
327 io->period_len = period_len;
328 io->period_num = 0;
329 }
330
331 static void fsi_stream_pop(struct fsi_priv *fsi, int is_play)
332 {
333 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
334
335 io->substream = NULL;
336 io->buff_len = 0;
337 io->buff_offset = 0;
338 io->period_len = 0;
339 io->period_num = 0;
340 }
341
342 static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play)
343 {
344 u32 status;
345 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
346 int data_num;
347
348 status = is_play ?
349 fsi_reg_read(fsi, DOFF_ST) :
350 fsi_reg_read(fsi, DIFF_ST);
351
352 data_num = 0x1ff & (status >> 8);
353 data_num *= io->chan_num;
354
355 return data_num;
356 }
357
358 static int fsi_len2num(int len, int width)
359 {
360 return len / width;
361 }
362
363 #define fsi_num2offset(a, b) fsi_num2len(a, b)
364 static int fsi_num2len(int num, int width)
365 {
366 return num * width;
367 }
368
369 static int fsi_get_frame_width(struct fsi_priv *fsi, int is_play)
370 {
371 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
372 struct snd_pcm_substream *substream = io->substream;
373 struct snd_pcm_runtime *runtime = substream->runtime;
374
375 return frames_to_bytes(runtime, 1) / io->chan_num;
376 }
377
378 /*
379 * dma function
380 */
381
382 static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream)
383 {
384 int is_play = fsi_stream_is_play(stream);
385 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
386
387 return io->substream->runtime->dma_area + io->buff_offset;
388 }
389
390 static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num)
391 {
392 u16 *start;
393 int i;
394
395 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
396
397 for (i = 0; i < num; i++)
398 fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8));
399 }
400
401 static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num)
402 {
403 u16 *start;
404 int i;
405
406 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
407
408
409 for (i = 0; i < num; i++)
410 *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
411 }
412
413 static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num)
414 {
415 u32 *start;
416 int i;
417
418 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
419
420
421 for (i = 0; i < num; i++)
422 fsi_reg_write(fsi, DODT, *(start + i));
423 }
424
425 static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num)
426 {
427 u32 *start;
428 int i;
429
430 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
431
432 for (i = 0; i < num; i++)
433 *(start + i) = fsi_reg_read(fsi, DIDT);
434 }
435
436 /*
437 * irq function
438 */
439
440 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
441 {
442 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
443 struct fsi_master *master = fsi_get_master(fsi);
444
445 fsi_core_mask_set(master, imsk, data, data);
446 fsi_core_mask_set(master, iemsk, data, data);
447 }
448
449 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
450 {
451 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
452 struct fsi_master *master = fsi_get_master(fsi);
453
454 fsi_core_mask_set(master, imsk, data, 0);
455 fsi_core_mask_set(master, iemsk, data, 0);
456 }
457
458 static u32 fsi_irq_get_status(struct fsi_master *master)
459 {
460 return fsi_core_read(master, int_st);
461 }
462
463 static void fsi_irq_clear_status(struct fsi_priv *fsi)
464 {
465 u32 data = 0;
466 struct fsi_master *master = fsi_get_master(fsi);
467
468 data |= AB_IO(1, fsi_get_port_shift(fsi, 0));
469 data |= AB_IO(1, fsi_get_port_shift(fsi, 1));
470
471 /* clear interrupt factor */
472 fsi_core_mask_set(master, int_st, data, 0);
473 }
474
475 /*
476 * SPDIF master clock function
477 *
478 * These functions are used later FSI2
479 */
480 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
481 {
482 struct fsi_master *master = fsi_get_master(fsi);
483 u32 mask, val;
484
485 if (master->core->ver < 2) {
486 pr_err("fsi: register access err (%s)\n", __func__);
487 return;
488 }
489
490 mask = BP | SE;
491 val = enable ? mask : 0;
492
493 fsi_is_port_a(fsi) ?
494 fsi_core_mask_set(master, a_mclk, mask, val) :
495 fsi_core_mask_set(master, b_mclk, mask, val);
496 }
497
498 /*
499 * ctrl function
500 */
501
502 static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable)
503 {
504 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4);
505 struct fsi_master *master = fsi_get_master(fsi);
506
507 if (enable)
508 fsi_master_mask_set(master, CLK_RST, val, val);
509 else
510 fsi_master_mask_set(master, CLK_RST, val, 0);
511 }
512
513 static void fsi_fifo_init(struct fsi_priv *fsi,
514 int is_play,
515 struct snd_soc_dai *dai)
516 {
517 struct fsi_master *master = fsi_get_master(fsi);
518 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
519 u32 shift, i;
520
521 /* get on-chip RAM capacity */
522 shift = fsi_master_read(master, FIFO_SZ);
523 shift >>= fsi_get_port_shift(fsi, is_play);
524 shift &= FIFO_SZ_MASK;
525 io->fifo_max_num = 256 << shift;
526 dev_dbg(dai->dev, "fifo = %d words\n", io->fifo_max_num);
527
528 /*
529 * The maximum number of sample data varies depending
530 * on the number of channels selected for the format.
531 *
532 * FIFOs are used in 4-channel units in 3-channel mode
533 * and in 8-channel units in 5- to 7-channel mode
534 * meaning that more FIFOs than the required size of DPRAM
535 * are used.
536 *
537 * ex) if 256 words of DP-RAM is connected
538 * 1 channel: 256 (256 x 1 = 256)
539 * 2 channels: 128 (128 x 2 = 256)
540 * 3 channels: 64 ( 64 x 3 = 192)
541 * 4 channels: 64 ( 64 x 4 = 256)
542 * 5 channels: 32 ( 32 x 5 = 160)
543 * 6 channels: 32 ( 32 x 6 = 192)
544 * 7 channels: 32 ( 32 x 7 = 224)
545 * 8 channels: 32 ( 32 x 8 = 256)
546 */
547 for (i = 1; i < io->chan_num; i <<= 1)
548 io->fifo_max_num >>= 1;
549 dev_dbg(dai->dev, "%d channel %d store\n",
550 io->chan_num, io->fifo_max_num);
551
552 /*
553 * set interrupt generation factor
554 * clear FIFO
555 */
556 if (is_play) {
557 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
558 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
559 } else {
560 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
561 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
562 }
563 }
564
565 static void fsi_soft_all_reset(struct fsi_master *master)
566 {
567 /* port AB reset */
568 fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0);
569 mdelay(10);
570
571 /* soft reset */
572 fsi_master_mask_set(master, SOFT_RST, FSISR, 0);
573 fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR);
574 mdelay(10);
575 }
576
577 static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int startup, int stream)
578 {
579 struct snd_pcm_runtime *runtime;
580 struct snd_pcm_substream *substream = NULL;
581 int is_play = fsi_stream_is_play(stream);
582 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
583 int data_residue_num;
584 int data_num;
585 int data_num_max;
586 int ch_width;
587 int over_period;
588 void (*fn)(struct fsi_priv *fsi, int size);
589
590 if (!fsi ||
591 !io->substream ||
592 !io->substream->runtime)
593 return -EINVAL;
594
595 over_period = 0;
596 substream = io->substream;
597 runtime = substream->runtime;
598
599 /* FSI FIFO has limit.
600 * So, this driver can not send periods data at a time
601 */
602 if (io->buff_offset >=
603 fsi_num2offset(io->period_num + 1, io->period_len)) {
604
605 over_period = 1;
606 io->period_num = (io->period_num + 1) % runtime->periods;
607
608 if (0 == io->period_num)
609 io->buff_offset = 0;
610 }
611
612 /* get 1 channel data width */
613 ch_width = fsi_get_frame_width(fsi, is_play);
614
615 /* get residue data number of alsa */
616 data_residue_num = fsi_len2num(io->buff_len - io->buff_offset,
617 ch_width);
618
619 if (is_play) {
620 /*
621 * for play-back
622 *
623 * data_num_max : number of FSI fifo free space
624 * data_num : number of ALSA residue data
625 */
626 data_num_max = io->fifo_max_num * io->chan_num;
627 data_num_max -= fsi_get_fifo_data_num(fsi, is_play);
628
629 data_num = data_residue_num;
630
631 switch (ch_width) {
632 case 2:
633 fn = fsi_dma_soft_push16;
634 break;
635 case 4:
636 fn = fsi_dma_soft_push32;
637 break;
638 default:
639 return -EINVAL;
640 }
641 } else {
642 /*
643 * for capture
644 *
645 * data_num_max : number of ALSA free space
646 * data_num : number of data in FSI fifo
647 */
648 data_num_max = data_residue_num;
649 data_num = fsi_get_fifo_data_num(fsi, is_play);
650
651 switch (ch_width) {
652 case 2:
653 fn = fsi_dma_soft_pop16;
654 break;
655 case 4:
656 fn = fsi_dma_soft_pop32;
657 break;
658 default:
659 return -EINVAL;
660 }
661 }
662
663 data_num = min(data_num, data_num_max);
664
665 fn(fsi, data_num);
666
667 /* update buff_offset */
668 io->buff_offset += fsi_num2offset(data_num, ch_width);
669
670 /* check fifo status */
671 if (!startup) {
672 struct snd_soc_dai *dai = fsi_get_dai(substream);
673 u32 status = is_play ?
674 fsi_reg_read(fsi, DOFF_ST) :
675 fsi_reg_read(fsi, DIFF_ST);
676
677 if (status & ERR_OVER)
678 dev_err(dai->dev, "over run\n");
679 if (status & ERR_UNDER)
680 dev_err(dai->dev, "under run\n");
681 }
682
683 is_play ?
684 fsi_reg_write(fsi, DOFF_ST, 0) :
685 fsi_reg_write(fsi, DIFF_ST, 0);
686
687 /* re-enable irq */
688 fsi_irq_enable(fsi, is_play);
689
690 if (over_period)
691 snd_pcm_period_elapsed(substream);
692
693 return 0;
694 }
695
696 static int fsi_data_pop(struct fsi_priv *fsi, int startup)
697 {
698 return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_CAPTURE);
699 }
700
701 static int fsi_data_push(struct fsi_priv *fsi, int startup)
702 {
703 return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_PLAYBACK);
704 }
705
706 static irqreturn_t fsi_interrupt(int irq, void *data)
707 {
708 struct fsi_master *master = data;
709 u32 int_st = fsi_irq_get_status(master);
710
711 /* clear irq status */
712 fsi_master_mask_set(master, SOFT_RST, IR, 0);
713 fsi_master_mask_set(master, SOFT_RST, IR, IR);
714
715 if (int_st & AB_IO(1, AO_SHIFT))
716 fsi_data_push(&master->fsia, 0);
717 if (int_st & AB_IO(1, BO_SHIFT))
718 fsi_data_push(&master->fsib, 0);
719 if (int_st & AB_IO(1, AI_SHIFT))
720 fsi_data_pop(&master->fsia, 0);
721 if (int_st & AB_IO(1, BI_SHIFT))
722 fsi_data_pop(&master->fsib, 0);
723
724 fsi_irq_clear_status(&master->fsia);
725 fsi_irq_clear_status(&master->fsib);
726
727 return IRQ_HANDLED;
728 }
729
730 /*
731 * dai ops
732 */
733
734 static int fsi_dai_startup(struct snd_pcm_substream *substream,
735 struct snd_soc_dai *dai)
736 {
737 struct fsi_priv *fsi = fsi_get_priv(substream);
738 struct fsi_master *master = fsi_get_master(fsi);
739 struct fsi_stream *io;
740 u32 flags = fsi_get_info_flags(fsi);
741 u32 fmt;
742 u32 data;
743 int is_play = fsi_is_play(substream);
744 int is_master;
745
746 io = fsi_get_stream(fsi, is_play);
747
748 pm_runtime_get_sync(dai->dev);
749
750 /* CKG1 */
751 data = is_play ? (1 << 0) : (1 << 4);
752 is_master = fsi_is_master_mode(fsi, is_play);
753 if (is_master)
754 fsi_reg_mask_set(fsi, CKG1, data, data);
755 else
756 fsi_reg_mask_set(fsi, CKG1, data, 0);
757
758 /* clock inversion (CKG2) */
759 data = 0;
760 if (SH_FSI_LRM_INV & flags)
761 data |= 1 << 12;
762 if (SH_FSI_BRM_INV & flags)
763 data |= 1 << 8;
764 if (SH_FSI_LRS_INV & flags)
765 data |= 1 << 4;
766 if (SH_FSI_BRS_INV & flags)
767 data |= 1 << 0;
768
769 fsi_reg_write(fsi, CKG2, data);
770
771 /* do fmt, di fmt */
772 data = 0;
773 fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags);
774 switch (fmt) {
775 case SH_FSI_FMT_MONO:
776 data = CR_MONO;
777 io->chan_num = 1;
778 break;
779 case SH_FSI_FMT_MONO_DELAY:
780 data = CR_MONO_D;
781 io->chan_num = 1;
782 break;
783 case SH_FSI_FMT_PCM:
784 data = CR_PCM;
785 io->chan_num = 2;
786 break;
787 case SH_FSI_FMT_I2S:
788 data = CR_I2S;
789 io->chan_num = 2;
790 break;
791 case SH_FSI_FMT_TDM:
792 io->chan_num = is_play ?
793 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
794 data = CR_TDM | (io->chan_num - 1);
795 break;
796 case SH_FSI_FMT_TDM_DELAY:
797 io->chan_num = is_play ?
798 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
799 data = CR_TDM_D | (io->chan_num - 1);
800 break;
801 case SH_FSI_FMT_SPDIF:
802 if (master->core->ver < 2) {
803 dev_err(dai->dev, "This FSI can not use SPDIF\n");
804 return -EINVAL;
805 }
806 data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM;
807 io->chan_num = 2;
808 fsi_spdif_clk_ctrl(fsi, 1);
809 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
810 break;
811 default:
812 dev_err(dai->dev, "unknown format.\n");
813 return -EINVAL;
814 }
815 is_play ?
816 fsi_reg_write(fsi, DO_FMT, data) :
817 fsi_reg_write(fsi, DI_FMT, data);
818
819 /* irq clear */
820 fsi_irq_disable(fsi, is_play);
821 fsi_irq_clear_status(fsi);
822
823 /* fifo init */
824 fsi_fifo_init(fsi, is_play, dai);
825
826 return 0;
827 }
828
829 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
830 struct snd_soc_dai *dai)
831 {
832 struct fsi_priv *fsi = fsi_get_priv(substream);
833 int is_play = fsi_is_play(substream);
834 struct fsi_master *master = fsi_get_master(fsi);
835 int (*set_rate)(struct device *dev, int is_porta, int rate, int enable);
836
837 fsi_irq_disable(fsi, is_play);
838 fsi_clk_ctrl(fsi, 0);
839
840 set_rate = master->info->set_rate;
841 if (set_rate && fsi->rate)
842 set_rate(dai->dev, fsi_is_port_a(fsi), fsi->rate, 0);
843 fsi->rate = 0;
844
845 pm_runtime_put_sync(dai->dev);
846 }
847
848 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
849 struct snd_soc_dai *dai)
850 {
851 struct fsi_priv *fsi = fsi_get_priv(substream);
852 struct snd_pcm_runtime *runtime = substream->runtime;
853 int is_play = fsi_is_play(substream);
854 int ret = 0;
855
856 switch (cmd) {
857 case SNDRV_PCM_TRIGGER_START:
858 fsi_stream_push(fsi, is_play, substream,
859 frames_to_bytes(runtime, runtime->buffer_size),
860 frames_to_bytes(runtime, runtime->period_size));
861 ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1);
862 break;
863 case SNDRV_PCM_TRIGGER_STOP:
864 fsi_irq_disable(fsi, is_play);
865 fsi_stream_pop(fsi, is_play);
866 break;
867 }
868
869 return ret;
870 }
871
872 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
873 struct snd_pcm_hw_params *params,
874 struct snd_soc_dai *dai)
875 {
876 struct fsi_priv *fsi = fsi_get_priv(substream);
877 struct fsi_master *master = fsi_get_master(fsi);
878 int (*set_rate)(struct device *dev, int is_porta, int rate, int enable);
879 int fsi_ver = master->core->ver;
880 long rate = params_rate(params);
881 int ret;
882
883 set_rate = master->info->set_rate;
884 if (!set_rate)
885 return 0;
886
887 ret = set_rate(dai->dev, fsi_is_port_a(fsi), rate, 1);
888 if (ret < 0) /* error */
889 return ret;
890
891 fsi->rate = rate;
892 if (ret > 0) {
893 u32 data = 0;
894
895 switch (ret & SH_FSI_ACKMD_MASK) {
896 default:
897 /* FALL THROUGH */
898 case SH_FSI_ACKMD_512:
899 data |= (0x0 << 12);
900 break;
901 case SH_FSI_ACKMD_256:
902 data |= (0x1 << 12);
903 break;
904 case SH_FSI_ACKMD_128:
905 data |= (0x2 << 12);
906 break;
907 case SH_FSI_ACKMD_64:
908 data |= (0x3 << 12);
909 break;
910 case SH_FSI_ACKMD_32:
911 if (fsi_ver < 2)
912 dev_err(dai->dev, "unsupported ACKMD\n");
913 else
914 data |= (0x4 << 12);
915 break;
916 }
917
918 switch (ret & SH_FSI_BPFMD_MASK) {
919 default:
920 /* FALL THROUGH */
921 case SH_FSI_BPFMD_32:
922 data |= (0x0 << 8);
923 break;
924 case SH_FSI_BPFMD_64:
925 data |= (0x1 << 8);
926 break;
927 case SH_FSI_BPFMD_128:
928 data |= (0x2 << 8);
929 break;
930 case SH_FSI_BPFMD_256:
931 data |= (0x3 << 8);
932 break;
933 case SH_FSI_BPFMD_512:
934 data |= (0x4 << 8);
935 break;
936 case SH_FSI_BPFMD_16:
937 if (fsi_ver < 2)
938 dev_err(dai->dev, "unsupported ACKMD\n");
939 else
940 data |= (0x7 << 8);
941 break;
942 }
943
944 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
945 udelay(10);
946 fsi_clk_ctrl(fsi, 1);
947 ret = 0;
948 }
949
950 return ret;
951
952 }
953
954 static struct snd_soc_dai_ops fsi_dai_ops = {
955 .startup = fsi_dai_startup,
956 .shutdown = fsi_dai_shutdown,
957 .trigger = fsi_dai_trigger,
958 .hw_params = fsi_dai_hw_params,
959 };
960
961 /*
962 * pcm ops
963 */
964
965 static struct snd_pcm_hardware fsi_pcm_hardware = {
966 .info = SNDRV_PCM_INFO_INTERLEAVED |
967 SNDRV_PCM_INFO_MMAP |
968 SNDRV_PCM_INFO_MMAP_VALID |
969 SNDRV_PCM_INFO_PAUSE,
970 .formats = FSI_FMTS,
971 .rates = FSI_RATES,
972 .rate_min = 8000,
973 .rate_max = 192000,
974 .channels_min = 1,
975 .channels_max = 2,
976 .buffer_bytes_max = 64 * 1024,
977 .period_bytes_min = 32,
978 .period_bytes_max = 8192,
979 .periods_min = 1,
980 .periods_max = 32,
981 .fifo_size = 256,
982 };
983
984 static int fsi_pcm_open(struct snd_pcm_substream *substream)
985 {
986 struct snd_pcm_runtime *runtime = substream->runtime;
987 int ret = 0;
988
989 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
990
991 ret = snd_pcm_hw_constraint_integer(runtime,
992 SNDRV_PCM_HW_PARAM_PERIODS);
993
994 return ret;
995 }
996
997 static int fsi_hw_params(struct snd_pcm_substream *substream,
998 struct snd_pcm_hw_params *hw_params)
999 {
1000 return snd_pcm_lib_malloc_pages(substream,
1001 params_buffer_bytes(hw_params));
1002 }
1003
1004 static int fsi_hw_free(struct snd_pcm_substream *substream)
1005 {
1006 return snd_pcm_lib_free_pages(substream);
1007 }
1008
1009 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1010 {
1011 struct snd_pcm_runtime *runtime = substream->runtime;
1012 struct fsi_priv *fsi = fsi_get_priv(substream);
1013 struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream));
1014 long location;
1015
1016 location = (io->buff_offset - 1);
1017 if (location < 0)
1018 location = 0;
1019
1020 return bytes_to_frames(runtime, location);
1021 }
1022
1023 static struct snd_pcm_ops fsi_pcm_ops = {
1024 .open = fsi_pcm_open,
1025 .ioctl = snd_pcm_lib_ioctl,
1026 .hw_params = fsi_hw_params,
1027 .hw_free = fsi_hw_free,
1028 .pointer = fsi_pointer,
1029 };
1030
1031 /*
1032 * snd_soc_platform
1033 */
1034
1035 #define PREALLOC_BUFFER (32 * 1024)
1036 #define PREALLOC_BUFFER_MAX (32 * 1024)
1037
1038 static void fsi_pcm_free(struct snd_pcm *pcm)
1039 {
1040 snd_pcm_lib_preallocate_free_for_all(pcm);
1041 }
1042
1043 static int fsi_pcm_new(struct snd_card *card,
1044 struct snd_soc_dai *dai,
1045 struct snd_pcm *pcm)
1046 {
1047 /*
1048 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
1049 * in MMAP mode (i.e. aplay -M)
1050 */
1051 return snd_pcm_lib_preallocate_pages_for_all(
1052 pcm,
1053 SNDRV_DMA_TYPE_CONTINUOUS,
1054 snd_dma_continuous_data(GFP_KERNEL),
1055 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1056 }
1057
1058 /*
1059 * alsa struct
1060 */
1061
1062 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1063 {
1064 .name = "fsia-dai",
1065 .playback = {
1066 .rates = FSI_RATES,
1067 .formats = FSI_FMTS,
1068 .channels_min = 1,
1069 .channels_max = 8,
1070 },
1071 .capture = {
1072 .rates = FSI_RATES,
1073 .formats = FSI_FMTS,
1074 .channels_min = 1,
1075 .channels_max = 8,
1076 },
1077 .ops = &fsi_dai_ops,
1078 },
1079 {
1080 .name = "fsib-dai",
1081 .playback = {
1082 .rates = FSI_RATES,
1083 .formats = FSI_FMTS,
1084 .channels_min = 1,
1085 .channels_max = 8,
1086 },
1087 .capture = {
1088 .rates = FSI_RATES,
1089 .formats = FSI_FMTS,
1090 .channels_min = 1,
1091 .channels_max = 8,
1092 },
1093 .ops = &fsi_dai_ops,
1094 },
1095 };
1096
1097 static struct snd_soc_platform_driver fsi_soc_platform = {
1098 .ops = &fsi_pcm_ops,
1099 .pcm_new = fsi_pcm_new,
1100 .pcm_free = fsi_pcm_free,
1101 };
1102
1103 /*
1104 * platform function
1105 */
1106
1107 static int fsi_probe(struct platform_device *pdev)
1108 {
1109 struct fsi_master *master;
1110 const struct platform_device_id *id_entry;
1111 struct resource *res;
1112 unsigned int irq;
1113 int ret;
1114
1115 id_entry = pdev->id_entry;
1116 if (!id_entry) {
1117 dev_err(&pdev->dev, "unknown fsi device\n");
1118 return -ENODEV;
1119 }
1120
1121 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1122 irq = platform_get_irq(pdev, 0);
1123 if (!res || (int)irq <= 0) {
1124 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1125 ret = -ENODEV;
1126 goto exit;
1127 }
1128
1129 master = kzalloc(sizeof(*master), GFP_KERNEL);
1130 if (!master) {
1131 dev_err(&pdev->dev, "Could not allocate master\n");
1132 ret = -ENOMEM;
1133 goto exit;
1134 }
1135
1136 master->base = ioremap_nocache(res->start, resource_size(res));
1137 if (!master->base) {
1138 ret = -ENXIO;
1139 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1140 goto exit_kfree;
1141 }
1142
1143 /* master setting */
1144 master->irq = irq;
1145 master->info = pdev->dev.platform_data;
1146 master->core = (struct fsi_core *)id_entry->driver_data;
1147 spin_lock_init(&master->lock);
1148
1149 /* FSI A setting */
1150 master->fsia.base = master->base;
1151 master->fsia.master = master;
1152
1153 /* FSI B setting */
1154 master->fsib.base = master->base + 0x40;
1155 master->fsib.master = master;
1156
1157 pm_runtime_enable(&pdev->dev);
1158 pm_runtime_resume(&pdev->dev);
1159 dev_set_drvdata(&pdev->dev, master);
1160
1161 fsi_soft_all_reset(master);
1162
1163 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED,
1164 id_entry->name, master);
1165 if (ret) {
1166 dev_err(&pdev->dev, "irq request err\n");
1167 goto exit_iounmap;
1168 }
1169
1170 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
1171 if (ret < 0) {
1172 dev_err(&pdev->dev, "cannot snd soc register\n");
1173 goto exit_free_irq;
1174 }
1175
1176 return snd_soc_register_dais(&pdev->dev, fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
1177
1178 exit_free_irq:
1179 free_irq(irq, master);
1180 exit_iounmap:
1181 iounmap(master->base);
1182 pm_runtime_disable(&pdev->dev);
1183 exit_kfree:
1184 kfree(master);
1185 master = NULL;
1186 exit:
1187 return ret;
1188 }
1189
1190 static int fsi_remove(struct platform_device *pdev)
1191 {
1192 struct fsi_master *master;
1193
1194 master = dev_get_drvdata(&pdev->dev);
1195
1196 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
1197 snd_soc_unregister_platform(&pdev->dev);
1198
1199 pm_runtime_disable(&pdev->dev);
1200
1201 free_irq(master->irq, master);
1202
1203 iounmap(master->base);
1204 kfree(master);
1205
1206 return 0;
1207 }
1208
1209 static int fsi_runtime_nop(struct device *dev)
1210 {
1211 /* Runtime PM callback shared between ->runtime_suspend()
1212 * and ->runtime_resume(). Simply returns success.
1213 *
1214 * This driver re-initializes all registers after
1215 * pm_runtime_get_sync() anyway so there is no need
1216 * to save and restore registers here.
1217 */
1218 return 0;
1219 }
1220
1221 static struct dev_pm_ops fsi_pm_ops = {
1222 .runtime_suspend = fsi_runtime_nop,
1223 .runtime_resume = fsi_runtime_nop,
1224 };
1225
1226 static struct fsi_core fsi1_core = {
1227 .ver = 1,
1228
1229 /* Interrupt */
1230 .int_st = INT_ST,
1231 .iemsk = IEMSK,
1232 .imsk = IMSK,
1233 };
1234
1235 static struct fsi_core fsi2_core = {
1236 .ver = 2,
1237
1238 /* Interrupt */
1239 .int_st = CPU_INT_ST,
1240 .iemsk = CPU_IEMSK,
1241 .imsk = CPU_IMSK,
1242 .a_mclk = A_MST_CTLR,
1243 .b_mclk = B_MST_CTLR,
1244 };
1245
1246 static struct platform_device_id fsi_id_table[] = {
1247 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1248 { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
1249 {},
1250 };
1251 MODULE_DEVICE_TABLE(platform, fsi_id_table);
1252
1253 static struct platform_driver fsi_driver = {
1254 .driver = {
1255 .name = "fsi-pcm-audio",
1256 .pm = &fsi_pm_ops,
1257 },
1258 .probe = fsi_probe,
1259 .remove = fsi_remove,
1260 .id_table = fsi_id_table,
1261 };
1262
1263 static int __init fsi_mobile_init(void)
1264 {
1265 return platform_driver_register(&fsi_driver);
1266 }
1267
1268 static void __exit fsi_mobile_exit(void)
1269 {
1270 platform_driver_unregister(&fsi_driver);
1271 }
1272
1273 module_init(fsi_mobile_init);
1274 module_exit(fsi_mobile_exit);
1275
1276 MODULE_LICENSE("GPL");
1277 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1278 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
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