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Merge branch 'for-next' into for-linus
[mirror_ubuntu-zesty-kernel.git] / sound / soc / sh / fsi.c
1 /*
2 * Fifo-attached Serial Interface (FSI) support for SH7724
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ssi.c
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/delay.h>
19 #include <linux/list.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/io.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/initval.h>
25 #include <sound/soc.h>
26 #include <sound/pcm_params.h>
27 #include <sound/sh_fsi.h>
28 #include <asm/atomic.h>
29
30 #define DO_FMT 0x0000
31 #define DOFF_CTL 0x0004
32 #define DOFF_ST 0x0008
33 #define DI_FMT 0x000C
34 #define DIFF_CTL 0x0010
35 #define DIFF_ST 0x0014
36 #define CKG1 0x0018
37 #define CKG2 0x001C
38 #define DIDT 0x0020
39 #define DODT 0x0024
40 #define MUTE_ST 0x0028
41 #define REG_END MUTE_ST
42
43 #define INT_ST 0x0200
44 #define IEMSK 0x0204
45 #define IMSK 0x0208
46 #define MUTE 0x020C
47 #define CLK_RST 0x0210
48 #define SOFT_RST 0x0214
49 #define MREG_START INT_ST
50 #define MREG_END SOFT_RST
51
52 /* DO_FMT */
53 /* DI_FMT */
54 #define CR_FMT(param) ((param) << 4)
55 # define CR_MONO 0x0
56 # define CR_MONO_D 0x1
57 # define CR_PCM 0x2
58 # define CR_I2S 0x3
59 # define CR_TDM 0x4
60 # define CR_TDM_D 0x5
61
62 /* DOFF_CTL */
63 /* DIFF_CTL */
64 #define IRQ_HALF 0x00100000
65 #define FIFO_CLR 0x00000001
66
67 /* DOFF_ST */
68 #define ERR_OVER 0x00000010
69 #define ERR_UNDER 0x00000001
70 #define ST_ERR (ERR_OVER | ERR_UNDER)
71
72 /* CLK_RST */
73 #define B_CLK 0x00000010
74 #define A_CLK 0x00000001
75
76 /* INT_ST */
77 #define INT_B_IN (1 << 12)
78 #define INT_B_OUT (1 << 8)
79 #define INT_A_IN (1 << 4)
80 #define INT_A_OUT (1 << 0)
81
82 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
83
84 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
85
86 /************************************************************************
87
88
89 struct
90
91
92 ************************************************************************/
93 struct fsi_priv {
94 void __iomem *base;
95 struct snd_pcm_substream *substream;
96 struct fsi_master *master;
97
98 int fifo_max;
99 int chan;
100
101 int byte_offset;
102 int period_len;
103 int buffer_len;
104 int periods;
105 };
106
107 struct fsi_master {
108 void __iomem *base;
109 int irq;
110 struct fsi_priv fsia;
111 struct fsi_priv fsib;
112 struct sh_fsi_platform_info *info;
113 spinlock_t lock;
114 };
115
116 /************************************************************************
117
118
119 basic read write function
120
121
122 ************************************************************************/
123 static void __fsi_reg_write(u32 reg, u32 data)
124 {
125 /* valid data area is 24bit */
126 data &= 0x00ffffff;
127
128 __raw_writel(data, reg);
129 }
130
131 static u32 __fsi_reg_read(u32 reg)
132 {
133 return __raw_readl(reg);
134 }
135
136 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
137 {
138 u32 val = __fsi_reg_read(reg);
139
140 val &= ~mask;
141 val |= data & mask;
142
143 __fsi_reg_write(reg, val);
144 }
145
146 static void fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data)
147 {
148 if (reg > REG_END)
149 return;
150
151 __fsi_reg_write((u32)(fsi->base + reg), data);
152 }
153
154 static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg)
155 {
156 if (reg > REG_END)
157 return 0;
158
159 return __fsi_reg_read((u32)(fsi->base + reg));
160 }
161
162 static void fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data)
163 {
164 if (reg > REG_END)
165 return;
166
167 __fsi_reg_mask_set((u32)(fsi->base + reg), mask, data);
168 }
169
170 static void fsi_master_write(struct fsi_master *master, u32 reg, u32 data)
171 {
172 unsigned long flags;
173
174 if ((reg < MREG_START) ||
175 (reg > MREG_END))
176 return;
177
178 spin_lock_irqsave(&master->lock, flags);
179 __fsi_reg_write((u32)(master->base + reg), data);
180 spin_unlock_irqrestore(&master->lock, flags);
181 }
182
183 static u32 fsi_master_read(struct fsi_master *master, u32 reg)
184 {
185 u32 ret;
186 unsigned long flags;
187
188 if ((reg < MREG_START) ||
189 (reg > MREG_END))
190 return 0;
191
192 spin_lock_irqsave(&master->lock, flags);
193 ret = __fsi_reg_read((u32)(master->base + reg));
194 spin_unlock_irqrestore(&master->lock, flags);
195
196 return ret;
197 }
198
199 static void fsi_master_mask_set(struct fsi_master *master,
200 u32 reg, u32 mask, u32 data)
201 {
202 unsigned long flags;
203
204 if ((reg < MREG_START) ||
205 (reg > MREG_END))
206 return;
207
208 spin_lock_irqsave(&master->lock, flags);
209 __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
210 spin_unlock_irqrestore(&master->lock, flags);
211 }
212
213 /************************************************************************
214
215
216 basic function
217
218
219 ************************************************************************/
220 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
221 {
222 return fsi->master;
223 }
224
225 static int fsi_is_port_a(struct fsi_priv *fsi)
226 {
227 return fsi->master->base == fsi->base;
228 }
229
230 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
231 {
232 struct snd_soc_pcm_runtime *rtd = substream->private_data;
233 struct snd_soc_dai_link *machine = rtd->dai;
234
235 return machine->cpu_dai;
236 }
237
238 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
239 {
240 struct snd_soc_dai *dai = fsi_get_dai(substream);
241
242 return dai->private_data;
243 }
244
245 static u32 fsi_get_info_flags(struct fsi_priv *fsi)
246 {
247 int is_porta = fsi_is_port_a(fsi);
248 struct fsi_master *master = fsi_get_master(fsi);
249
250 return is_porta ? master->info->porta_flags :
251 master->info->portb_flags;
252 }
253
254 static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play)
255 {
256 u32 mode;
257 u32 flags = fsi_get_info_flags(fsi);
258
259 mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE;
260
261 /* return
262 * 1 : master mode
263 * 0 : slave mode
264 */
265
266 return (mode & flags) != mode;
267 }
268
269 static u32 fsi_port_ab_io_bit(struct fsi_priv *fsi, int is_play)
270 {
271 int is_porta = fsi_is_port_a(fsi);
272 u32 data;
273
274 if (is_porta)
275 data = is_play ? (1 << 0) : (1 << 4);
276 else
277 data = is_play ? (1 << 8) : (1 << 12);
278
279 return data;
280 }
281
282 static void fsi_stream_push(struct fsi_priv *fsi,
283 struct snd_pcm_substream *substream,
284 u32 buffer_len,
285 u32 period_len)
286 {
287 fsi->substream = substream;
288 fsi->buffer_len = buffer_len;
289 fsi->period_len = period_len;
290 fsi->byte_offset = 0;
291 fsi->periods = 0;
292 }
293
294 static void fsi_stream_pop(struct fsi_priv *fsi)
295 {
296 fsi->substream = NULL;
297 fsi->buffer_len = 0;
298 fsi->period_len = 0;
299 fsi->byte_offset = 0;
300 fsi->periods = 0;
301 }
302
303 static int fsi_get_fifo_residue(struct fsi_priv *fsi, int is_play)
304 {
305 u32 status;
306 u32 reg = is_play ? DOFF_ST : DIFF_ST;
307 int residue;
308
309 status = fsi_reg_read(fsi, reg);
310 residue = 0x1ff & (status >> 8);
311 residue *= fsi->chan;
312
313 return residue;
314 }
315
316 /************************************************************************
317
318
319 ctrl function
320
321
322 ************************************************************************/
323 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
324 {
325 u32 data = fsi_port_ab_io_bit(fsi, is_play);
326 struct fsi_master *master = fsi_get_master(fsi);
327
328 fsi_master_mask_set(master, IMSK, data, data);
329 fsi_master_mask_set(master, IEMSK, data, data);
330 }
331
332 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
333 {
334 u32 data = fsi_port_ab_io_bit(fsi, is_play);
335 struct fsi_master *master = fsi_get_master(fsi);
336
337 fsi_master_mask_set(master, IMSK, data, 0);
338 fsi_master_mask_set(master, IEMSK, data, 0);
339 }
340
341 static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable)
342 {
343 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4);
344 struct fsi_master *master = fsi_get_master(fsi);
345
346 if (enable)
347 fsi_master_mask_set(master, CLK_RST, val, val);
348 else
349 fsi_master_mask_set(master, CLK_RST, val, 0);
350 }
351
352 static void fsi_irq_init(struct fsi_priv *fsi, int is_play)
353 {
354 u32 data;
355 u32 ctrl;
356
357 data = fsi_port_ab_io_bit(fsi, is_play);
358 ctrl = is_play ? DOFF_CTL : DIFF_CTL;
359
360 /* set IMSK */
361 fsi_irq_disable(fsi, is_play);
362
363 /* set interrupt generation factor */
364 fsi_reg_write(fsi, ctrl, IRQ_HALF);
365
366 /* clear FIFO */
367 fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR);
368
369 /* clear interrupt factor */
370 fsi_master_mask_set(fsi_get_master(fsi), INT_ST, data, 0);
371 }
372
373 static void fsi_soft_all_reset(struct fsi_master *master)
374 {
375 u32 status = fsi_master_read(master, SOFT_RST);
376
377 /* port AB reset */
378 status &= 0x000000ff;
379 fsi_master_write(master, SOFT_RST, status);
380 mdelay(10);
381
382 /* soft reset */
383 status &= 0x000000f0;
384 fsi_master_write(master, SOFT_RST, status);
385 status |= 0x00000001;
386 fsi_master_write(master, SOFT_RST, status);
387 mdelay(10);
388 }
389
390 /* playback interrupt */
391 static int fsi_data_push(struct fsi_priv *fsi, int startup)
392 {
393 struct snd_pcm_runtime *runtime;
394 struct snd_pcm_substream *substream = NULL;
395 u32 status;
396 int send;
397 int fifo_free;
398 int width;
399 u8 *start;
400 int i, over_period;
401
402 if (!fsi ||
403 !fsi->substream ||
404 !fsi->substream->runtime)
405 return -EINVAL;
406
407 over_period = 0;
408 substream = fsi->substream;
409 runtime = substream->runtime;
410
411 /* FSI FIFO has limit.
412 * So, this driver can not send periods data at a time
413 */
414 if (fsi->byte_offset >=
415 fsi->period_len * (fsi->periods + 1)) {
416
417 over_period = 1;
418 fsi->periods = (fsi->periods + 1) % runtime->periods;
419
420 if (0 == fsi->periods)
421 fsi->byte_offset = 0;
422 }
423
424 /* get 1 channel data width */
425 width = frames_to_bytes(runtime, 1) / fsi->chan;
426
427 /* get send size for alsa */
428 send = (fsi->buffer_len - fsi->byte_offset) / width;
429
430 /* get FIFO free size */
431 fifo_free = (fsi->fifo_max * fsi->chan) - fsi_get_fifo_residue(fsi, 1);
432
433 /* size check */
434 if (fifo_free < send)
435 send = fifo_free;
436
437 start = runtime->dma_area;
438 start += fsi->byte_offset;
439
440 switch (width) {
441 case 2:
442 for (i = 0; i < send; i++)
443 fsi_reg_write(fsi, DODT,
444 ((u32)*((u16 *)start + i) << 8));
445 break;
446 case 4:
447 for (i = 0; i < send; i++)
448 fsi_reg_write(fsi, DODT, *((u32 *)start + i));
449 break;
450 default:
451 return -EINVAL;
452 }
453
454 fsi->byte_offset += send * width;
455
456 status = fsi_reg_read(fsi, DOFF_ST);
457 if (!startup) {
458 struct snd_soc_dai *dai = fsi_get_dai(substream);
459
460 if (status & ERR_OVER)
461 dev_err(dai->dev, "over run\n");
462 if (status & ERR_UNDER)
463 dev_err(dai->dev, "under run\n");
464 }
465 fsi_reg_write(fsi, DOFF_ST, 0);
466
467 fsi_irq_enable(fsi, 1);
468
469 if (over_period)
470 snd_pcm_period_elapsed(substream);
471
472 return 0;
473 }
474
475 static int fsi_data_pop(struct fsi_priv *fsi, int startup)
476 {
477 struct snd_pcm_runtime *runtime;
478 struct snd_pcm_substream *substream = NULL;
479 u32 status;
480 int free;
481 int fifo_fill;
482 int width;
483 u8 *start;
484 int i, over_period;
485
486 if (!fsi ||
487 !fsi->substream ||
488 !fsi->substream->runtime)
489 return -EINVAL;
490
491 over_period = 0;
492 substream = fsi->substream;
493 runtime = substream->runtime;
494
495 /* FSI FIFO has limit.
496 * So, this driver can not send periods data at a time
497 */
498 if (fsi->byte_offset >=
499 fsi->period_len * (fsi->periods + 1)) {
500
501 over_period = 1;
502 fsi->periods = (fsi->periods + 1) % runtime->periods;
503
504 if (0 == fsi->periods)
505 fsi->byte_offset = 0;
506 }
507
508 /* get 1 channel data width */
509 width = frames_to_bytes(runtime, 1) / fsi->chan;
510
511 /* get free space for alsa */
512 free = (fsi->buffer_len - fsi->byte_offset) / width;
513
514 /* get recv size */
515 fifo_fill = fsi_get_fifo_residue(fsi, 0);
516
517 if (free < fifo_fill)
518 fifo_fill = free;
519
520 start = runtime->dma_area;
521 start += fsi->byte_offset;
522
523 switch (width) {
524 case 2:
525 for (i = 0; i < fifo_fill; i++)
526 *((u16 *)start + i) =
527 (u16)(fsi_reg_read(fsi, DIDT) >> 8);
528 break;
529 case 4:
530 for (i = 0; i < fifo_fill; i++)
531 *((u32 *)start + i) = fsi_reg_read(fsi, DIDT);
532 break;
533 default:
534 return -EINVAL;
535 }
536
537 fsi->byte_offset += fifo_fill * width;
538
539 status = fsi_reg_read(fsi, DIFF_ST);
540 if (!startup) {
541 struct snd_soc_dai *dai = fsi_get_dai(substream);
542
543 if (status & ERR_OVER)
544 dev_err(dai->dev, "over run\n");
545 if (status & ERR_UNDER)
546 dev_err(dai->dev, "under run\n");
547 }
548 fsi_reg_write(fsi, DIFF_ST, 0);
549
550 fsi_irq_enable(fsi, 0);
551
552 if (over_period)
553 snd_pcm_period_elapsed(substream);
554
555 return 0;
556 }
557
558 static irqreturn_t fsi_interrupt(int irq, void *data)
559 {
560 struct fsi_master *master = data;
561 u32 status = fsi_master_read(master, SOFT_RST) & ~0x00000010;
562 u32 int_st = fsi_master_read(master, INT_ST);
563
564 /* clear irq status */
565 fsi_master_write(master, SOFT_RST, status);
566 fsi_master_write(master, SOFT_RST, status | 0x00000010);
567
568 if (int_st & INT_A_OUT)
569 fsi_data_push(&master->fsia, 0);
570 if (int_st & INT_B_OUT)
571 fsi_data_push(&master->fsib, 0);
572 if (int_st & INT_A_IN)
573 fsi_data_pop(&master->fsia, 0);
574 if (int_st & INT_B_IN)
575 fsi_data_pop(&master->fsib, 0);
576
577 fsi_master_write(master, INT_ST, 0x0000000);
578
579 return IRQ_HANDLED;
580 }
581
582 /************************************************************************
583
584
585 dai ops
586
587
588 ************************************************************************/
589 static int fsi_dai_startup(struct snd_pcm_substream *substream,
590 struct snd_soc_dai *dai)
591 {
592 struct fsi_priv *fsi = fsi_get_priv(substream);
593 const char *msg;
594 u32 flags = fsi_get_info_flags(fsi);
595 u32 fmt;
596 u32 reg;
597 u32 data;
598 int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
599 int is_master;
600 int ret = 0;
601
602 pm_runtime_get_sync(dai->dev);
603
604 /* CKG1 */
605 data = is_play ? (1 << 0) : (1 << 4);
606 is_master = fsi_is_master_mode(fsi, is_play);
607 if (is_master)
608 fsi_reg_mask_set(fsi, CKG1, data, data);
609 else
610 fsi_reg_mask_set(fsi, CKG1, data, 0);
611
612 /* clock inversion (CKG2) */
613 data = 0;
614 switch (SH_FSI_INVERSION_MASK & flags) {
615 case SH_FSI_LRM_INV:
616 data = 1 << 12;
617 break;
618 case SH_FSI_BRM_INV:
619 data = 1 << 8;
620 break;
621 case SH_FSI_LRS_INV:
622 data = 1 << 4;
623 break;
624 case SH_FSI_BRS_INV:
625 data = 1 << 0;
626 break;
627 }
628 fsi_reg_write(fsi, CKG2, data);
629
630 /* do fmt, di fmt */
631 data = 0;
632 reg = is_play ? DO_FMT : DI_FMT;
633 fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags);
634 switch (fmt) {
635 case SH_FSI_FMT_MONO:
636 msg = "MONO";
637 data = CR_FMT(CR_MONO);
638 fsi->chan = 1;
639 break;
640 case SH_FSI_FMT_MONO_DELAY:
641 msg = "MONO Delay";
642 data = CR_FMT(CR_MONO_D);
643 fsi->chan = 1;
644 break;
645 case SH_FSI_FMT_PCM:
646 msg = "PCM";
647 data = CR_FMT(CR_PCM);
648 fsi->chan = 2;
649 break;
650 case SH_FSI_FMT_I2S:
651 msg = "I2S";
652 data = CR_FMT(CR_I2S);
653 fsi->chan = 2;
654 break;
655 case SH_FSI_FMT_TDM:
656 msg = "TDM";
657 data = CR_FMT(CR_TDM) | (fsi->chan - 1);
658 fsi->chan = is_play ?
659 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
660 break;
661 case SH_FSI_FMT_TDM_DELAY:
662 msg = "TDM Delay";
663 data = CR_FMT(CR_TDM_D) | (fsi->chan - 1);
664 fsi->chan = is_play ?
665 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
666 break;
667 default:
668 dev_err(dai->dev, "unknown format.\n");
669 return -EINVAL;
670 }
671
672 switch (fsi->chan) {
673 case 1:
674 fsi->fifo_max = 256;
675 break;
676 case 2:
677 fsi->fifo_max = 128;
678 break;
679 case 3:
680 case 4:
681 fsi->fifo_max = 64;
682 break;
683 case 5:
684 case 6:
685 case 7:
686 case 8:
687 fsi->fifo_max = 32;
688 break;
689 default:
690 dev_err(dai->dev, "channel size error.\n");
691 return -EINVAL;
692 }
693
694 fsi_reg_write(fsi, reg, data);
695
696 /*
697 * clear clk reset if master mode
698 */
699 if (is_master)
700 fsi_clk_ctrl(fsi, 1);
701
702 /* irq setting */
703 fsi_irq_init(fsi, is_play);
704
705 return ret;
706 }
707
708 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
709 struct snd_soc_dai *dai)
710 {
711 struct fsi_priv *fsi = fsi_get_priv(substream);
712 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
713
714 fsi_irq_disable(fsi, is_play);
715 fsi_clk_ctrl(fsi, 0);
716
717 pm_runtime_put_sync(dai->dev);
718 }
719
720 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
721 struct snd_soc_dai *dai)
722 {
723 struct fsi_priv *fsi = fsi_get_priv(substream);
724 struct snd_pcm_runtime *runtime = substream->runtime;
725 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
726 int ret = 0;
727
728 switch (cmd) {
729 case SNDRV_PCM_TRIGGER_START:
730 fsi_stream_push(fsi, substream,
731 frames_to_bytes(runtime, runtime->buffer_size),
732 frames_to_bytes(runtime, runtime->period_size));
733 ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1);
734 break;
735 case SNDRV_PCM_TRIGGER_STOP:
736 fsi_irq_disable(fsi, is_play);
737 fsi_stream_pop(fsi);
738 break;
739 }
740
741 return ret;
742 }
743
744 static struct snd_soc_dai_ops fsi_dai_ops = {
745 .startup = fsi_dai_startup,
746 .shutdown = fsi_dai_shutdown,
747 .trigger = fsi_dai_trigger,
748 };
749
750 /************************************************************************
751
752
753 pcm ops
754
755
756 ************************************************************************/
757 static struct snd_pcm_hardware fsi_pcm_hardware = {
758 .info = SNDRV_PCM_INFO_INTERLEAVED |
759 SNDRV_PCM_INFO_MMAP |
760 SNDRV_PCM_INFO_MMAP_VALID |
761 SNDRV_PCM_INFO_PAUSE,
762 .formats = FSI_FMTS,
763 .rates = FSI_RATES,
764 .rate_min = 8000,
765 .rate_max = 192000,
766 .channels_min = 1,
767 .channels_max = 2,
768 .buffer_bytes_max = 64 * 1024,
769 .period_bytes_min = 32,
770 .period_bytes_max = 8192,
771 .periods_min = 1,
772 .periods_max = 32,
773 .fifo_size = 256,
774 };
775
776 static int fsi_pcm_open(struct snd_pcm_substream *substream)
777 {
778 struct snd_pcm_runtime *runtime = substream->runtime;
779 int ret = 0;
780
781 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
782
783 ret = snd_pcm_hw_constraint_integer(runtime,
784 SNDRV_PCM_HW_PARAM_PERIODS);
785
786 return ret;
787 }
788
789 static int fsi_hw_params(struct snd_pcm_substream *substream,
790 struct snd_pcm_hw_params *hw_params)
791 {
792 return snd_pcm_lib_malloc_pages(substream,
793 params_buffer_bytes(hw_params));
794 }
795
796 static int fsi_hw_free(struct snd_pcm_substream *substream)
797 {
798 return snd_pcm_lib_free_pages(substream);
799 }
800
801 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
802 {
803 struct snd_pcm_runtime *runtime = substream->runtime;
804 struct fsi_priv *fsi = fsi_get_priv(substream);
805 long location;
806
807 location = (fsi->byte_offset - 1);
808 if (location < 0)
809 location = 0;
810
811 return bytes_to_frames(runtime, location);
812 }
813
814 static struct snd_pcm_ops fsi_pcm_ops = {
815 .open = fsi_pcm_open,
816 .ioctl = snd_pcm_lib_ioctl,
817 .hw_params = fsi_hw_params,
818 .hw_free = fsi_hw_free,
819 .pointer = fsi_pointer,
820 };
821
822 /************************************************************************
823
824
825 snd_soc_platform
826
827
828 ************************************************************************/
829 #define PREALLOC_BUFFER (32 * 1024)
830 #define PREALLOC_BUFFER_MAX (32 * 1024)
831
832 static void fsi_pcm_free(struct snd_pcm *pcm)
833 {
834 snd_pcm_lib_preallocate_free_for_all(pcm);
835 }
836
837 static int fsi_pcm_new(struct snd_card *card,
838 struct snd_soc_dai *dai,
839 struct snd_pcm *pcm)
840 {
841 /*
842 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
843 * in MMAP mode (i.e. aplay -M)
844 */
845 return snd_pcm_lib_preallocate_pages_for_all(
846 pcm,
847 SNDRV_DMA_TYPE_CONTINUOUS,
848 snd_dma_continuous_data(GFP_KERNEL),
849 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
850 }
851
852 /************************************************************************
853
854
855 alsa struct
856
857
858 ************************************************************************/
859 struct snd_soc_dai fsi_soc_dai[] = {
860 {
861 .name = "FSIA",
862 .id = 0,
863 .playback = {
864 .rates = FSI_RATES,
865 .formats = FSI_FMTS,
866 .channels_min = 1,
867 .channels_max = 8,
868 },
869 .capture = {
870 .rates = FSI_RATES,
871 .formats = FSI_FMTS,
872 .channels_min = 1,
873 .channels_max = 8,
874 },
875 .ops = &fsi_dai_ops,
876 },
877 {
878 .name = "FSIB",
879 .id = 1,
880 .playback = {
881 .rates = FSI_RATES,
882 .formats = FSI_FMTS,
883 .channels_min = 1,
884 .channels_max = 8,
885 },
886 .capture = {
887 .rates = FSI_RATES,
888 .formats = FSI_FMTS,
889 .channels_min = 1,
890 .channels_max = 8,
891 },
892 .ops = &fsi_dai_ops,
893 },
894 };
895 EXPORT_SYMBOL_GPL(fsi_soc_dai);
896
897 struct snd_soc_platform fsi_soc_platform = {
898 .name = "fsi-pcm",
899 .pcm_ops = &fsi_pcm_ops,
900 .pcm_new = fsi_pcm_new,
901 .pcm_free = fsi_pcm_free,
902 };
903 EXPORT_SYMBOL_GPL(fsi_soc_platform);
904
905 /************************************************************************
906
907
908 platform function
909
910
911 ************************************************************************/
912 static int fsi_probe(struct platform_device *pdev)
913 {
914 struct fsi_master *master;
915 struct resource *res;
916 unsigned int irq;
917 int ret;
918
919 if (0 != pdev->id) {
920 dev_err(&pdev->dev, "current fsi support id 0 only now\n");
921 return -ENODEV;
922 }
923
924 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
925 irq = platform_get_irq(pdev, 0);
926 if (!res || (int)irq <= 0) {
927 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
928 ret = -ENODEV;
929 goto exit;
930 }
931
932 master = kzalloc(sizeof(*master), GFP_KERNEL);
933 if (!master) {
934 dev_err(&pdev->dev, "Could not allocate master\n");
935 ret = -ENOMEM;
936 goto exit;
937 }
938
939 master->base = ioremap_nocache(res->start, resource_size(res));
940 if (!master->base) {
941 ret = -ENXIO;
942 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
943 goto exit_kfree;
944 }
945
946 master->irq = irq;
947 master->info = pdev->dev.platform_data;
948 master->fsia.base = master->base;
949 master->fsia.master = master;
950 master->fsib.base = master->base + 0x40;
951 master->fsib.master = master;
952 spin_lock_init(&master->lock);
953
954 pm_runtime_enable(&pdev->dev);
955 pm_runtime_resume(&pdev->dev);
956
957 fsi_soc_dai[0].dev = &pdev->dev;
958 fsi_soc_dai[0].private_data = &master->fsia;
959 fsi_soc_dai[1].dev = &pdev->dev;
960 fsi_soc_dai[1].private_data = &master->fsib;
961
962 fsi_soft_all_reset(master);
963
964 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED, "fsi", master);
965 if (ret) {
966 dev_err(&pdev->dev, "irq request err\n");
967 goto exit_iounmap;
968 }
969
970 ret = snd_soc_register_platform(&fsi_soc_platform);
971 if (ret < 0) {
972 dev_err(&pdev->dev, "cannot snd soc register\n");
973 goto exit_free_irq;
974 }
975
976 return snd_soc_register_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
977
978 exit_free_irq:
979 free_irq(irq, master);
980 exit_iounmap:
981 iounmap(master->base);
982 pm_runtime_disable(&pdev->dev);
983 exit_kfree:
984 kfree(master);
985 master = NULL;
986 exit:
987 return ret;
988 }
989
990 static int fsi_remove(struct platform_device *pdev)
991 {
992 struct fsi_master *master;
993
994 master = fsi_get_master(fsi_soc_dai[0].private_data);
995
996 snd_soc_unregister_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
997 snd_soc_unregister_platform(&fsi_soc_platform);
998
999 pm_runtime_disable(&pdev->dev);
1000
1001 free_irq(master->irq, master);
1002
1003 iounmap(master->base);
1004 kfree(master);
1005
1006 fsi_soc_dai[0].dev = NULL;
1007 fsi_soc_dai[0].private_data = NULL;
1008 fsi_soc_dai[1].dev = NULL;
1009 fsi_soc_dai[1].private_data = NULL;
1010
1011 return 0;
1012 }
1013
1014 static int fsi_runtime_nop(struct device *dev)
1015 {
1016 /* Runtime PM callback shared between ->runtime_suspend()
1017 * and ->runtime_resume(). Simply returns success.
1018 *
1019 * This driver re-initializes all registers after
1020 * pm_runtime_get_sync() anyway so there is no need
1021 * to save and restore registers here.
1022 */
1023 return 0;
1024 }
1025
1026 static struct dev_pm_ops fsi_pm_ops = {
1027 .runtime_suspend = fsi_runtime_nop,
1028 .runtime_resume = fsi_runtime_nop,
1029 };
1030
1031 static struct platform_driver fsi_driver = {
1032 .driver = {
1033 .name = "sh_fsi",
1034 .pm = &fsi_pm_ops,
1035 },
1036 .probe = fsi_probe,
1037 .remove = fsi_remove,
1038 };
1039
1040 static int __init fsi_mobile_init(void)
1041 {
1042 return platform_driver_register(&fsi_driver);
1043 }
1044
1045 static void __exit fsi_mobile_exit(void)
1046 {
1047 platform_driver_unregister(&fsi_driver);
1048 }
1049 module_init(fsi_mobile_init);
1050 module_exit(fsi_mobile_exit);
1051
1052 MODULE_LICENSE("GPL");
1053 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1054 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
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