sound/soc/sh/rcar/adg.c

   1 /*
   2  * Helper routines for R-Car sound ADG.
   3  *
   4  *  Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/clk-provider.h>
  11 #include "rsnd.h"
  12
  13 #define CLKA    0
  14 #define CLKB    1
  15 #define CLKC    2
  16 #define CLKI    3
  17 #define CLKMAX  4
  18
  19 #define CLKOUT  0
  20 #define CLKOUT1 1
  21 #define CLKOUT2 2
  22 #define CLKOUT3 3
  23 #define CLKOUTMAX 4
  24
  25 #define BRRx_MASK(x) (0x3FF & x)
  26
  27 static struct rsnd_mod_ops adg_ops = {
  28         .name = "adg",
  29 };
  30
  31 struct rsnd_adg {
  32         struct clk *clk[CLKMAX];
  33         struct clk *clkout[CLKOUTMAX];
  34         struct clk_onecell_data onecell;
  35         struct rsnd_mod mod;
  36
  37         int rbga_rate_for_441khz; /* RBGA */
  38         int rbgb_rate_for_48khz;  /* RBGB */
  39 };
  40
  41 #define for_each_rsnd_clk(pos, adg, i)          \
  42         for (i = 0;                             \
  43              (i < CLKMAX) &&                    \
  44              ((pos) = adg->clk[i]);             \
  45              i++)
  46 #define for_each_rsnd_clkout(pos, adg, i)       \
  47         for (i = 0;                             \
  48              (i < CLKOUTMAX) &&                 \
  49              ((pos) = adg->clkout[i]);  \
  50              i++)
  51 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
  52
  53 static u32 rsnd_adg_calculate_rbgx(unsigned long div)
  54 {
  55         int i, ratio;
  56
  57         if (!div)
  58                 return 0;
  59
  60         for (i = 3; i >= 0; i--) {
  61                 ratio = 2 << (i * 2);
  62                 if (0 == (div % ratio))
  63                         return (u32)((i << 8) | ((div / ratio) - 1));
  64         }
  65
  66         return ~0;
  67 }
  68
  69 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
  70 {
  71         struct rsnd_mod *mod = rsnd_io_to_mod_ssi(io);
  72         int id = rsnd_mod_id(mod);
  73         int ws = id;
  74
  75         if (rsnd_ssi_is_pin_sharing(io)) {
  76                 switch (id) {
  77                 case 1:
  78                 case 2:
  79                         ws = 0;
  80                         break;
  81                 case 4:
  82                         ws = 3;
  83                         break;
  84                 case 8:
  85                         ws = 7;
  86                         break;
  87                 }
  88         }
  89
  90         return (0x6 + ws) << 8;
  91 }
  92
  93 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *mod,
  94                                  struct rsnd_dai_stream *io)
  95 {
  96         struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
  97         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
  98         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
  99         int id = rsnd_mod_id(mod);
 100         int shift = (id % 2) ? 16 : 0;
 101         u32 mask, val;
 102
 103         val = rsnd_adg_ssi_ws_timing_gen2(io);
 104
 105         val  = val      << shift;
 106         mask = 0xffff   << shift;
 107
 108         rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
 109
 110         return 0;
 111 }
 112
 113 static int rsnd_adg_set_src_timsel_gen2(struct rsnd_mod *src_mod,
 114                                         struct rsnd_dai_stream *io,
 115                                         u32 timsel)
 116 {
 117         struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
 118         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 119         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 120         int is_play = rsnd_io_is_play(io);
 121         int id = rsnd_mod_id(src_mod);
 122         int shift = (id % 2) ? 16 : 0;
 123         u32 mask, ws;
 124         u32 in, out;
 125
 126         rsnd_mod_confirm_src(src_mod);
 127
 128         ws = rsnd_adg_ssi_ws_timing_gen2(io);
 129
 130         in  = (is_play) ? timsel : ws;
 131         out = (is_play) ? ws     : timsel;
 132
 133         in   = in       << shift;
 134         out  = out      << shift;
 135         mask = 0xffff   << shift;
 136
 137         switch (id / 2) {
 138         case 0:
 139                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0,  mask, in);
 140                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out);
 141                 break;
 142         case 1:
 143                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1,  mask, in);
 144                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out);
 145                 break;
 146         case 2:
 147                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2,  mask, in);
 148                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out);
 149                 break;
 150         case 3:
 151                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3,  mask, in);
 152                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out);
 153                 break;
 154         case 4:
 155                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4,  mask, in);
 156                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out);
 157                 break;
 158         }
 159
 160         return 0;
 161 }
 162
 163 int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *src_mod,
 164                                   struct rsnd_dai_stream *io,
 165                                   unsigned int src_rate,
 166                                   unsigned int dst_rate)
 167 {
 168         struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
 169         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 170         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 171         struct device *dev = rsnd_priv_to_dev(priv);
 172         int idx, sel, div, step, ret;
 173         u32 val, en;
 174         unsigned int min, diff;
 175         unsigned int sel_rate [] = {
 176                 clk_get_rate(adg->clk[CLKA]),   /* 0000: CLKA */
 177                 clk_get_rate(adg->clk[CLKB]),   /* 0001: CLKB */
 178                 clk_get_rate(adg->clk[CLKC]),   /* 0010: CLKC */
 179                 adg->rbga_rate_for_441khz,      /* 0011: RBGA */
 180                 adg->rbgb_rate_for_48khz,       /* 0100: RBGB */
 181         };
 182
 183         rsnd_mod_confirm_src(src_mod);
 184
 185         min = ~0;
 186         val = 0;
 187         en = 0;
 188         for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
 189                 idx = 0;
 190                 step = 2;
 191
 192                 if (!sel_rate[sel])
 193                         continue;
 194
 195                 for (div = 2; div <= 98304; div += step) {
 196                         diff = abs(src_rate - sel_rate[sel] / div);
 197                         if (min > diff) {
 198                                 val = (sel << 8) | idx;
 199                                 min = diff;
 200                                 en = 1 << (sel + 1); /* fixme */
 201                         }
 202
 203                         /*
 204                          * step of 0_0000 / 0_0001 / 0_1101
 205                          * are out of order
 206                          */
 207                         if ((idx > 2) && (idx % 2))
 208                                 step *= 2;
 209                         if (idx == 0x1c) {
 210                                 div += step;
 211                                 step *= 2;
 212                         }
 213                         idx++;
 214                 }
 215         }
 216
 217         if (min == ~0) {
 218                 dev_err(dev, "no Input clock\n");
 219                 return -EIO;
 220         }
 221
 222         ret = rsnd_adg_set_src_timsel_gen2(src_mod, io, val);
 223         if (ret < 0) {
 224                 dev_err(dev, "timsel error\n");
 225                 return ret;
 226         }
 227
 228         rsnd_mod_bset(adg_mod, DIV_EN, en, en);
 229
 230         dev_dbg(dev, "convert rate %d <-> %d\n", src_rate, dst_rate);
 231
 232         return 0;
 233 }
 234
 235 int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *src_mod,
 236                                      struct rsnd_dai_stream *io)
 237 {
 238         u32 val = rsnd_adg_ssi_ws_timing_gen2(io);
 239
 240         rsnd_mod_confirm_src(src_mod);
 241
 242         return rsnd_adg_set_src_timsel_gen2(src_mod, io, val);
 243 }
 244
 245 int rsnd_adg_set_convert_clk_gen1(struct rsnd_priv *priv,
 246                                   struct rsnd_mod *mod,
 247                                   unsigned int src_rate,
 248                                   unsigned int dst_rate)
 249 {
 250         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 251         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 252         struct device *dev = rsnd_priv_to_dev(priv);
 253         int idx, sel, div, shift;
 254         u32 mask, val;
 255         int id = rsnd_mod_id(mod);
 256         unsigned int sel_rate [] = {
 257                 clk_get_rate(adg->clk[CLKA]),   /* 000: CLKA */
 258                 clk_get_rate(adg->clk[CLKB]),   /* 001: CLKB */
 259                 clk_get_rate(adg->clk[CLKC]),   /* 010: CLKC */
 260                 0,                              /* 011: MLBCLK (not used) */
 261                 adg->rbga_rate_for_441khz,      /* 100: RBGA */
 262                 adg->rbgb_rate_for_48khz,       /* 101: RBGB */
 263         };
 264
 265         /* find div (= 1/128, 1/256, 1/512, 1/1024, 1/2048 */
 266         for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
 267                 for (div  = 128,        idx = 0;
 268                      div <= 2048;
 269                      div *= 2,          idx++) {
 270                         if (src_rate == sel_rate[sel] / div) {
 271                                 val = (idx << 4) | sel;
 272                                 goto find_rate;
 273                         }
 274                 }
 275         }
 276         dev_err(dev, "can't find convert src clk\n");
 277         return -EINVAL;
 278
 279 find_rate:
 280         shift   = (id % 4) * 8;
 281         mask    = 0xFF << shift;
 282         val     = val << shift;
 283
 284         dev_dbg(dev, "adg convert src clk = %02x\n", val);
 285
 286         switch (id / 4) {
 287         case 0:
 288                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL3, mask, val);
 289                 break;
 290         case 1:
 291                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL4, mask, val);
 292                 break;
 293         case 2:
 294                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL5, mask, val);
 295                 break;
 296         }
 297
 298         /*
 299          * Gen1 doesn't need dst_rate settings,
 300          * since it uses SSI WS pin.
 301          * see also rsnd_src_set_route_if_gen1()
 302          */
 303
 304         return 0;
 305 }
 306
 307 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
 308 {
 309         struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
 310         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 311         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 312         int id = rsnd_mod_id(ssi_mod);
 313         int shift = (id % 4) * 8;
 314         u32 mask = 0xFF << shift;
 315
 316         rsnd_mod_confirm_ssi(ssi_mod);
 317
 318         val = val << shift;
 319
 320         /*
 321          * SSI 8 is not connected to ADG.
 322          * it works with SSI 7
 323          */
 324         if (id == 8)
 325                 return;
 326
 327         switch (id / 4) {
 328         case 0:
 329                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val);
 330                 break;
 331         case 1:
 332                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val);
 333                 break;
 334         case 2:
 335                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val);
 336                 break;
 337         }
 338 }
 339
 340 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod)
 341 {
 342         /*
 343          * "mod" = "ssi" here.
 344          * we can get "ssi id" from mod
 345          */
 346         rsnd_adg_set_ssi_clk(mod, 0);
 347
 348         return 0;
 349 }
 350
 351 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
 352 {
 353         struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
 354         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 355         struct device *dev = rsnd_priv_to_dev(priv);
 356         struct clk *clk;
 357         int i;
 358         u32 data;
 359         int sel_table[] = {
 360                 [CLKA] = 0x1,
 361                 [CLKB] = 0x2,
 362                 [CLKC] = 0x3,
 363                 [CLKI] = 0x0,
 364         };
 365
 366         dev_dbg(dev, "request clock = %d\n", rate);
 367
 368         /*
 369          * find suitable clock from
 370          * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
 371          */
 372         data = 0;
 373         for_each_rsnd_clk(clk, adg, i) {
 374                 if (rate == clk_get_rate(clk)) {
 375                         data = sel_table[i];
 376                         goto found_clock;
 377                 }
 378         }
 379
 380         /*
 381          * find divided clock from BRGA/BRGB
 382          */
 383         if (rate  == adg->rbga_rate_for_441khz) {
 384                 data = 0x10;
 385                 goto found_clock;
 386         }
 387
 388         if (rate == adg->rbgb_rate_for_48khz) {
 389                 data = 0x20;
 390                 goto found_clock;
 391         }
 392
 393         return -EIO;
 394
 395 found_clock:
 396
 397         /*
 398          * This "mod" = "ssi" here.
 399          * we can get "ssi id" from mod
 400          */
 401         rsnd_adg_set_ssi_clk(mod, data);
 402
 403         dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n",
 404                 rsnd_mod_name(mod), rsnd_mod_id(mod),
 405                 data, rate);
 406
 407         return 0;
 408 }
 409
 410 static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
 411                                struct rsnd_adg *adg)
 412 {
 413         struct device *dev = rsnd_priv_to_dev(priv);
 414         struct clk *clk;
 415         static const char * const clk_name[] = {
 416                 [CLKA]  = "clk_a",
 417                 [CLKB]  = "clk_b",
 418                 [CLKC]  = "clk_c",
 419                 [CLKI]  = "clk_i",
 420         };
 421         int i;
 422
 423         for (i = 0; i < CLKMAX; i++) {
 424                 clk = devm_clk_get(dev, clk_name[i]);
 425                 adg->clk[i] = IS_ERR(clk) ? NULL : clk;
 426         }
 427
 428         for_each_rsnd_clk(clk, adg, i)
 429                 dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
 430 }
 431
 432 static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
 433                                 struct rsnd_adg *adg)
 434 {
 435         struct clk *clk;
 436         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 437         struct device *dev = rsnd_priv_to_dev(priv);
 438         struct device_node *np = dev->of_node;
 439         u32 ckr, rbgx, rbga, rbgb;
 440         u32 rate, req_rate, div;
 441         uint32_t count = 0;
 442         unsigned long req_48kHz_rate, req_441kHz_rate;
 443         int i;
 444         const char *parent_clk_name = NULL;
 445         static const char * const clkout_name[] = {
 446                 [CLKOUT]  = "audio_clkout",
 447                 [CLKOUT1] = "audio_clkout1",
 448                 [CLKOUT2] = "audio_clkout2",
 449                 [CLKOUT3] = "audio_clkout3",
 450         };
 451         int brg_table[] = {
 452                 [CLKA] = 0x0,
 453                 [CLKB] = 0x1,
 454                 [CLKC] = 0x4,
 455                 [CLKI] = 0x2,
 456         };
 457
 458         of_property_read_u32(np, "#clock-cells", &count);
 459
 460         /*
 461          * ADG supports BRRA/BRRB output only
 462          * this means all clkout0/1/2/3 will be same rate
 463          */
 464         of_property_read_u32(np, "clock-frequency", &req_rate);
 465         req_48kHz_rate = 0;
 466         req_441kHz_rate = 0;
 467         if (0 == (req_rate % 44100))
 468                 req_441kHz_rate = req_rate;
 469         if (0 == (req_rate % 48000))
 470                 req_48kHz_rate = req_rate;
 471
 472         /*
 473          * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
 474          * have 44.1kHz or 48kHz base clocks for now.
 475          *
 476          * SSI itself can divide parent clock by 1/1 - 1/16
 477          * see
 478          *      rsnd_adg_ssi_clk_try_start()
 479          *      rsnd_ssi_master_clk_start()
 480          */
 481         ckr = 0;
 482         rbga = 2; /* default 1/6 */
 483         rbgb = 2; /* default 1/6 */
 484         adg->rbga_rate_for_441khz       = 0;
 485         adg->rbgb_rate_for_48khz        = 0;
 486         for_each_rsnd_clk(clk, adg, i) {
 487                 rate = clk_get_rate(clk);
 488
 489                 if (0 == rate) /* not used */
 490                         continue;
 491
 492                 /* RBGA */
 493                 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
 494                         div = 6;
 495                         if (req_441kHz_rate)
 496                                 div = rate / req_441kHz_rate;
 497                         rbgx = rsnd_adg_calculate_rbgx(div);
 498                         if (BRRx_MASK(rbgx) == rbgx) {
 499                                 rbga = rbgx;
 500                                 adg->rbga_rate_for_441khz = rate / div;
 501                                 ckr |= brg_table[i] << 20;
 502                                 if (req_441kHz_rate)
 503                                         parent_clk_name = __clk_get_name(clk);
 504                         }
 505                 }
 506
 507                 /* RBGB */
 508                 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
 509                         div = 6;
 510                         if (req_48kHz_rate)
 511                                 div = rate / req_48kHz_rate;
 512                         rbgx = rsnd_adg_calculate_rbgx(div);
 513                         if (BRRx_MASK(rbgx) == rbgx) {
 514                                 rbgb = rbgx;
 515                                 adg->rbgb_rate_for_48khz = rate / div;
 516                                 ckr |= brg_table[i] << 16;
 517                                 if (req_48kHz_rate) {
 518                                         parent_clk_name = __clk_get_name(clk);
 519                                         ckr |= 0x80000000;
 520                                 }
 521                         }
 522                 }
 523         }
 524
 525         /*
 526          * ADG supports BRRA/BRRB output only.
 527          * this means all clkout0/1/2/3 will be * same rate
 528          */
 529
 530         /*
 531          * for clkout
 532          */
 533         if (!count) {
 534                 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
 535                                               parent_clk_name,
 536                                               (parent_clk_name) ?
 537                                               0 : CLK_IS_ROOT, req_rate);
 538                 if (!IS_ERR(clk)) {
 539                         adg->clkout[CLKOUT] = clk;
 540                         of_clk_add_provider(np, of_clk_src_simple_get, clk);
 541                 }
 542         }
 543         /*
 544          * for clkout0/1/2/3
 545          */
 546         else {
 547                 for (i = 0; i < CLKOUTMAX; i++) {
 548                         clk = clk_register_fixed_rate(dev, clkout_name[i],
 549                                                       parent_clk_name,
 550                                                       (parent_clk_name) ?
 551                                                       0 : CLK_IS_ROOT,
 552                                                       req_rate);
 553                         if (!IS_ERR(clk)) {
 554                                 adg->onecell.clks       = adg->clkout;
 555                                 adg->onecell.clk_num    = CLKOUTMAX;
 556
 557                                 adg->clkout[i] = clk;
 558
 559                                 of_clk_add_provider(np, of_clk_src_onecell_get,
 560                                                     &adg->onecell);
 561                         }
 562                 }
 563         }
 564
 565         rsnd_mod_bset(adg_mod, SSICKR, 0x00FF0000, ckr);
 566         rsnd_mod_write(adg_mod, BRRA,  rbga);
 567         rsnd_mod_write(adg_mod, BRRB,  rbgb);
 568
 569         for_each_rsnd_clkout(clk, adg, i)
 570                 dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk));
 571         dev_dbg(dev, "SSICKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
 572                 ckr, rbga, rbgb);
 573 }
 574
 575 int rsnd_adg_probe(struct platform_device *pdev,
 576                    const struct rsnd_of_data *of_data,
 577                    struct rsnd_priv *priv)
 578 {
 579         struct rsnd_adg *adg;
 580         struct device *dev = rsnd_priv_to_dev(priv);
 581
 582         adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
 583         if (!adg) {
 584                 dev_err(dev, "ADG allocate failed\n");
 585                 return -ENOMEM;
 586         }
 587
 588         /*
 589          * ADG is special module.
 590          * Use ADG mod without rsnd_mod_init() to make debug easy
 591          * for rsnd_write/rsnd_read
 592          */
 593         adg->mod.ops = &adg_ops;
 594         adg->mod.priv = priv;
 595
 596         rsnd_adg_get_clkin(priv, adg);
 597         rsnd_adg_get_clkout(priv, adg);
 598
 599         priv->adg = adg;
 600
 601         return 0;
 602 }