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git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - sound/soc/sh/rcar/adg.c
2 * Helper routines for R-Car sound ADG.
4 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/clk-provider.h>
25 #define BRRx_MASK(x) (0x3FF & x)
27 static struct rsnd_mod_ops adg_ops
= {
32 struct clk
*clk
[CLKMAX
];
33 struct clk
*clkout
[CLKOUTMAX
];
34 struct clk_onecell_data onecell
;
41 int rbga_rate_for_441khz
; /* RBGA */
42 int rbgb_rate_for_48khz
; /* RBGB */
45 #define LRCLK_ASYNC (1 << 0)
46 #define AUDIO_OUT_48 (1 << 1)
48 #define for_each_rsnd_clk(pos, adg, i) \
51 ((pos) = adg->clk[i]); \
53 #define for_each_rsnd_clkout(pos, adg, i) \
56 ((pos) = adg->clkout[i]); \
58 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
60 static const char * const clk_name
[] = {
67 static u32
rsnd_adg_calculate_rbgx(unsigned long div
)
74 for (i
= 3; i
>= 0; i
--) {
76 if (0 == (div
% ratio
))
77 return (u32
)((i
<< 8) | ((div
/ ratio
) - 1));
83 static u32
rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream
*io
)
85 struct rsnd_mod
*ssi_mod
= rsnd_io_to_mod_ssi(io
);
86 int id
= rsnd_mod_id(ssi_mod
);
89 if (rsnd_ssi_is_pin_sharing(io
)) {
104 return (0x6 + ws
) << 8;
107 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv
*priv
,
108 struct rsnd_dai_stream
*io
,
109 unsigned int target_rate
,
110 unsigned int *target_val
,
111 unsigned int *target_en
)
113 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
114 struct device
*dev
= rsnd_priv_to_dev(priv
);
115 int idx
, sel
, div
, step
;
116 unsigned int val
, en
;
117 unsigned int min
, diff
;
118 unsigned int sel_rate
[] = {
119 clk_get_rate(adg
->clk
[CLKA
]), /* 0000: CLKA */
120 clk_get_rate(adg
->clk
[CLKB
]), /* 0001: CLKB */
121 clk_get_rate(adg
->clk
[CLKC
]), /* 0010: CLKC */
122 adg
->rbga_rate_for_441khz
, /* 0011: RBGA */
123 adg
->rbgb_rate_for_48khz
, /* 0100: RBGB */
129 for (sel
= 0; sel
< ARRAY_SIZE(sel_rate
); sel
++) {
136 for (div
= 2; div
<= 98304; div
+= step
) {
137 diff
= abs(target_rate
- sel_rate
[sel
] / div
);
139 val
= (sel
<< 8) | idx
;
141 en
= 1 << (sel
+ 1); /* fixme */
145 * step of 0_0000 / 0_0001 / 0_1101
148 if ((idx
> 2) && (idx
% 2))
159 dev_err(dev
, "no Input clock\n");
168 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv
*priv
,
169 struct rsnd_dai_stream
*io
,
170 unsigned int in_rate
,
171 unsigned int out_rate
,
172 u32
*in
, u32
*out
, u32
*en
)
174 struct snd_pcm_runtime
*runtime
= rsnd_io_to_runtime(io
);
175 unsigned int target_rate
;
181 /* default = SSI WS */
183 _out
= rsnd_adg_ssi_ws_timing_gen2(io
);
188 if (runtime
->rate
!= in_rate
) {
189 target_rate
= out_rate
;
191 } else if (runtime
->rate
!= out_rate
) {
192 target_rate
= in_rate
;
197 __rsnd_adg_get_timesel_ratio(priv
, io
,
209 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod
*cmd_mod
,
210 struct rsnd_dai_stream
*io
)
212 struct rsnd_priv
*priv
= rsnd_mod_to_priv(cmd_mod
);
213 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
214 struct rsnd_mod
*adg_mod
= rsnd_mod_get(adg
);
215 int id
= rsnd_mod_id(cmd_mod
);
216 int shift
= (id
% 2) ? 16 : 0;
219 rsnd_adg_get_timesel_ratio(priv
, io
,
220 rsnd_src_get_in_rate(priv
, io
),
221 rsnd_src_get_out_rate(priv
, io
),
225 mask
= 0x0f1f << shift
;
227 rsnd_mod_bset(adg_mod
, CMDOUT_TIMSEL
, mask
, val
);
232 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod
*src_mod
,
233 struct rsnd_dai_stream
*io
,
234 unsigned int in_rate
,
235 unsigned int out_rate
)
237 struct rsnd_priv
*priv
= rsnd_mod_to_priv(src_mod
);
238 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
239 struct rsnd_mod
*adg_mod
= rsnd_mod_get(adg
);
242 int id
= rsnd_mod_id(src_mod
);
243 int shift
= (id
% 2) ? 16 : 0;
245 rsnd_mod_confirm_src(src_mod
);
247 rsnd_adg_get_timesel_ratio(priv
, io
,
253 mask
= 0x0f1f << shift
;
257 rsnd_mod_bset(adg_mod
, SRCIN_TIMSEL0
, mask
, in
);
258 rsnd_mod_bset(adg_mod
, SRCOUT_TIMSEL0
, mask
, out
);
261 rsnd_mod_bset(adg_mod
, SRCIN_TIMSEL1
, mask
, in
);
262 rsnd_mod_bset(adg_mod
, SRCOUT_TIMSEL1
, mask
, out
);
265 rsnd_mod_bset(adg_mod
, SRCIN_TIMSEL2
, mask
, in
);
266 rsnd_mod_bset(adg_mod
, SRCOUT_TIMSEL2
, mask
, out
);
269 rsnd_mod_bset(adg_mod
, SRCIN_TIMSEL3
, mask
, in
);
270 rsnd_mod_bset(adg_mod
, SRCOUT_TIMSEL3
, mask
, out
);
273 rsnd_mod_bset(adg_mod
, SRCIN_TIMSEL4
, mask
, in
);
274 rsnd_mod_bset(adg_mod
, SRCOUT_TIMSEL4
, mask
, out
);
279 rsnd_mod_bset(adg_mod
, DIV_EN
, en
, en
);
284 static void rsnd_adg_set_ssi_clk(struct rsnd_mod
*ssi_mod
, u32 val
)
286 struct rsnd_priv
*priv
= rsnd_mod_to_priv(ssi_mod
);
287 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
288 struct rsnd_mod
*adg_mod
= rsnd_mod_get(adg
);
289 struct device
*dev
= rsnd_priv_to_dev(priv
);
290 int id
= rsnd_mod_id(ssi_mod
);
291 int shift
= (id
% 4) * 8;
292 u32 mask
= 0xFF << shift
;
294 rsnd_mod_confirm_ssi(ssi_mod
);
299 * SSI 8 is not connected to ADG.
300 * it works with SSI 7
307 rsnd_mod_bset(adg_mod
, AUDIO_CLK_SEL0
, mask
, val
);
310 rsnd_mod_bset(adg_mod
, AUDIO_CLK_SEL1
, mask
, val
);
313 rsnd_mod_bset(adg_mod
, AUDIO_CLK_SEL2
, mask
, val
);
317 dev_dbg(dev
, "AUDIO_CLK_SEL is 0x%x\n", val
);
320 int rsnd_adg_clk_query(struct rsnd_priv
*priv
, unsigned int rate
)
322 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
333 * find suitable clock from
334 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
336 for_each_rsnd_clk(clk
, adg
, i
) {
337 if (rate
== clk_get_rate(clk
))
342 * find divided clock from BRGA/BRGB
344 if (rate
== adg
->rbga_rate_for_441khz
)
347 if (rate
== adg
->rbgb_rate_for_48khz
)
353 int rsnd_adg_ssi_clk_stop(struct rsnd_mod
*ssi_mod
)
355 rsnd_adg_set_ssi_clk(ssi_mod
, 0);
360 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod
*ssi_mod
, unsigned int rate
)
362 struct rsnd_priv
*priv
= rsnd_mod_to_priv(ssi_mod
);
363 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
364 struct device
*dev
= rsnd_priv_to_dev(priv
);
365 struct rsnd_mod
*adg_mod
= rsnd_mod_get(adg
);
369 data
= rsnd_adg_clk_query(priv
, rate
);
373 rsnd_adg_set_ssi_clk(ssi_mod
, data
);
375 if (rsnd_flags_has(adg
, LRCLK_ASYNC
)) {
376 if (rsnd_flags_has(adg
, AUDIO_OUT_48
))
379 if (0 == (rate
% 8000))
383 rsnd_mod_bset(adg_mod
, BRGCKR
, 0x80770000, adg
->ckr
| ckr
);
384 rsnd_mod_write(adg_mod
, BRRA
, adg
->rbga
);
385 rsnd_mod_write(adg_mod
, BRRB
, adg
->rbgb
);
387 dev_dbg(dev
, "CLKOUT is based on BRG%c (= %dHz)\n",
389 (ckr
) ? adg
->rbgb_rate_for_48khz
:
390 adg
->rbga_rate_for_441khz
);
395 void rsnd_adg_clk_control(struct rsnd_priv
*priv
, int enable
)
397 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
398 struct device
*dev
= rsnd_priv_to_dev(priv
);
402 for_each_rsnd_clk(clk
, adg
, i
) {
405 ret
= clk_prepare_enable(clk
);
407 clk_disable_unprepare(clk
);
410 dev_warn(dev
, "can't use clk %d\n", i
);
414 static void rsnd_adg_get_clkin(struct rsnd_priv
*priv
,
415 struct rsnd_adg
*adg
)
417 struct device
*dev
= rsnd_priv_to_dev(priv
);
421 for (i
= 0; i
< CLKMAX
; i
++) {
422 clk
= devm_clk_get(dev
, clk_name
[i
]);
423 adg
->clk
[i
] = IS_ERR(clk
) ? NULL
: clk
;
427 static void rsnd_adg_get_clkout(struct rsnd_priv
*priv
,
428 struct rsnd_adg
*adg
)
431 struct device
*dev
= rsnd_priv_to_dev(priv
);
432 struct device_node
*np
= dev
->of_node
;
433 struct property
*prop
;
434 u32 ckr
, rbgx
, rbga
, rbgb
;
437 u32 req_rate
[REQ_SIZE
] = {};
439 unsigned long req_48kHz_rate
, req_441kHz_rate
;
441 const char *parent_clk_name
= NULL
;
442 static const char * const clkout_name
[] = {
443 [CLKOUT
] = "audio_clkout",
444 [CLKOUT1
] = "audio_clkout1",
445 [CLKOUT2
] = "audio_clkout2",
446 [CLKOUT3
] = "audio_clkout3",
456 rbga
= 2; /* default 1/6 */
457 rbgb
= 2; /* default 1/6 */
460 * ADG supports BRRA/BRRB output only
461 * this means all clkout0/1/2/3 will be same rate
463 prop
= of_find_property(np
, "clock-frequency", NULL
);
465 goto rsnd_adg_get_clkout_end
;
467 req_size
= prop
->length
/ sizeof(u32
);
469 of_property_read_u32_array(np
, "clock-frequency", req_rate
, req_size
);
472 for (i
= 0; i
< req_size
; i
++) {
473 if (0 == (req_rate
[i
] % 44100))
474 req_441kHz_rate
= req_rate
[i
];
475 if (0 == (req_rate
[i
] % 48000))
476 req_48kHz_rate
= req_rate
[i
];
479 if (req_rate
[0] % 48000 == 0)
480 rsnd_flags_set(adg
, AUDIO_OUT_48
);
482 if (of_get_property(np
, "clkout-lr-asynchronous", NULL
))
483 rsnd_flags_set(adg
, LRCLK_ASYNC
);
486 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
487 * have 44.1kHz or 48kHz base clocks for now.
489 * SSI itself can divide parent clock by 1/1 - 1/16
491 * rsnd_adg_ssi_clk_try_start()
492 * rsnd_ssi_master_clk_start()
494 adg
->rbga_rate_for_441khz
= 0;
495 adg
->rbgb_rate_for_48khz
= 0;
496 for_each_rsnd_clk(clk
, adg
, i
) {
497 rate
= clk_get_rate(clk
);
499 if (0 == rate
) /* not used */
503 if (!adg
->rbga_rate_for_441khz
&& (0 == rate
% 44100)) {
506 div
= rate
/ req_441kHz_rate
;
507 rbgx
= rsnd_adg_calculate_rbgx(div
);
508 if (BRRx_MASK(rbgx
) == rbgx
) {
510 adg
->rbga_rate_for_441khz
= rate
/ div
;
511 ckr
|= brg_table
[i
] << 20;
512 if (req_441kHz_rate
&&
513 !rsnd_flags_has(adg
, AUDIO_OUT_48
))
514 parent_clk_name
= __clk_get_name(clk
);
519 if (!adg
->rbgb_rate_for_48khz
&& (0 == rate
% 48000)) {
522 div
= rate
/ req_48kHz_rate
;
523 rbgx
= rsnd_adg_calculate_rbgx(div
);
524 if (BRRx_MASK(rbgx
) == rbgx
) {
526 adg
->rbgb_rate_for_48khz
= rate
/ div
;
527 ckr
|= brg_table
[i
] << 16;
528 if (req_48kHz_rate
&&
529 rsnd_flags_has(adg
, AUDIO_OUT_48
))
530 parent_clk_name
= __clk_get_name(clk
);
536 * ADG supports BRRA/BRRB output only.
537 * this means all clkout0/1/2/3 will be * same rate
540 of_property_read_u32(np
, "#clock-cells", &count
);
545 clk
= clk_register_fixed_rate(dev
, clkout_name
[CLKOUT
],
546 parent_clk_name
, 0, req_rate
[0]);
548 adg
->clkout
[CLKOUT
] = clk
;
549 of_clk_add_provider(np
, of_clk_src_simple_get
, clk
);
556 for (i
= 0; i
< CLKOUTMAX
; i
++) {
557 clk
= clk_register_fixed_rate(dev
, clkout_name
[i
],
561 adg
->clkout
[i
] = clk
;
563 adg
->onecell
.clks
= adg
->clkout
;
564 adg
->onecell
.clk_num
= CLKOUTMAX
;
565 of_clk_add_provider(np
, of_clk_src_onecell_get
,
569 rsnd_adg_get_clkout_end
:
576 static void rsnd_adg_clk_dbg_info(struct rsnd_priv
*priv
, struct rsnd_adg
*adg
)
578 struct device
*dev
= rsnd_priv_to_dev(priv
);
582 for_each_rsnd_clk(clk
, adg
, i
)
583 dev_dbg(dev
, "%s : %p : %ld\n",
584 clk_name
[i
], clk
, clk_get_rate(clk
));
586 dev_dbg(dev
, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
587 adg
->ckr
, adg
->rbga
, adg
->rbgb
);
588 dev_dbg(dev
, "BRGA (for 44100 base) = %d\n", adg
->rbga_rate_for_441khz
);
589 dev_dbg(dev
, "BRGB (for 48000 base) = %d\n", adg
->rbgb_rate_for_48khz
);
592 * Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start()
593 * by BRGCKR::BRGCKR_31
595 for_each_rsnd_clkout(clk
, adg
, i
)
596 dev_dbg(dev
, "clkout %d : %p : %ld\n", i
,
597 clk
, clk_get_rate(clk
));
600 #define rsnd_adg_clk_dbg_info(priv, adg)
603 int rsnd_adg_probe(struct rsnd_priv
*priv
)
605 struct rsnd_adg
*adg
;
606 struct device
*dev
= rsnd_priv_to_dev(priv
);
609 adg
= devm_kzalloc(dev
, sizeof(*adg
), GFP_KERNEL
);
613 ret
= rsnd_mod_init(priv
, &adg
->mod
, &adg_ops
,
618 rsnd_adg_get_clkin(priv
, adg
);
619 rsnd_adg_get_clkout(priv
, adg
);
620 rsnd_adg_clk_dbg_info(priv
, adg
);
624 rsnd_adg_clk_enable(priv
);
629 void rsnd_adg_remove(struct rsnd_priv
*priv
)
631 struct device
*dev
= rsnd_priv_to_dev(priv
);
632 struct device_node
*np
= dev
->of_node
;
633 struct rsnd_adg
*adg
= priv
->adg
;
637 for_each_rsnd_clkout(clk
, adg
, i
)
639 clk_unregister_fixed_rate(adg
->clkout
[i
]);
641 of_clk_del_provider(np
);
643 rsnd_adg_clk_disable(priv
);