sound/soc/sof/intel/cnl.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2 //
   3 // This file is provided under a dual BSD/GPLv2 license.  When using or
   4 // redistributing this file, you may do so under either license.
   5 //
   6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
   7 //
   8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
   9 //          Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
  10 //          Rander Wang <rander.wang@intel.com>
  11 //          Keyon Jie <yang.jie@linux.intel.com>
  12 //
  13
  14 /*
  15  * Hardware interface for audio DSP on Cannonlake.
  16  */
  17
  18 #include "../ops.h"
  19 #include "hda.h"
  20 #include "hda-ipc.h"
  21 #include "../sof-audio.h"
  22
  23 static const struct snd_sof_debugfs_map cnl_dsp_debugfs[] = {
  24         {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
  25         {"pp", HDA_DSP_PP_BAR,  0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
  26         {"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
  27 };
  28
  29 static void cnl_ipc_host_done(struct snd_sof_dev *sdev);
  30 static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev);
  31
  32 static irqreturn_t cnl_ipc_irq_thread(int irq, void *context)
  33 {
  34         struct snd_sof_dev *sdev = context;
  35         u32 hipci;
  36         u32 hipcida;
  37         u32 hipctdr;
  38         u32 hipctdd;
  39         u32 msg;
  40         u32 msg_ext;
  41         bool ipc_irq = false;
  42
  43         hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
  44         hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
  45         hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDD);
  46         hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR);
  47
  48         /* reply message from DSP */
  49         if (hipcida & CNL_DSP_REG_HIPCIDA_DONE) {
  50                 msg_ext = hipci & CNL_DSP_REG_HIPCIDR_MSG_MASK;
  51                 msg = hipcida & CNL_DSP_REG_HIPCIDA_MSG_MASK;
  52
  53                 dev_vdbg(sdev->dev,
  54                          "ipc: firmware response, msg:0x%x, msg_ext:0x%x\n",
  55                          msg, msg_ext);
  56
  57                 /* mask Done interrupt */
  58                 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
  59                                         CNL_DSP_REG_HIPCCTL,
  60                                         CNL_DSP_REG_HIPCCTL_DONE, 0);
  61
  62                 spin_lock_irq(&sdev->ipc_lock);
  63
  64                 /* handle immediate reply from DSP core */
  65                 hda_dsp_ipc_get_reply(sdev);
  66                 snd_sof_ipc_reply(sdev, msg);
  67
  68                 cnl_ipc_dsp_done(sdev);
  69
  70                 spin_unlock_irq(&sdev->ipc_lock);
  71
  72                 ipc_irq = true;
  73         }
  74
  75         /* new message from DSP */
  76         if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) {
  77                 msg = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK;
  78                 msg_ext = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK;
  79
  80                 dev_vdbg(sdev->dev,
  81                          "ipc: firmware initiated, msg:0x%x, msg_ext:0x%x\n",
  82                          msg, msg_ext);
  83
  84                 /* handle messages from DSP */
  85                 if ((hipctdr & SOF_IPC_PANIC_MAGIC_MASK) ==
  86                    SOF_IPC_PANIC_MAGIC) {
  87                         snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext));
  88                 } else {
  89                         snd_sof_ipc_msgs_rx(sdev);
  90                 }
  91
  92                 cnl_ipc_host_done(sdev);
  93
  94                 ipc_irq = true;
  95         }
  96
  97         if (!ipc_irq) {
  98                 /*
  99                  * This interrupt is not shared so no need to return IRQ_NONE.
 100                  */
 101                 dev_dbg_ratelimited(sdev->dev,
 102                                     "nothing to do in IPC IRQ thread\n");
 103         }
 104
 105         return IRQ_HANDLED;
 106 }
 107
 108 static void cnl_ipc_host_done(struct snd_sof_dev *sdev)
 109 {
 110         /*
 111          * clear busy interrupt to tell dsp controller this
 112          * interrupt has been accepted, not trigger it again
 113          */
 114         snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
 115                                        CNL_DSP_REG_HIPCTDR,
 116                                        CNL_DSP_REG_HIPCTDR_BUSY,
 117                                        CNL_DSP_REG_HIPCTDR_BUSY);
 118         /*
 119          * set done bit to ack dsp the msg has been
 120          * processed and send reply msg to dsp
 121          */
 122         snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
 123                                        CNL_DSP_REG_HIPCTDA,
 124                                        CNL_DSP_REG_HIPCTDA_DONE,
 125                                        CNL_DSP_REG_HIPCTDA_DONE);
 126 }
 127
 128 static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev)
 129 {
 130         /*
 131          * set DONE bit - tell DSP we have received the reply msg
 132          * from DSP, and processed it, don't send more reply to host
 133          */
 134         snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
 135                                        CNL_DSP_REG_HIPCIDA,
 136                                        CNL_DSP_REG_HIPCIDA_DONE,
 137                                        CNL_DSP_REG_HIPCIDA_DONE);
 138
 139         /* unmask Done interrupt */
 140         snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
 141                                 CNL_DSP_REG_HIPCCTL,
 142                                 CNL_DSP_REG_HIPCCTL_DONE,
 143                                 CNL_DSP_REG_HIPCCTL_DONE);
 144 }
 145
 146 static bool cnl_compact_ipc_compress(struct snd_sof_ipc_msg *msg,
 147                                      u32 *dr, u32 *dd)
 148 {
 149         struct sof_ipc_pm_gate *pm_gate;
 150
 151         if (msg->header == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) {
 152                 pm_gate = msg->msg_data;
 153
 154                 /* send the compact message via the primary register */
 155                 *dr = HDA_IPC_MSG_COMPACT | HDA_IPC_PM_GATE;
 156
 157                 /* send payload via the extended data register */
 158                 *dd = pm_gate->flags;
 159
 160                 return true;
 161         }
 162
 163         return false;
 164 }
 165
 166 static int cnl_ipc_send_msg(struct snd_sof_dev *sdev,
 167                             struct snd_sof_ipc_msg *msg)
 168 {
 169         struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
 170         struct sof_ipc_cmd_hdr *hdr;
 171         u32 dr = 0;
 172         u32 dd = 0;
 173
 174         /*
 175          * Currently the only compact IPC supported is the PM_GATE
 176          * IPC which is used for transitioning the DSP between the
 177          * D0I0 and D0I3 states. And these are sent only during the
 178          * set_power_state() op. Therefore, there will never be a case
 179          * that a compact IPC results in the DSP exiting D0I3 without
 180          * the host and FW being in sync.
 181          */
 182         if (cnl_compact_ipc_compress(msg, &dr, &dd)) {
 183                 /* send the message via IPC registers */
 184                 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDD,
 185                                   dd);
 186                 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
 187                                   CNL_DSP_REG_HIPCIDR_BUSY | dr);
 188                 return 0;
 189         }
 190
 191         /* send the message via mailbox */
 192         sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
 193                           msg->msg_size);
 194         snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
 195                           CNL_DSP_REG_HIPCIDR_BUSY);
 196
 197         hdr = msg->msg_data;
 198
 199         /*
 200          * Use mod_delayed_work() to schedule the delayed work
 201          * to avoid scheduling multiple workqueue items when
 202          * IPCs are sent at a high-rate. mod_delayed_work()
 203          * modifies the timer if the work is pending.
 204          * Also, a new delayed work should not be queued after the
 205          * the CTX_SAVE IPC, which is sent before the DSP enters D3.
 206          */
 207         if (hdr->cmd != (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE))
 208                 mod_delayed_work(system_wq, &hdev->d0i3_work,
 209                                  msecs_to_jiffies(SOF_HDA_D0I3_WORK_DELAY_MS));
 210
 211         return 0;
 212 }
 213
 214 static void cnl_ipc_dump(struct snd_sof_dev *sdev)
 215 {
 216         u32 hipcctl;
 217         u32 hipcida;
 218         u32 hipctdr;
 219
 220         hda_ipc_irq_dump(sdev);
 221
 222         /* read IPC status */
 223         hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
 224         hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL);
 225         hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
 226
 227         /* dump the IPC regs */
 228         /* TODO: parse the raw msg */
 229         dev_err(sdev->dev,
 230                 "error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
 231                 hipcida, hipctdr, hipcctl);
 232 }
 233
 234 /* cannonlake ops */
 235 const struct snd_sof_dsp_ops sof_cnl_ops = {
 236         /* probe and remove */
 237         .probe          = hda_dsp_probe,
 238         .remove         = hda_dsp_remove,
 239
 240         /* Register IO */
 241         .write          = sof_io_write,
 242         .read           = sof_io_read,
 243         .write64        = sof_io_write64,
 244         .read64         = sof_io_read64,
 245
 246         /* Block IO */
 247         .block_read     = sof_block_read,
 248         .block_write    = sof_block_write,
 249
 250         /* doorbell */
 251         .irq_thread     = cnl_ipc_irq_thread,
 252
 253         /* ipc */
 254         .send_msg       = cnl_ipc_send_msg,
 255         .fw_ready       = sof_fw_ready,
 256         .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset,
 257         .get_window_offset = hda_dsp_ipc_get_window_offset,
 258
 259         .ipc_msg_data   = hda_ipc_msg_data,
 260         .ipc_pcm_params = hda_ipc_pcm_params,
 261
 262         /* machine driver */
 263         .machine_select = hda_machine_select,
 264         .machine_register = sof_machine_register,
 265         .machine_unregister = sof_machine_unregister,
 266         .set_mach_params = hda_set_mach_params,
 267
 268         /* debug */
 269         .debug_map      = cnl_dsp_debugfs,
 270         .debug_map_count        = ARRAY_SIZE(cnl_dsp_debugfs),
 271         .dbg_dump       = hda_dsp_dump,
 272         .ipc_dump       = cnl_ipc_dump,
 273
 274         /* stream callbacks */
 275         .pcm_open       = hda_dsp_pcm_open,
 276         .pcm_close      = hda_dsp_pcm_close,
 277         .pcm_hw_params  = hda_dsp_pcm_hw_params,
 278         .pcm_hw_free    = hda_dsp_stream_hw_free,
 279         .pcm_trigger    = hda_dsp_pcm_trigger,
 280         .pcm_pointer    = hda_dsp_pcm_pointer,
 281
 282 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
 283         /* probe callbacks */
 284         .probe_assign   = hda_probe_compr_assign,
 285         .probe_free     = hda_probe_compr_free,
 286         .probe_set_params       = hda_probe_compr_set_params,
 287         .probe_trigger  = hda_probe_compr_trigger,
 288         .probe_pointer  = hda_probe_compr_pointer,
 289 #endif
 290
 291         /* firmware loading */
 292         .load_firmware = snd_sof_load_firmware_raw,
 293
 294         /* pre/post fw run */
 295         .pre_fw_run = hda_dsp_pre_fw_run,
 296         .post_fw_run = hda_dsp_post_fw_run,
 297
 298         /* dsp core power up/down */
 299         .core_power_up = hda_dsp_enable_core,
 300         .core_power_down = hda_dsp_core_reset_power_down,
 301
 302         /* firmware run */
 303         .run = hda_dsp_cl_boot_firmware,
 304
 305         /* trace callback */
 306         .trace_init = hda_dsp_trace_init,
 307         .trace_release = hda_dsp_trace_release,
 308         .trace_trigger = hda_dsp_trace_trigger,
 309
 310         /* DAI drivers */
 311         .drv            = skl_dai,
 312         .num_drv        = SOF_SKL_NUM_DAIS,
 313
 314         /* PM */
 315         .suspend                = hda_dsp_suspend,
 316         .resume                 = hda_dsp_resume,
 317         .runtime_suspend        = hda_dsp_runtime_suspend,
 318         .runtime_resume         = hda_dsp_runtime_resume,
 319         .runtime_idle           = hda_dsp_runtime_idle,
 320         .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume,
 321         .set_power_state        = hda_dsp_set_power_state,
 322
 323         /* ALSA HW info flags */
 324         .hw_info =      SNDRV_PCM_INFO_MMAP |
 325                         SNDRV_PCM_INFO_MMAP_VALID |
 326                         SNDRV_PCM_INFO_INTERLEAVED |
 327                         SNDRV_PCM_INFO_PAUSE |
 328                         SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
 329
 330         .arch_ops = &sof_xtensa_arch_ops,
 331 };
 332 EXPORT_SYMBOL_NS(sof_cnl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
 333
 334 const struct sof_intel_dsp_desc cnl_chip_info = {
 335         /* Cannonlake */
 336         .cores_num = 4,
 337         .init_core_mask = 1,
 338         .cores_mask = HDA_DSP_CORE_MASK(0) |
 339                                 HDA_DSP_CORE_MASK(1) |
 340                                 HDA_DSP_CORE_MASK(2) |
 341                                 HDA_DSP_CORE_MASK(3),
 342         .ipc_req = CNL_DSP_REG_HIPCIDR,
 343         .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
 344         .ipc_ack = CNL_DSP_REG_HIPCIDA,
 345         .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
 346         .ipc_ctl = CNL_DSP_REG_HIPCCTL,
 347         .rom_init_timeout       = 300,
 348         .ssp_count = CNL_SSP_COUNT,
 349         .ssp_base_offset = CNL_SSP_BASE_OFFSET,
 350 };
 351 EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 352
 353 const struct sof_intel_dsp_desc icl_chip_info = {
 354         /* Icelake */
 355         .cores_num = 4,
 356         .init_core_mask = 1,
 357         .cores_mask = HDA_DSP_CORE_MASK(0) |
 358                                 HDA_DSP_CORE_MASK(1) |
 359                                 HDA_DSP_CORE_MASK(2) |
 360                                 HDA_DSP_CORE_MASK(3),
 361         .ipc_req = CNL_DSP_REG_HIPCIDR,
 362         .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
 363         .ipc_ack = CNL_DSP_REG_HIPCIDA,
 364         .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
 365         .ipc_ctl = CNL_DSP_REG_HIPCCTL,
 366         .rom_init_timeout       = 300,
 367         .ssp_count = ICL_SSP_COUNT,
 368         .ssp_base_offset = CNL_SSP_BASE_OFFSET,
 369 };
 370 EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 371
 372 const struct sof_intel_dsp_desc tgl_chip_info = {
 373         /* Tigerlake */
 374         .cores_num = 4,
 375         .init_core_mask = 1,
 376         .cores_mask = HDA_DSP_CORE_MASK(0),
 377         .ipc_req = CNL_DSP_REG_HIPCIDR,
 378         .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
 379         .ipc_ack = CNL_DSP_REG_HIPCIDA,
 380         .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
 381         .ipc_ctl = CNL_DSP_REG_HIPCCTL,
 382         .rom_init_timeout       = 300,
 383         .ssp_count = ICL_SSP_COUNT,
 384         .ssp_base_offset = CNL_SSP_BASE_OFFSET,
 385 };
 386 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 387
 388 const struct sof_intel_dsp_desc ehl_chip_info = {
 389         /* Elkhartlake */
 390         .cores_num = 4,
 391         .init_core_mask = 1,
 392         .cores_mask = HDA_DSP_CORE_MASK(0),
 393         .ipc_req = CNL_DSP_REG_HIPCIDR,
 394         .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
 395         .ipc_ack = CNL_DSP_REG_HIPCIDA,
 396         .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
 397         .ipc_ctl = CNL_DSP_REG_HIPCCTL,
 398         .rom_init_timeout       = 300,
 399         .ssp_count = ICL_SSP_COUNT,
 400         .ssp_base_offset = CNL_SSP_BASE_OFFSET,
 401 };
 402 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 403
 404 const struct sof_intel_dsp_desc jsl_chip_info = {
 405         /* Jasperlake */
 406         .cores_num = 2,
 407         .init_core_mask = 1,
 408         .cores_mask = HDA_DSP_CORE_MASK(0) |
 409                                 HDA_DSP_CORE_MASK(1),
 410         .ipc_req = CNL_DSP_REG_HIPCIDR,
 411         .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
 412         .ipc_ack = CNL_DSP_REG_HIPCIDA,
 413         .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
 414         .ipc_ctl = CNL_DSP_REG_HIPCCTL,
 415         .rom_init_timeout       = 300,
 416         .ssp_count = ICL_SSP_COUNT,
 417         .ssp_base_offset = CNL_SSP_BASE_OFFSET,
 418 };
 419 EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);