1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10 // Rander Wang <rander.wang@intel.com>
11 // Keyon Jie <yang.jie@linux.intel.com>
15 * Hardware interface for generic Intel audio DSP HDA IP
18 #include <linux/module.h>
19 #include <sound/hdaudio_ext.h>
20 #include <sound/hda_register.h>
21 #include "../sof-audio.h"
26 static bool hda_enable_trace_D0I3_S0
;
27 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG)
28 module_param_named(enable_trace_D0I3_S0
, hda_enable_trace_D0I3_S0
, bool, 0444);
29 MODULE_PARM_DESC(enable_trace_D0I3_S0
,
30 "SOF HDA enable trace when the DSP is in D0I3 in S0");
37 int hda_dsp_core_reset_enter(struct snd_sof_dev
*sdev
, unsigned int core_mask
)
43 /* set reset bits for cores */
44 reset
= HDA_DSP_ADSPCS_CRST_MASK(core_mask
);
45 snd_sof_dsp_update_bits_unlocked(sdev
, HDA_DSP_BAR
,
49 /* poll with timeout to check if operation successful */
50 ret
= snd_sof_dsp_read_poll_timeout(sdev
, HDA_DSP_BAR
,
51 HDA_DSP_REG_ADSPCS
, adspcs
,
52 ((adspcs
& reset
) == reset
),
53 HDA_DSP_REG_POLL_INTERVAL_US
,
54 HDA_DSP_RESET_TIMEOUT_US
);
57 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
62 /* has core entered reset ? */
63 adspcs
= snd_sof_dsp_read(sdev
, HDA_DSP_BAR
,
65 if ((adspcs
& HDA_DSP_ADSPCS_CRST_MASK(core_mask
)) !=
66 HDA_DSP_ADSPCS_CRST_MASK(core_mask
)) {
68 "error: reset enter failed: core_mask %x adspcs 0x%x\n",
76 int hda_dsp_core_reset_leave(struct snd_sof_dev
*sdev
, unsigned int core_mask
)
82 /* clear reset bits for cores */
83 snd_sof_dsp_update_bits_unlocked(sdev
, HDA_DSP_BAR
,
85 HDA_DSP_ADSPCS_CRST_MASK(core_mask
),
88 /* poll with timeout to check if operation successful */
89 crst
= HDA_DSP_ADSPCS_CRST_MASK(core_mask
);
90 ret
= snd_sof_dsp_read_poll_timeout(sdev
, HDA_DSP_BAR
,
91 HDA_DSP_REG_ADSPCS
, adspcs
,
93 HDA_DSP_REG_POLL_INTERVAL_US
,
94 HDA_DSP_RESET_TIMEOUT_US
);
98 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
103 /* has core left reset ? */
104 adspcs
= snd_sof_dsp_read(sdev
, HDA_DSP_BAR
,
106 if ((adspcs
& HDA_DSP_ADSPCS_CRST_MASK(core_mask
)) != 0) {
108 "error: reset leave failed: core_mask %x adspcs 0x%x\n",
116 int hda_dsp_core_stall_reset(struct snd_sof_dev
*sdev
, unsigned int core_mask
)
119 snd_sof_dsp_update_bits_unlocked(sdev
, HDA_DSP_BAR
,
121 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask
),
122 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask
));
124 /* set reset state */
125 return hda_dsp_core_reset_enter(sdev
, core_mask
);
128 int hda_dsp_core_run(struct snd_sof_dev
*sdev
, unsigned int core_mask
)
132 /* leave reset state */
133 ret
= hda_dsp_core_reset_leave(sdev
, core_mask
);
138 dev_dbg(sdev
->dev
, "unstall/run core: core_mask = %x\n", core_mask
);
139 snd_sof_dsp_update_bits_unlocked(sdev
, HDA_DSP_BAR
,
141 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask
),
144 /* is core now running ? */
145 if (!hda_dsp_core_is_enabled(sdev
, core_mask
)) {
146 hda_dsp_core_stall_reset(sdev
, core_mask
);
147 dev_err(sdev
->dev
, "error: DSP start core failed: core_mask %x\n",
159 int hda_dsp_core_power_up(struct snd_sof_dev
*sdev
, unsigned int core_mask
)
166 snd_sof_dsp_update_bits(sdev
, HDA_DSP_BAR
, HDA_DSP_REG_ADSPCS
,
167 HDA_DSP_ADSPCS_SPA_MASK(core_mask
),
168 HDA_DSP_ADSPCS_SPA_MASK(core_mask
));
170 /* poll with timeout to check if operation successful */
171 cpa
= HDA_DSP_ADSPCS_CPA_MASK(core_mask
);
172 ret
= snd_sof_dsp_read_poll_timeout(sdev
, HDA_DSP_BAR
,
173 HDA_DSP_REG_ADSPCS
, adspcs
,
174 (adspcs
& cpa
) == cpa
,
175 HDA_DSP_REG_POLL_INTERVAL_US
,
176 HDA_DSP_RESET_TIMEOUT_US
);
179 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
184 /* did core power up ? */
185 adspcs
= snd_sof_dsp_read(sdev
, HDA_DSP_BAR
,
187 if ((adspcs
& HDA_DSP_ADSPCS_CPA_MASK(core_mask
)) !=
188 HDA_DSP_ADSPCS_CPA_MASK(core_mask
)) {
190 "error: power up core failed core_mask %xadspcs 0x%x\n",
198 int hda_dsp_core_power_down(struct snd_sof_dev
*sdev
, unsigned int core_mask
)
204 snd_sof_dsp_update_bits_unlocked(sdev
, HDA_DSP_BAR
,
206 HDA_DSP_ADSPCS_SPA_MASK(core_mask
), 0);
208 ret
= snd_sof_dsp_read_poll_timeout(sdev
, HDA_DSP_BAR
,
209 HDA_DSP_REG_ADSPCS
, adspcs
,
210 !(adspcs
& HDA_DSP_ADSPCS_SPA_MASK(core_mask
)),
211 HDA_DSP_REG_POLL_INTERVAL_US
,
212 HDA_DSP_PD_TIMEOUT
* USEC_PER_MSEC
);
215 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
221 bool hda_dsp_core_is_enabled(struct snd_sof_dev
*sdev
,
222 unsigned int core_mask
)
227 val
= snd_sof_dsp_read(sdev
, HDA_DSP_BAR
, HDA_DSP_REG_ADSPCS
);
229 is_enable
= (val
& HDA_DSP_ADSPCS_CPA_MASK(core_mask
)) &&
230 (val
& HDA_DSP_ADSPCS_SPA_MASK(core_mask
)) &&
231 !(val
& HDA_DSP_ADSPCS_CRST_MASK(core_mask
)) &&
232 !(val
& HDA_DSP_ADSPCS_CSTALL_MASK(core_mask
));
234 dev_dbg(sdev
->dev
, "DSP core(s) enabled? %d : core_mask %x\n",
235 is_enable
, core_mask
);
240 int hda_dsp_enable_core(struct snd_sof_dev
*sdev
, unsigned int core_mask
)
242 struct sof_intel_hda_dev
*hda
= sdev
->pdata
->hw_pdata
;
243 const struct sof_intel_dsp_desc
*chip
= hda
->desc
;
246 /* restrict core_mask to host managed cores mask */
247 core_mask
&= chip
->host_managed_cores_mask
;
249 /* return if core_mask is not valid or cores are already enabled */
250 if (!core_mask
|| hda_dsp_core_is_enabled(sdev
, core_mask
))
254 ret
= hda_dsp_core_power_up(sdev
, core_mask
);
256 dev_err(sdev
->dev
, "error: dsp core power up failed: core_mask %x\n",
261 return hda_dsp_core_run(sdev
, core_mask
);
264 int hda_dsp_core_reset_power_down(struct snd_sof_dev
*sdev
,
265 unsigned int core_mask
)
267 struct sof_intel_hda_dev
*hda
= sdev
->pdata
->hw_pdata
;
268 const struct sof_intel_dsp_desc
*chip
= hda
->desc
;
271 /* restrict core_mask to host managed cores mask */
272 core_mask
&= chip
->host_managed_cores_mask
;
274 /* return if core_mask is not valid */
278 /* place core in reset prior to power down */
279 ret
= hda_dsp_core_stall_reset(sdev
, core_mask
);
281 dev_err(sdev
->dev
, "error: dsp core reset failed: core_mask %x\n",
286 /* power down core */
287 ret
= hda_dsp_core_power_down(sdev
, core_mask
);
289 dev_err(sdev
->dev
, "error: dsp core power down fail mask %x: %d\n",
294 /* make sure we are in OFF state */
295 if (hda_dsp_core_is_enabled(sdev
, core_mask
)) {
296 dev_err(sdev
->dev
, "error: dsp core disable fail mask %x: %d\n",
304 void hda_dsp_ipc_int_enable(struct snd_sof_dev
*sdev
)
306 struct sof_intel_hda_dev
*hda
= sdev
->pdata
->hw_pdata
;
307 const struct sof_intel_dsp_desc
*chip
= hda
->desc
;
309 /* enable IPC DONE and BUSY interrupts */
310 snd_sof_dsp_update_bits(sdev
, HDA_DSP_BAR
, chip
->ipc_ctl
,
311 HDA_DSP_REG_HIPCCTL_DONE
| HDA_DSP_REG_HIPCCTL_BUSY
,
312 HDA_DSP_REG_HIPCCTL_DONE
| HDA_DSP_REG_HIPCCTL_BUSY
);
314 /* enable IPC interrupt */
315 snd_sof_dsp_update_bits(sdev
, HDA_DSP_BAR
, HDA_DSP_REG_ADSPIC
,
316 HDA_DSP_ADSPIC_IPC
, HDA_DSP_ADSPIC_IPC
);
319 void hda_dsp_ipc_int_disable(struct snd_sof_dev
*sdev
)
321 struct sof_intel_hda_dev
*hda
= sdev
->pdata
->hw_pdata
;
322 const struct sof_intel_dsp_desc
*chip
= hda
->desc
;
324 /* disable IPC interrupt */
325 snd_sof_dsp_update_bits(sdev
, HDA_DSP_BAR
, HDA_DSP_REG_ADSPIC
,
326 HDA_DSP_ADSPIC_IPC
, 0);
328 /* disable IPC BUSY and DONE interrupt */
329 snd_sof_dsp_update_bits(sdev
, HDA_DSP_BAR
, chip
->ipc_ctl
,
330 HDA_DSP_REG_HIPCCTL_BUSY
| HDA_DSP_REG_HIPCCTL_DONE
, 0);
333 static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev
*sdev
)
335 struct hdac_bus
*bus
= sof_to_bus(sdev
);
336 int retry
= HDA_DSP_REG_POLL_RETRY_COUNT
;
338 while (snd_hdac_chip_readb(bus
, VS_D0I3C
) & SOF_HDA_VS_D0I3C_CIP
) {
341 usleep_range(10, 15);
347 static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev
*sdev
, u32 flags
)
349 struct sof_ipc_pm_gate pm_gate
;
350 struct sof_ipc_reply reply
;
352 memset(&pm_gate
, 0, sizeof(pm_gate
));
354 /* configure pm_gate ipc message */
355 pm_gate
.hdr
.size
= sizeof(pm_gate
);
356 pm_gate
.hdr
.cmd
= SOF_IPC_GLB_PM_MSG
| SOF_IPC_PM_GATE
;
357 pm_gate
.flags
= flags
;
359 /* send pm_gate ipc to dsp */
360 return sof_ipc_tx_message_no_pm(sdev
->ipc
, pm_gate
.hdr
.cmd
,
361 &pm_gate
, sizeof(pm_gate
), &reply
,
365 static int hda_dsp_update_d0i3c_register(struct snd_sof_dev
*sdev
, u8 value
)
367 struct hdac_bus
*bus
= sof_to_bus(sdev
);
370 /* Write to D0I3C after Command-In-Progress bit is cleared */
371 ret
= hda_dsp_wait_d0i3c_done(sdev
);
373 dev_err(bus
->dev
, "CIP timeout before D0I3C update!\n");
377 /* Update D0I3C register */
378 snd_hdac_chip_updateb(bus
, VS_D0I3C
, SOF_HDA_VS_D0I3C_I3
, value
);
380 /* Wait for cmd in progress to be cleared before exiting the function */
381 ret
= hda_dsp_wait_d0i3c_done(sdev
);
383 dev_err(bus
->dev
, "CIP timeout after D0I3C update!\n");
387 dev_vdbg(bus
->dev
, "D0I3C updated, register = 0x%x\n",
388 snd_hdac_chip_readb(bus
, VS_D0I3C
));
393 static int hda_dsp_set_D0_state(struct snd_sof_dev
*sdev
,
394 const struct sof_dsp_power_state
*target_state
)
401 * Sanity check for illegal state transitions
402 * The only allowed transitions are:
407 switch (sdev
->dsp_power_state
.state
) {
409 /* Follow the sequence below for D0 substate transitions */
412 /* Follow regular flow for D3 -> D0 transition */
415 dev_err(sdev
->dev
, "error: transition from %d to %d not allowed\n",
416 sdev
->dsp_power_state
.state
, target_state
->state
);
420 /* Set flags and register value for D0 target substate */
421 if (target_state
->substate
== SOF_HDA_DSP_PM_D0I3
) {
422 value
= SOF_HDA_VS_D0I3C_I3
;
425 * Trace DMA need to be disabled when the DSP enters
426 * D0I3 for S0Ix suspend, but it can be kept enabled
427 * when the DSP enters D0I3 while the system is in S0
430 if (!sdev
->dtrace_is_supported
||
431 !hda_enable_trace_D0I3_S0
||
432 sdev
->system_suspend_target
!= SOF_SUSPEND_NONE
)
433 flags
= HDA_PM_NO_DMA_TRACE
;
435 /* prevent power gating in D0I0 */
439 /* update D0I3C register */
440 ret
= hda_dsp_update_d0i3c_register(sdev
, value
);
445 * Notify the DSP of the state change.
446 * If this IPC fails, revert the D0I3C register update in order
447 * to prevent partial state change.
449 ret
= hda_dsp_send_pm_gate_ipc(sdev
, flags
);
452 "error: PM_GATE ipc error %d\n", ret
);
459 /* fallback to the previous register value */
460 value
= value
? 0 : SOF_HDA_VS_D0I3C_I3
;
463 * This can fail but return the IPC error to signal that
464 * the state change failed.
466 hda_dsp_update_d0i3c_register(sdev
, value
);
471 /* helper to log DSP state */
472 static void hda_dsp_state_log(struct snd_sof_dev
*sdev
)
474 switch (sdev
->dsp_power_state
.state
) {
476 switch (sdev
->dsp_power_state
.substate
) {
477 case SOF_HDA_DSP_PM_D0I0
:
478 dev_dbg(sdev
->dev
, "Current DSP power state: D0I0\n");
480 case SOF_HDA_DSP_PM_D0I3
:
481 dev_dbg(sdev
->dev
, "Current DSP power state: D0I3\n");
484 dev_dbg(sdev
->dev
, "Unknown DSP D0 substate: %d\n",
485 sdev
->dsp_power_state
.substate
);
490 dev_dbg(sdev
->dev
, "Current DSP power state: D1\n");
493 dev_dbg(sdev
->dev
, "Current DSP power state: D2\n");
495 case SOF_DSP_PM_D3_HOT
:
496 dev_dbg(sdev
->dev
, "Current DSP power state: D3_HOT\n");
499 dev_dbg(sdev
->dev
, "Current DSP power state: D3\n");
501 case SOF_DSP_PM_D3_COLD
:
502 dev_dbg(sdev
->dev
, "Current DSP power state: D3_COLD\n");
505 dev_dbg(sdev
->dev
, "Unknown DSP power state: %d\n",
506 sdev
->dsp_power_state
.state
);
512 * All DSP power state transitions are initiated by the driver.
513 * If the requested state change fails, the error is simply returned.
514 * Further state transitions are attempted only when the set_power_save() op
515 * is called again either because of a new IPC sent to the DSP or
516 * during system suspend/resume.
518 int hda_dsp_set_power_state(struct snd_sof_dev
*sdev
,
519 const struct sof_dsp_power_state
*target_state
)
524 * When the DSP is already in D0I3 and the target state is D0I3,
525 * it could be the case that the DSP is in D0I3 during S0
526 * and the system is suspending to S0Ix. Therefore,
527 * hda_dsp_set_D0_state() must be called to disable trace DMA
528 * by sending the PM_GATE IPC to the FW.
530 if (target_state
->substate
== SOF_HDA_DSP_PM_D0I3
&&
531 sdev
->system_suspend_target
== SOF_SUSPEND_S0IX
)
535 * For all other cases, return without doing anything if
536 * the DSP is already in the target state.
538 if (target_state
->state
== sdev
->dsp_power_state
.state
&&
539 target_state
->substate
== sdev
->dsp_power_state
.substate
)
543 switch (target_state
->state
) {
545 ret
= hda_dsp_set_D0_state(sdev
, target_state
);
548 /* The only allowed transition is: D0I0 -> D3 */
549 if (sdev
->dsp_power_state
.state
== SOF_DSP_PM_D0
&&
550 sdev
->dsp_power_state
.substate
== SOF_HDA_DSP_PM_D0I0
)
554 "error: transition from %d to %d not allowed\n",
555 sdev
->dsp_power_state
.state
, target_state
->state
);
558 dev_err(sdev
->dev
, "error: target state unsupported %d\n",
559 target_state
->state
);
564 "failed to set requested target DSP state %d substate %d\n",
565 target_state
->state
, target_state
->substate
);
569 sdev
->dsp_power_state
= *target_state
;
570 hda_dsp_state_log(sdev
);
575 * Audio DSP states may transform as below:-
577 * Opportunistic D0I3 in S0
578 * Runtime +---------------------+ Delayed D0i3 work timeout
579 * suspend | +--------------------+
580 * +------------+ D0I0(active) | |
581 * | | <---------------+ |
582 * | +--------> | New IPC | |
583 * | |Runtime +--^--+---------^--+--+ (via mailbox) | |
584 * | |resume | | | | | |
586 * | | System| | | | | |
587 * | | resume| | S3/S0IX | | | |
588 * | | | | suspend | | S0IX | |
589 * | | | | | |suspend | |
592 * +-v---+-----------+--v-------+ | | +------+----v----+
593 * | | | +-----------> |
594 * | D3 (suspended) | | | D0I3 |
595 * | | +--------------+ |
596 * | | System resume | |
597 * +----------------------------+ +----------------+
599 * S0IX suspend: The DSP is in D0I3 if any D0I3-compatible streams
600 * ignored the suspend trigger. Otherwise the DSP
604 static int hda_suspend(struct snd_sof_dev
*sdev
, bool runtime_suspend
)
606 struct sof_intel_hda_dev
*hda
= sdev
->pdata
->hw_pdata
;
607 const struct sof_intel_dsp_desc
*chip
= hda
->desc
;
608 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
609 struct hdac_bus
*bus
= sof_to_bus(sdev
);
613 hda_sdw_int_enable(sdev
, false);
615 /* disable IPC interrupts */
616 hda_dsp_ipc_int_disable(sdev
);
618 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
620 hda_codec_jack_wake_enable(sdev
, true);
622 /* power down all hda link */
623 snd_hdac_ext_bus_link_power_down_all(bus
);
627 ret
= hda_dsp_core_reset_power_down(sdev
, chip
->host_managed_cores_mask
);
630 "error: failed to power down core during suspend\n");
634 /* disable ppcap interrupt */
635 hda_dsp_ctrl_ppcap_enable(sdev
, false);
636 hda_dsp_ctrl_ppcap_int_enable(sdev
, false);
638 /* disable hda bus irq and streams */
639 hda_dsp_ctrl_stop_chip(sdev
);
641 /* disable LP retention mode */
642 snd_sof_pci_update_bits(sdev
, PCI_PGCTL
,
643 PCI_PGCTL_LSRMD_MASK
, PCI_PGCTL_LSRMD_MASK
);
645 /* reset controller */
646 ret
= hda_dsp_ctrl_link_reset(sdev
, true);
649 "error: failed to reset controller during suspend\n");
653 /* display codec can powered off after link reset */
654 hda_codec_i915_display_power(sdev
, false);
659 static int hda_resume(struct snd_sof_dev
*sdev
, bool runtime_resume
)
661 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
662 struct hdac_bus
*bus
= sof_to_bus(sdev
);
663 struct hdac_ext_link
*hlink
= NULL
;
667 /* display codec must be powered before link reset */
668 hda_codec_i915_display_power(sdev
, true);
671 * clear TCSEL to clear playback on some HD Audio
672 * codecs. PCI TCSEL is defined in the Intel manuals.
674 snd_sof_pci_update_bits(sdev
, PCI_TCSEL
, 0x07, 0);
676 /* reset and start hda controller */
677 ret
= hda_dsp_ctrl_init_chip(sdev
, true);
680 "error: failed to start controller after resume\n");
684 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
685 /* check jack status */
686 if (runtime_resume
) {
687 hda_codec_jack_wake_enable(sdev
, false);
688 hda_codec_jack_check(sdev
);
691 /* turn off the links that were off before suspend */
692 list_for_each_entry(hlink
, &bus
->hlink_list
, list
) {
693 if (!hlink
->ref_count
)
694 snd_hdac_ext_bus_link_power_down(hlink
);
697 /* check dma status and clean up CORB/RIRB buffers */
698 if (!bus
->cmd_dma_state
)
699 snd_hdac_bus_stop_cmd_io(bus
);
702 /* enable ppcap interrupt */
703 hda_dsp_ctrl_ppcap_enable(sdev
, true);
704 hda_dsp_ctrl_ppcap_int_enable(sdev
, true);
709 int hda_dsp_resume(struct snd_sof_dev
*sdev
)
711 struct sof_intel_hda_dev
*hda
= sdev
->pdata
->hw_pdata
;
712 struct pci_dev
*pci
= to_pci_dev(sdev
->dev
);
713 const struct sof_dsp_power_state target_state
= {
714 .state
= SOF_DSP_PM_D0
,
715 .substate
= SOF_HDA_DSP_PM_D0I0
,
717 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
718 struct hdac_bus
*bus
= sof_to_bus(sdev
);
719 struct hdac_ext_link
*hlink
= NULL
;
723 /* resume from D0I3 */
724 if (sdev
->dsp_power_state
.state
== SOF_DSP_PM_D0
) {
725 hda_codec_i915_display_power(sdev
, true);
727 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
728 /* power up links that were active before suspend */
729 list_for_each_entry(hlink
, &bus
->hlink_list
, list
) {
730 if (hlink
->ref_count
) {
731 ret
= snd_hdac_ext_bus_link_power_up(hlink
);
734 "error %x in %s: failed to power up links",
741 /* set up CORB/RIRB buffers if was on before suspend */
742 if (bus
->cmd_dma_state
)
743 snd_hdac_bus_init_cmd_io(bus
);
746 /* Set DSP power state */
747 ret
= snd_sof_dsp_set_power_state(sdev
, &target_state
);
749 dev_err(sdev
->dev
, "error: setting dsp state %d substate %d\n",
750 target_state
.state
, target_state
.substate
);
754 /* restore L1SEN bit */
755 if (hda
->l1_support_changed
)
756 snd_sof_dsp_update_bits(sdev
, HDA_DSP_HDA_BAR
,
758 HDA_VS_INTEL_EM2_L1SEN
, 0);
760 /* restore and disable the system wakeup */
761 pci_restore_state(pci
);
762 disable_irq_wake(pci
->irq
);
766 /* init hda controller. DSP cores will be powered up during fw boot */
767 ret
= hda_resume(sdev
, false);
771 return snd_sof_dsp_set_power_state(sdev
, &target_state
);
774 int hda_dsp_runtime_resume(struct snd_sof_dev
*sdev
)
776 const struct sof_dsp_power_state target_state
= {
777 .state
= SOF_DSP_PM_D0
,
781 /* init hda controller. DSP cores will be powered up during fw boot */
782 ret
= hda_resume(sdev
, true);
786 return snd_sof_dsp_set_power_state(sdev
, &target_state
);
789 int hda_dsp_runtime_idle(struct snd_sof_dev
*sdev
)
791 struct hdac_bus
*hbus
= sof_to_bus(sdev
);
793 if (hbus
->codec_powered
) {
794 dev_dbg(sdev
->dev
, "some codecs still powered (%08X), not idle\n",
795 (unsigned int)hbus
->codec_powered
);
802 int hda_dsp_runtime_suspend(struct snd_sof_dev
*sdev
)
804 const struct sof_dsp_power_state target_state
= {
805 .state
= SOF_DSP_PM_D3
,
809 /* stop hda controller and power dsp off */
810 ret
= hda_suspend(sdev
, true);
814 return snd_sof_dsp_set_power_state(sdev
, &target_state
);
817 int hda_dsp_suspend(struct snd_sof_dev
*sdev
, u32 target_state
)
819 struct sof_intel_hda_dev
*hda
= sdev
->pdata
->hw_pdata
;
820 struct hdac_bus
*bus
= sof_to_bus(sdev
);
821 struct pci_dev
*pci
= to_pci_dev(sdev
->dev
);
822 const struct sof_dsp_power_state target_dsp_state
= {
823 .state
= target_state
,
824 .substate
= target_state
== SOF_DSP_PM_D0
?
825 SOF_HDA_DSP_PM_D0I3
: 0,
829 /* cancel any attempt for DSP D0I3 */
830 cancel_delayed_work_sync(&hda
->d0i3_work
);
832 if (target_state
== SOF_DSP_PM_D0
) {
833 /* we can't keep a wakeref to display driver at suspend */
834 hda_codec_i915_display_power(sdev
, false);
836 /* Set DSP power state */
837 ret
= snd_sof_dsp_set_power_state(sdev
, &target_dsp_state
);
839 dev_err(sdev
->dev
, "error: setting dsp state %d substate %d\n",
840 target_dsp_state
.state
,
841 target_dsp_state
.substate
);
845 /* enable L1SEN to make sure the system can enter S0Ix */
846 hda
->l1_support_changed
=
847 snd_sof_dsp_update_bits(sdev
, HDA_DSP_HDA_BAR
,
849 HDA_VS_INTEL_EM2_L1SEN
,
850 HDA_VS_INTEL_EM2_L1SEN
);
852 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
853 /* stop the CORB/RIRB DMA if it is On */
854 if (bus
->cmd_dma_state
)
855 snd_hdac_bus_stop_cmd_io(bus
);
857 /* no link can be powered in s0ix state */
858 ret
= snd_hdac_ext_bus_link_power_down_all(bus
);
861 "error %d in %s: failed to power down links",
867 /* enable the system waking up via IPC IRQ */
868 enable_irq_wake(pci
->irq
);
873 /* stop hda controller and power dsp off */
874 ret
= hda_suspend(sdev
, false);
876 dev_err(bus
->dev
, "error: suspending dsp\n");
880 return snd_sof_dsp_set_power_state(sdev
, &target_dsp_state
);
883 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev
*sdev
)
885 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
886 struct hdac_bus
*bus
= sof_to_bus(sdev
);
887 struct snd_soc_pcm_runtime
*rtd
;
888 struct hdac_ext_stream
*stream
;
889 struct hdac_ext_link
*link
;
890 struct hdac_stream
*s
;
894 /* set internal flag for BE */
895 list_for_each_entry(s
, &bus
->stream_list
, list
) {
896 stream
= stream_to_hdac_ext_stream(s
);
899 * clear stream. This should already be taken care for running
900 * streams when the SUSPEND trigger is called. But paused
901 * streams do not get suspended, so this needs to be done
902 * explicitly during suspend.
904 if (stream
->link_substream
) {
905 rtd
= asoc_substream_to_rtd(stream
->link_substream
);
906 name
= asoc_rtd_to_codec(rtd
, 0)->component
->name
;
907 link
= snd_hdac_ext_bus_get_link(bus
, name
);
911 stream
->link_prepared
= 0;
913 if (hdac_stream(stream
)->direction
==
914 SNDRV_PCM_STREAM_CAPTURE
)
917 stream_tag
= hdac_stream(stream
)->stream_tag
;
918 snd_hdac_ext_link_clear_stream_id(link
, stream_tag
);
925 void hda_dsp_d0i3_work(struct work_struct
*work
)
927 struct sof_intel_hda_dev
*hdev
= container_of(work
,
928 struct sof_intel_hda_dev
,
930 struct hdac_bus
*bus
= &hdev
->hbus
.core
;
931 struct snd_sof_dev
*sdev
= dev_get_drvdata(bus
->dev
);
932 struct sof_dsp_power_state target_state
;
935 target_state
.state
= SOF_DSP_PM_D0
;
937 /* DSP can enter D0I3 iff only D0I3-compatible streams are active */
938 if (snd_sof_dsp_only_d0i3_compatible_stream_active(sdev
))
939 target_state
.substate
= SOF_HDA_DSP_PM_D0I3
;
941 target_state
.substate
= SOF_HDA_DSP_PM_D0I0
;
944 if (target_state
.substate
== SOF_HDA_DSP_PM_D0I0
)
947 /* This can fail but error cannot be propagated */
948 ret
= snd_sof_dsp_set_power_state(sdev
, &target_state
);
950 dev_err_ratelimited(sdev
->dev
,
951 "error: failed to set DSP state %d substate %d\n",
952 target_state
.state
, target_state
.substate
);