sound/soc/sunxi/sun4i-codec.c

   1 /*
   2  * Copyright 2014 Emilio López <emilio@elopez.com.ar>
   3  * Copyright 2014 Jon Smirl <jonsmirl@gmail.com>
   4  * Copyright 2015 Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * Based on the Allwinner SDK driver, released under the GPL.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/delay.h>
  24 #include <linux/slab.h>
  25 #include <linux/of.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/of_address.h>
  28 #include <linux/clk.h>
  29 #include <linux/regmap.h>
  30
  31 #include <sound/core.h>
  32 #include <sound/pcm.h>
  33 #include <sound/pcm_params.h>
  34 #include <sound/soc.h>
  35 #include <sound/tlv.h>
  36 #include <sound/initval.h>
  37 #include <sound/dmaengine_pcm.h>
  38
  39 /* Codec DAC register offsets and bit fields */
  40 #define SUN4I_CODEC_DAC_DPC                     (0x00)
  41 #define SUN4I_CODEC_DAC_DPC_EN_DA                       (31)
  42 #define SUN4I_CODEC_DAC_DPC_DVOL                        (12)
  43 #define SUN4I_CODEC_DAC_FIFOC                   (0x04)
  44 #define SUN4I_CODEC_DAC_FIFOC_DAC_FS                    (29)
  45 #define SUN4I_CODEC_DAC_FIFOC_FIR_VERSION               (28)
  46 #define SUN4I_CODEC_DAC_FIFOC_SEND_LASAT                (26)
  47 #define SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE              (24)
  48 #define SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT               (21)
  49 #define SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL             (8)
  50 #define SUN4I_CODEC_DAC_FIFOC_MONO_EN                   (6)
  51 #define SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS            (5)
  52 #define SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN                (4)
  53 #define SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH                (0)
  54 #define SUN4I_CODEC_DAC_FIFOS                   (0x08)
  55 #define SUN4I_CODEC_DAC_TXDATA                  (0x0c)
  56 #define SUN4I_CODEC_DAC_ACTL                    (0x10)
  57 #define SUN4I_CODEC_DAC_ACTL_DACAENR                    (31)
  58 #define SUN4I_CODEC_DAC_ACTL_DACAENL                    (30)
  59 #define SUN4I_CODEC_DAC_ACTL_MIXEN                      (29)
  60 #define SUN4I_CODEC_DAC_ACTL_LDACLMIXS                  (15)
  61 #define SUN4I_CODEC_DAC_ACTL_RDACRMIXS                  (14)
  62 #define SUN4I_CODEC_DAC_ACTL_LDACRMIXS                  (13)
  63 #define SUN4I_CODEC_DAC_ACTL_DACPAS                     (8)
  64 #define SUN4I_CODEC_DAC_ACTL_MIXPAS                     (7)
  65 #define SUN4I_CODEC_DAC_ACTL_PA_MUTE                    (6)
  66 #define SUN4I_CODEC_DAC_ACTL_PA_VOL                     (0)
  67 #define SUN4I_CODEC_DAC_TUNE                    (0x14)
  68 #define SUN4I_CODEC_DAC_DEBUG                   (0x18)
  69
  70 /* Codec ADC register offsets and bit fields */
  71 #define SUN4I_CODEC_ADC_FIFOC                   (0x1c)
  72 #define SUN4I_CODEC_ADC_FIFOC_ADC_FS                    (29)
  73 #define SUN4I_CODEC_ADC_FIFOC_EN_AD                     (28)
  74 #define SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE              (24)
  75 #define SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL             (8)
  76 #define SUN4I_CODEC_ADC_FIFOC_MONO_EN                   (7)
  77 #define SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS            (6)
  78 #define SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN                (4)
  79 #define SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH                (0)
  80 #define SUN4I_CODEC_ADC_FIFOS                   (0x20)
  81 #define SUN4I_CODEC_ADC_RXDATA                  (0x24)
  82 #define SUN4I_CODEC_ADC_ACTL                    (0x28)
  83 #define SUN4I_CODEC_ADC_ACTL_ADC_R_EN                   (31)
  84 #define SUN4I_CODEC_ADC_ACTL_ADC_L_EN                   (30)
  85 #define SUN4I_CODEC_ADC_ACTL_PREG1EN                    (29)
  86 #define SUN4I_CODEC_ADC_ACTL_PREG2EN                    (28)
  87 #define SUN4I_CODEC_ADC_ACTL_VMICEN                     (27)
  88 #define SUN4I_CODEC_ADC_ACTL_VADCG                      (20)
  89 #define SUN4I_CODEC_ADC_ACTL_ADCIS                      (17)
  90 #define SUN4I_CODEC_ADC_ACTL_PA_EN                      (4)
  91 #define SUN4I_CODEC_ADC_ACTL_DDE                        (3)
  92 #define SUN4I_CODEC_ADC_DEBUG                   (0x2c)
  93
  94 /* Other various ADC registers */
  95 #define SUN4I_CODEC_DAC_TXCNT                   (0x30)
  96 #define SUN4I_CODEC_ADC_RXCNT                   (0x34)
  97 #define SUN4I_CODEC_AC_SYS_VERI                 (0x38)
  98 #define SUN4I_CODEC_AC_MIC_PHONE_CAL            (0x3c)
  99
 100 struct sun4i_codec {
 101         struct device   *dev;
 102         struct regmap   *regmap;
 103         struct clk      *clk_apb;
 104         struct clk      *clk_module;
 105
 106         struct snd_dmaengine_dai_dma_data       capture_dma_data;
 107         struct snd_dmaengine_dai_dma_data       playback_dma_data;
 108 };
 109
 110 static void sun4i_codec_start_playback(struct sun4i_codec *scodec)
 111 {
 112         /* Flush TX FIFO */
 113         regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
 114                            BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH),
 115                            BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
 116
 117         /* Enable DAC DRQ */
 118         regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
 119                            BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN),
 120                            BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
 121 }
 122
 123 static void sun4i_codec_stop_playback(struct sun4i_codec *scodec)
 124 {
 125         /* Disable DAC DRQ */
 126         regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
 127                            BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN),
 128                            0);
 129 }
 130
 131 static void sun4i_codec_start_capture(struct sun4i_codec *scodec)
 132 {
 133         /* Enable ADC DRQ */
 134         regmap_update_bits(scodec->regmap, SUN4I_CODEC_ADC_FIFOC,
 135                            BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN),
 136                            BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN));
 137 }
 138
 139 static void sun4i_codec_stop_capture(struct sun4i_codec *scodec)
 140 {
 141         /* Disable ADC DRQ */
 142         regmap_update_bits(scodec->regmap, SUN4I_CODEC_ADC_FIFOC,
 143                            BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN), 0);
 144 }
 145
 146 static int sun4i_codec_trigger(struct snd_pcm_substream *substream, int cmd,
 147                                struct snd_soc_dai *dai)
 148 {
 149         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 150         struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
 151
 152         switch (cmd) {
 153         case SNDRV_PCM_TRIGGER_START:
 154         case SNDRV_PCM_TRIGGER_RESUME:
 155         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 156                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 157                         sun4i_codec_start_playback(scodec);
 158                 else
 159                         sun4i_codec_start_capture(scodec);
 160                 break;
 161
 162         case SNDRV_PCM_TRIGGER_STOP:
 163         case SNDRV_PCM_TRIGGER_SUSPEND:
 164         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 165                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 166                         sun4i_codec_stop_playback(scodec);
 167                 else
 168                         sun4i_codec_stop_capture(scodec);
 169                 break;
 170
 171         default:
 172                 return -EINVAL;
 173         }
 174
 175         return 0;
 176 }
 177
 178 static int sun4i_codec_prepare_capture(struct snd_pcm_substream *substream,
 179                                        struct snd_soc_dai *dai)
 180 {
 181         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 182         struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
 183
 184
 185         /* Flush RX FIFO */
 186         regmap_update_bits(scodec->regmap, SUN4I_CODEC_ADC_FIFOC,
 187                            BIT(SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH),
 188                            BIT(SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH));
 189
 190
 191         /* Set RX FIFO trigger level */
 192         regmap_update_bits(scodec->regmap, SUN4I_CODEC_ADC_FIFOC,
 193                            0xf << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
 194                            0x7 << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL);
 195
 196         /*
 197          * FIXME: Undocumented in the datasheet, but
 198          *        Allwinner's code mentions that it is related
 199          *        related to microphone gain
 200          */
 201         regmap_update_bits(scodec->regmap, SUN4I_CODEC_ADC_ACTL,
 202                            0x3 << 25,
 203                            0x1 << 25);
 204
 205         if (of_device_is_compatible(scodec->dev->of_node,
 206                                     "allwinner,sun7i-a20-codec"))
 207                 /* FIXME: Undocumented bits */
 208                 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_TUNE,
 209                                    0x3 << 8,
 210                                    0x1 << 8);
 211
 212         /* Fill most significant bits with valid data MSB */
 213         regmap_update_bits(scodec->regmap, SUN4I_CODEC_ADC_FIFOC,
 214                            BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE),
 215                            BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE));
 216
 217         return 0;
 218 }
 219
 220 static int sun4i_codec_prepare_playback(struct snd_pcm_substream *substream,
 221                                         struct snd_soc_dai *dai)
 222 {
 223         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 224         struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
 225         u32 val;
 226
 227         /* Flush the TX FIFO */
 228         regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
 229                            BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH),
 230                            BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
 231
 232         /* Set TX FIFO Empty Trigger Level */
 233         regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
 234                            0x3f << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL,
 235                            0xf << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL);
 236
 237         if (substream->runtime->rate > 32000)
 238                 /* Use 64 bits FIR filter */
 239                 val = 0;
 240         else
 241                 /* Use 32 bits FIR filter */
 242                 val = BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION);
 243
 244         regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
 245                            BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION),
 246                            val);
 247
 248         /* Send zeros when we have an underrun */
 249         regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
 250                            BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT),
 251                            0);
 252
 253         return 0;
 254 };
 255
 256 static int sun4i_codec_prepare(struct snd_pcm_substream *substream,
 257                                struct snd_soc_dai *dai)
 258 {
 259         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 260                 return sun4i_codec_prepare_playback(substream, dai);
 261
 262         return sun4i_codec_prepare_capture(substream, dai);
 263 }
 264
 265 static unsigned long sun4i_codec_get_mod_freq(struct snd_pcm_hw_params *params)
 266 {
 267         unsigned int rate = params_rate(params);
 268
 269         switch (rate) {
 270         case 176400:
 271         case 88200:
 272         case 44100:
 273         case 33075:
 274         case 22050:
 275         case 14700:
 276         case 11025:
 277         case 7350:
 278                 return 22579200;
 279
 280         case 192000:
 281         case 96000:
 282         case 48000:
 283         case 32000:
 284         case 24000:
 285         case 16000:
 286         case 12000:
 287         case 8000:
 288                 return 24576000;
 289
 290         default:
 291                 return 0;
 292         }
 293 }
 294
 295 static int sun4i_codec_get_hw_rate(struct snd_pcm_hw_params *params)
 296 {
 297         unsigned int rate = params_rate(params);
 298
 299         switch (rate) {
 300         case 192000:
 301         case 176400:
 302                 return 6;
 303
 304         case 96000:
 305         case 88200:
 306                 return 7;
 307
 308         case 48000:
 309         case 44100:
 310                 return 0;
 311
 312         case 32000:
 313         case 33075:
 314                 return 1;
 315
 316         case 24000:
 317         case 22050:
 318                 return 2;
 319
 320         case 16000:
 321         case 14700:
 322                 return 3;
 323
 324         case 12000:
 325         case 11025:
 326                 return 4;
 327
 328         case 8000:
 329         case 7350:
 330                 return 5;
 331
 332         default:
 333                 return -EINVAL;
 334         }
 335 }
 336
 337 static int sun4i_codec_hw_params_capture(struct sun4i_codec *scodec,
 338                                          struct snd_pcm_hw_params *params,
 339                                          unsigned int hwrate)
 340 {
 341         /* Set ADC sample rate */
 342         regmap_update_bits(scodec->regmap, SUN4I_CODEC_ADC_FIFOC,
 343                            7 << SUN4I_CODEC_ADC_FIFOC_ADC_FS,
 344                            hwrate << SUN4I_CODEC_ADC_FIFOC_ADC_FS);
 345
 346         /* Set the number of channels we want to use */
 347         if (params_channels(params) == 1)
 348                 regmap_update_bits(scodec->regmap, SUN4I_CODEC_ADC_FIFOC,
 349                                    BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN),
 350                                    BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN));
 351         else
 352                 regmap_update_bits(scodec->regmap, SUN4I_CODEC_ADC_FIFOC,
 353                                    BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN), 0);
 354
 355         return 0;
 356 }
 357
 358 static int sun4i_codec_hw_params_playback(struct sun4i_codec *scodec,
 359                                           struct snd_pcm_hw_params *params,
 360                                           unsigned int hwrate)
 361 {
 362         u32 val;
 363
 364         /* Set DAC sample rate */
 365         regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
 366                            7 << SUN4I_CODEC_DAC_FIFOC_DAC_FS,
 367                            hwrate << SUN4I_CODEC_DAC_FIFOC_DAC_FS);
 368
 369         /* Set the number of channels we want to use */
 370         if (params_channels(params) == 1)
 371                 val = BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN);
 372         else
 373                 val = 0;
 374
 375         regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
 376                            BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN),
 377                            val);
 378
 379         /* Set the number of sample bits to either 16 or 24 bits */
 380         if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) {
 381                 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
 382                                    BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS),
 383                                    BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
 384
 385                 /* Set TX FIFO mode to padding the LSBs with 0 */
 386                 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
 387                                    BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE),
 388                                    0);
 389
 390                 scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 391         } else {
 392                 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
 393                                    BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS),
 394                                    0);
 395
 396                 /* Set TX FIFO mode to repeat the MSB */
 397                 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
 398                                    BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE),
 399                                    BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
 400
 401                 scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 402         }
 403
 404         return 0;
 405 }
 406
 407 static int sun4i_codec_hw_params(struct snd_pcm_substream *substream,
 408                                  struct snd_pcm_hw_params *params,
 409                                  struct snd_soc_dai *dai)
 410 {
 411         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 412         struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
 413         unsigned long clk_freq;
 414         int ret, hwrate;
 415
 416         clk_freq = sun4i_codec_get_mod_freq(params);
 417         if (!clk_freq)
 418                 return -EINVAL;
 419
 420         ret = clk_set_rate(scodec->clk_module, clk_freq);
 421         if (ret)
 422                 return ret;
 423
 424         hwrate = sun4i_codec_get_hw_rate(params);
 425         if (hwrate < 0)
 426                 return hwrate;
 427
 428         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 429                 return sun4i_codec_hw_params_playback(scodec, params,
 430                                                       hwrate);
 431
 432         return sun4i_codec_hw_params_capture(scodec, params,
 433                                              hwrate);
 434 }
 435
 436 static int sun4i_codec_startup(struct snd_pcm_substream *substream,
 437                                struct snd_soc_dai *dai)
 438 {
 439         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 440         struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
 441
 442         /*
 443          * Stop issuing DRQ when we have room for less than 16 samples
 444          * in our TX FIFO
 445          */
 446         regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
 447                            3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT,
 448                            3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT);
 449
 450         return clk_prepare_enable(scodec->clk_module);
 451 }
 452
 453 static void sun4i_codec_shutdown(struct snd_pcm_substream *substream,
 454                                  struct snd_soc_dai *dai)
 455 {
 456         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 457         struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
 458
 459         clk_disable_unprepare(scodec->clk_module);
 460 }
 461
 462 static const struct snd_soc_dai_ops sun4i_codec_dai_ops = {
 463         .startup        = sun4i_codec_startup,
 464         .shutdown       = sun4i_codec_shutdown,
 465         .trigger        = sun4i_codec_trigger,
 466         .hw_params      = sun4i_codec_hw_params,
 467         .prepare        = sun4i_codec_prepare,
 468 };
 469
 470 static struct snd_soc_dai_driver sun4i_codec_dai = {
 471         .name   = "Codec",
 472         .ops    = &sun4i_codec_dai_ops,
 473         .playback = {
 474                 .stream_name    = "Codec Playback",
 475                 .channels_min   = 1,
 476                 .channels_max   = 2,
 477                 .rate_min       = 8000,
 478                 .rate_max       = 192000,
 479                 .rates          = SNDRV_PCM_RATE_8000_48000 |
 480                                   SNDRV_PCM_RATE_96000 |
 481                                   SNDRV_PCM_RATE_192000,
 482                 .formats        = SNDRV_PCM_FMTBIT_S16_LE |
 483                                   SNDRV_PCM_FMTBIT_S32_LE,
 484                 .sig_bits       = 24,
 485         },
 486         .capture = {
 487                 .stream_name    = "Codec Capture",
 488                 .channels_min   = 1,
 489                 .channels_max   = 2,
 490                 .rate_min       = 8000,
 491                 .rate_max       = 192000,
 492                 .rates          = SNDRV_PCM_RATE_8000_48000 |
 493                                   SNDRV_PCM_RATE_96000 |
 494                                   SNDRV_PCM_RATE_192000 |
 495                                   SNDRV_PCM_RATE_KNOT,
 496                 .formats        = SNDRV_PCM_FMTBIT_S16_LE |
 497                                   SNDRV_PCM_FMTBIT_S32_LE,
 498                 .sig_bits       = 24,
 499         },
 500 };
 501
 502 /*** Codec ***/
 503 static const struct snd_kcontrol_new sun4i_codec_pa_mute =
 504         SOC_DAPM_SINGLE("Switch", SUN4I_CODEC_DAC_ACTL,
 505                         SUN4I_CODEC_DAC_ACTL_PA_MUTE, 1, 0);
 506
 507 static DECLARE_TLV_DB_SCALE(sun4i_codec_pa_volume_scale, -6300, 100, 1);
 508
 509 static const struct snd_kcontrol_new sun4i_codec_widgets[] = {
 510         SOC_SINGLE_TLV("PA Volume", SUN4I_CODEC_DAC_ACTL,
 511                        SUN4I_CODEC_DAC_ACTL_PA_VOL, 0x3F, 0,
 512                        sun4i_codec_pa_volume_scale),
 513 };
 514
 515 static const struct snd_kcontrol_new sun4i_codec_left_mixer_controls[] = {
 516         SOC_DAPM_SINGLE("Left DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
 517                         SUN4I_CODEC_DAC_ACTL_LDACLMIXS, 1, 0),
 518 };
 519
 520 static const struct snd_kcontrol_new sun4i_codec_right_mixer_controls[] = {
 521         SOC_DAPM_SINGLE("Right DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
 522                         SUN4I_CODEC_DAC_ACTL_RDACRMIXS, 1, 0),
 523         SOC_DAPM_SINGLE("Left DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
 524                         SUN4I_CODEC_DAC_ACTL_LDACRMIXS, 1, 0),
 525 };
 526
 527 static const struct snd_kcontrol_new sun4i_codec_pa_mixer_controls[] = {
 528         SOC_DAPM_SINGLE("DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
 529                         SUN4I_CODEC_DAC_ACTL_DACPAS, 1, 0),
 530         SOC_DAPM_SINGLE("Mixer Playback Switch", SUN4I_CODEC_DAC_ACTL,
 531                         SUN4I_CODEC_DAC_ACTL_MIXPAS, 1, 0),
 532 };
 533
 534 static const struct snd_soc_dapm_widget sun4i_codec_dapm_widgets[] = {
 535         /* Digital parts of the ADCs */
 536         SND_SOC_DAPM_SUPPLY("ADC", SUN4I_CODEC_ADC_FIFOC,
 537                             SUN4I_CODEC_ADC_FIFOC_EN_AD, 0,
 538                             NULL, 0),
 539
 540         /* Digital parts of the DACs */
 541         SND_SOC_DAPM_SUPPLY("DAC", SUN4I_CODEC_DAC_DPC,
 542                             SUN4I_CODEC_DAC_DPC_EN_DA, 0,
 543                             NULL, 0),
 544
 545         /* Analog parts of the ADCs */
 546         SND_SOC_DAPM_ADC("Left ADC", "Codec Capture", SUN4I_CODEC_ADC_ACTL,
 547                          SUN4I_CODEC_ADC_ACTL_ADC_L_EN, 0),
 548         SND_SOC_DAPM_ADC("Right ADC", "Codec Capture", SUN4I_CODEC_ADC_ACTL,
 549                          SUN4I_CODEC_ADC_ACTL_ADC_R_EN, 0),
 550
 551         /* Analog parts of the DACs */
 552         SND_SOC_DAPM_DAC("Left DAC", "Codec Playback", SUN4I_CODEC_DAC_ACTL,
 553                          SUN4I_CODEC_DAC_ACTL_DACAENL, 0),
 554         SND_SOC_DAPM_DAC("Right DAC", "Codec Playback", SUN4I_CODEC_DAC_ACTL,
 555                          SUN4I_CODEC_DAC_ACTL_DACAENR, 0),
 556
 557         /* Mixers */
 558         SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
 559                            sun4i_codec_left_mixer_controls,
 560                            ARRAY_SIZE(sun4i_codec_left_mixer_controls)),
 561         SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
 562                            sun4i_codec_right_mixer_controls,
 563                            ARRAY_SIZE(sun4i_codec_right_mixer_controls)),
 564
 565         /* Global Mixer Enable */
 566         SND_SOC_DAPM_SUPPLY("Mixer Enable", SUN4I_CODEC_DAC_ACTL,
 567                             SUN4I_CODEC_DAC_ACTL_MIXEN, 0, NULL, 0),
 568
 569         /* VMIC */
 570         SND_SOC_DAPM_SUPPLY("VMIC", SUN4I_CODEC_ADC_ACTL,
 571                             SUN4I_CODEC_ADC_ACTL_VMICEN, 0, NULL, 0),
 572
 573         /* Mic Pre-Amplifiers */
 574         SND_SOC_DAPM_PGA("MIC1 Pre-Amplifier", SUN4I_CODEC_ADC_ACTL,
 575                          SUN4I_CODEC_ADC_ACTL_PREG1EN, 0, NULL, 0),
 576
 577         /* Pre-Amplifier */
 578         SND_SOC_DAPM_MIXER("Pre-Amplifier", SUN4I_CODEC_ADC_ACTL,
 579                            SUN4I_CODEC_ADC_ACTL_PA_EN, 0,
 580                            sun4i_codec_pa_mixer_controls,
 581                            ARRAY_SIZE(sun4i_codec_pa_mixer_controls)),
 582         SND_SOC_DAPM_SWITCH("Pre-Amplifier Mute", SND_SOC_NOPM, 0, 0,
 583                             &sun4i_codec_pa_mute),
 584
 585         SND_SOC_DAPM_INPUT("Mic1"),
 586
 587         SND_SOC_DAPM_OUTPUT("HP Right"),
 588         SND_SOC_DAPM_OUTPUT("HP Left"),
 589 };
 590
 591 static const struct snd_soc_dapm_route sun4i_codec_dapm_routes[] = {
 592         /* Left ADC / DAC Routes */
 593         { "Left ADC", NULL, "ADC" },
 594         { "Left DAC", NULL, "DAC" },
 595
 596         /* Right ADC / DAC Routes */
 597         { "Right ADC", NULL, "ADC" },
 598         { "Right DAC", NULL, "DAC" },
 599
 600         /* Right Mixer Routes */
 601         { "Right Mixer", NULL, "Mixer Enable" },
 602         { "Right Mixer", "Left DAC Playback Switch", "Left DAC" },
 603         { "Right Mixer", "Right DAC Playback Switch", "Right DAC" },
 604
 605         /* Left Mixer Routes */
 606         { "Left Mixer", NULL, "Mixer Enable" },
 607         { "Left Mixer", "Left DAC Playback Switch", "Left DAC" },
 608
 609         /* Pre-Amplifier Mixer Routes */
 610         { "Pre-Amplifier", "Mixer Playback Switch", "Left Mixer" },
 611         { "Pre-Amplifier", "Mixer Playback Switch", "Right Mixer" },
 612         { "Pre-Amplifier", "DAC Playback Switch", "Left DAC" },
 613         { "Pre-Amplifier", "DAC Playback Switch", "Right DAC" },
 614
 615         /* PA -> HP path */
 616         { "Pre-Amplifier Mute", "Switch", "Pre-Amplifier" },
 617         { "HP Right", NULL, "Pre-Amplifier Mute" },
 618         { "HP Left", NULL, "Pre-Amplifier Mute" },
 619
 620         /* Mic1 Routes */
 621         { "Left ADC", NULL, "MIC1 Pre-Amplifier" },
 622         { "Right ADC", NULL, "MIC1 Pre-Amplifier" },
 623         { "MIC1 Pre-Amplifier", NULL, "Mic1"},
 624         { "Mic1", NULL, "VMIC" },
 625 };
 626
 627 static struct snd_soc_codec_driver sun4i_codec_codec = {
 628         .controls               = sun4i_codec_widgets,
 629         .num_controls           = ARRAY_SIZE(sun4i_codec_widgets),
 630         .dapm_widgets           = sun4i_codec_dapm_widgets,
 631         .num_dapm_widgets       = ARRAY_SIZE(sun4i_codec_dapm_widgets),
 632         .dapm_routes            = sun4i_codec_dapm_routes,
 633         .num_dapm_routes        = ARRAY_SIZE(sun4i_codec_dapm_routes),
 634 };
 635
 636 static const struct snd_soc_component_driver sun4i_codec_component = {
 637         .name = "sun4i-codec",
 638 };
 639
 640 #define SUN4I_CODEC_RATES       SNDRV_PCM_RATE_8000_192000
 641 #define SUN4I_CODEC_FORMATS     (SNDRV_PCM_FMTBIT_S16_LE | \
 642                                  SNDRV_PCM_FMTBIT_S32_LE)
 643
 644 static int sun4i_codec_dai_probe(struct snd_soc_dai *dai)
 645 {
 646         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
 647         struct sun4i_codec *scodec = snd_soc_card_get_drvdata(card);
 648
 649         snd_soc_dai_init_dma_data(dai, &scodec->playback_dma_data,
 650                                   &scodec->capture_dma_data);
 651
 652         return 0;
 653 }
 654
 655 static struct snd_soc_dai_driver dummy_cpu_dai = {
 656         .name   = "sun4i-codec-cpu-dai",
 657         .probe  = sun4i_codec_dai_probe,
 658         .playback = {
 659                 .stream_name    = "Playback",
 660                 .channels_min   = 1,
 661                 .channels_max   = 2,
 662                 .rates          = SUN4I_CODEC_RATES,
 663                 .formats        = SUN4I_CODEC_FORMATS,
 664                 .sig_bits       = 24,
 665         },
 666         .capture = {
 667                 .stream_name    = "Capture",
 668                 .channels_min   = 1,
 669                 .channels_max   = 2,
 670                 .rates          = SUN4I_CODEC_RATES,
 671                 .formats        = SUN4I_CODEC_FORMATS,
 672                 .sig_bits       = 24,
 673          },
 674 };
 675
 676 static const struct regmap_config sun4i_codec_regmap_config = {
 677         .reg_bits       = 32,
 678         .reg_stride     = 4,
 679         .val_bits       = 32,
 680         .max_register   = SUN4I_CODEC_AC_MIC_PHONE_CAL,
 681 };
 682
 683 static const struct of_device_id sun4i_codec_of_match[] = {
 684         { .compatible = "allwinner,sun4i-a10-codec" },
 685         { .compatible = "allwinner,sun7i-a20-codec" },
 686         {}
 687 };
 688 MODULE_DEVICE_TABLE(of, sun4i_codec_of_match);
 689
 690 static struct snd_soc_dai_link *sun4i_codec_create_link(struct device *dev,
 691                                                         int *num_links)
 692 {
 693         struct snd_soc_dai_link *link = devm_kzalloc(dev, sizeof(*link),
 694                                                      GFP_KERNEL);
 695         if (!link)
 696                 return NULL;
 697
 698         link->name              = "cdc";
 699         link->stream_name       = "CDC PCM";
 700         link->codec_dai_name    = "Codec";
 701         link->cpu_dai_name      = dev_name(dev);
 702         link->codec_name        = dev_name(dev);
 703         link->platform_name     = dev_name(dev);
 704         link->dai_fmt           = SND_SOC_DAIFMT_I2S;
 705
 706         *num_links = 1;
 707
 708         return link;
 709 };
 710
 711 static struct snd_soc_card *sun4i_codec_create_card(struct device *dev)
 712 {
 713         struct snd_soc_card *card;
 714
 715         card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
 716         if (!card)
 717                 return NULL;
 718
 719         card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
 720         if (!card->dai_link)
 721                 return NULL;
 722
 723         card->dev               = dev;
 724         card->name              = "sun4i-codec";
 725
 726         return card;
 727 };
 728
 729 static int sun4i_codec_probe(struct platform_device *pdev)
 730 {
 731         struct snd_soc_card *card;
 732         struct sun4i_codec *scodec;
 733         struct resource *res;
 734         void __iomem *base;
 735         int ret;
 736
 737         scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
 738         if (!scodec)
 739                 return -ENOMEM;
 740
 741         scodec->dev = &pdev->dev;
 742
 743         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 744         base = devm_ioremap_resource(&pdev->dev, res);
 745         if (IS_ERR(base)) {
 746                 dev_err(&pdev->dev, "Failed to map the registers\n");
 747                 return PTR_ERR(base);
 748         }
 749
 750         scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
 751                                              &sun4i_codec_regmap_config);
 752         if (IS_ERR(scodec->regmap)) {
 753                 dev_err(&pdev->dev, "Failed to create our regmap\n");
 754                 return PTR_ERR(scodec->regmap);
 755         }
 756
 757         /* Get the clocks from the DT */
 758         scodec->clk_apb = devm_clk_get(&pdev->dev, "apb");
 759         if (IS_ERR(scodec->clk_apb)) {
 760                 dev_err(&pdev->dev, "Failed to get the APB clock\n");
 761                 return PTR_ERR(scodec->clk_apb);
 762         }
 763
 764         scodec->clk_module = devm_clk_get(&pdev->dev, "codec");
 765         if (IS_ERR(scodec->clk_module)) {
 766                 dev_err(&pdev->dev, "Failed to get the module clock\n");
 767                 return PTR_ERR(scodec->clk_module);
 768         }
 769
 770         /* Enable the bus clock */
 771         if (clk_prepare_enable(scodec->clk_apb)) {
 772                 dev_err(&pdev->dev, "Failed to enable the APB clock\n");
 773                 return -EINVAL;
 774         }
 775
 776         /* DMA configuration for TX FIFO */
 777         scodec->playback_dma_data.addr = res->start + SUN4I_CODEC_DAC_TXDATA;
 778         scodec->playback_dma_data.maxburst = 4;
 779         scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 780
 781         /* DMA configuration for RX FIFO */
 782         scodec->capture_dma_data.addr = res->start + SUN4I_CODEC_ADC_RXDATA;
 783         scodec->capture_dma_data.maxburst = 4;
 784         scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 785
 786         ret = snd_soc_register_codec(&pdev->dev, &sun4i_codec_codec,
 787                                      &sun4i_codec_dai, 1);
 788         if (ret) {
 789                 dev_err(&pdev->dev, "Failed to register our codec\n");
 790                 goto err_clk_disable;
 791         }
 792
 793         ret = devm_snd_soc_register_component(&pdev->dev,
 794                                               &sun4i_codec_component,
 795                                               &dummy_cpu_dai, 1);
 796         if (ret) {
 797                 dev_err(&pdev->dev, "Failed to register our DAI\n");
 798                 goto err_unregister_codec;
 799         }
 800
 801         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 802         if (ret) {
 803                 dev_err(&pdev->dev, "Failed to register against DMAEngine\n");
 804                 goto err_unregister_codec;
 805         }
 806
 807         card = sun4i_codec_create_card(&pdev->dev);
 808         if (!card) {
 809                 dev_err(&pdev->dev, "Failed to create our card\n");
 810                 goto err_unregister_codec;
 811         }
 812
 813         platform_set_drvdata(pdev, card);
 814         snd_soc_card_set_drvdata(card, scodec);
 815
 816         ret = snd_soc_register_card(card);
 817         if (ret) {
 818                 dev_err(&pdev->dev, "Failed to register our card\n");
 819                 goto err_unregister_codec;
 820         }
 821
 822         return 0;
 823
 824 err_unregister_codec:
 825         snd_soc_unregister_codec(&pdev->dev);
 826 err_clk_disable:
 827         clk_disable_unprepare(scodec->clk_apb);
 828         return ret;
 829 }
 830
 831 static int sun4i_codec_remove(struct platform_device *pdev)
 832 {
 833         struct snd_soc_card *card = platform_get_drvdata(pdev);
 834         struct sun4i_codec *scodec = snd_soc_card_get_drvdata(card);
 835
 836         snd_soc_unregister_card(card);
 837         snd_soc_unregister_codec(&pdev->dev);
 838         clk_disable_unprepare(scodec->clk_apb);
 839
 840         return 0;
 841 }
 842
 843 static struct platform_driver sun4i_codec_driver = {
 844         .driver = {
 845                 .name = "sun4i-codec",
 846                 .of_match_table = sun4i_codec_of_match,
 847         },
 848         .probe = sun4i_codec_probe,
 849         .remove = sun4i_codec_remove,
 850 };
 851 module_platform_driver(sun4i_codec_driver);
 852
 853 MODULE_DESCRIPTION("Allwinner A10 codec driver");
 854 MODULE_AUTHOR("Emilio López <emilio@elopez.com.ar>");
 855 MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>");
 856 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
 857 MODULE_LICENSE("GPL");