sound/soc/sunxi/sun8i-codec.c

   1 /*
   2  * This driver supports the digital controls for the internal codec
   3  * found in Allwinner's A33 SoCs.
   4  *
   5  * (C) Copyright 2010-2016
   6  * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
   7  * huangxin <huangxin@Reuuimllatech.com>
   8  * Mylène Josserand <mylene.josserand@free-electrons.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/regmap.h>
  27
  28 #include <sound/pcm_params.h>
  29 #include <sound/soc.h>
  30 #include <sound/soc-dapm.h>
  31
  32 #define SUN8I_SYSCLK_CTL                                0x00c
  33 #define SUN8I_SYSCLK_CTL_AIF1CLK_ENA                    11
  34 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL                9
  35 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC                    8
  36 #define SUN8I_SYSCLK_CTL_SYSCLK_ENA                     3
  37 #define SUN8I_SYSCLK_CTL_SYSCLK_SRC                     0
  38 #define SUN8I_MOD_CLK_ENA                               0x010
  39 #define SUN8I_MOD_CLK_ENA_AIF1                          15
  40 #define SUN8I_MOD_CLK_ENA_DAC                           2
  41 #define SUN8I_MOD_RST_CTL                               0x014
  42 #define SUN8I_MOD_RST_CTL_AIF1                          15
  43 #define SUN8I_MOD_RST_CTL_DAC                           2
  44 #define SUN8I_SYS_SR_CTRL                               0x018
  45 #define SUN8I_SYS_SR_CTRL_AIF1_FS                       12
  46 #define SUN8I_SYS_SR_CTRL_AIF2_FS                       8
  47 #define SUN8I_AIF1CLK_CTRL                              0x040
  48 #define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD                15
  49 #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV                14
  50 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV                13
  51 #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV                9
  52 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV                6
  53 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16             (1 << 6)
  54 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ                4
  55 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16             (1 << 4)
  56 #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT                2
  57 #define SUN8I_AIF1_DACDAT_CTRL                          0x048
  58 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA            15
  59 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA            14
  60 #define SUN8I_DAC_DIG_CTRL                              0x120
  61 #define SUN8I_DAC_DIG_CTRL_ENDA                 15
  62 #define SUN8I_DAC_MXR_SRC                               0x130
  63 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L 15
  64 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L 14
  65 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL 13
  66 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL             12
  67 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R 11
  68 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R 10
  69 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9
  70 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR             8
  71
  72 #define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK          GENMASK(15, 12)
  73 #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK          GENMASK(11, 8)
  74 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK   GENMASK(5, 4)
  75 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK   GENMASK(8, 6)
  76
  77 struct sun8i_codec {
  78         struct device   *dev;
  79         struct regmap   *regmap;
  80         struct clk      *clk_module;
  81         struct clk      *clk_bus;
  82 };
  83
  84 static int sun8i_codec_runtime_resume(struct device *dev)
  85 {
  86         struct sun8i_codec *scodec = dev_get_drvdata(dev);
  87         int ret;
  88
  89         ret = clk_prepare_enable(scodec->clk_module);
  90         if (ret) {
  91                 dev_err(dev, "Failed to enable the module clock\n");
  92                 return ret;
  93         }
  94
  95         ret = clk_prepare_enable(scodec->clk_bus);
  96         if (ret) {
  97                 dev_err(dev, "Failed to enable the bus clock\n");
  98                 goto err_disable_modclk;
  99         }
 100
 101         regcache_cache_only(scodec->regmap, false);
 102
 103         ret = regcache_sync(scodec->regmap);
 104         if (ret) {
 105                 dev_err(dev, "Failed to sync regmap cache\n");
 106                 goto err_disable_clk;
 107         }
 108
 109         return 0;
 110
 111 err_disable_clk:
 112         clk_disable_unprepare(scodec->clk_bus);
 113
 114 err_disable_modclk:
 115         clk_disable_unprepare(scodec->clk_module);
 116
 117         return ret;
 118 }
 119
 120 static int sun8i_codec_runtime_suspend(struct device *dev)
 121 {
 122         struct sun8i_codec *scodec = dev_get_drvdata(dev);
 123
 124         regcache_cache_only(scodec->regmap, true);
 125         regcache_mark_dirty(scodec->regmap);
 126
 127         clk_disable_unprepare(scodec->clk_module);
 128         clk_disable_unprepare(scodec->clk_bus);
 129
 130         return 0;
 131 }
 132
 133 static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params)
 134 {
 135         unsigned int rate = params_rate(params);
 136
 137         switch (rate) {
 138         case 8000:
 139         case 7350:
 140                 return 0x0;
 141         case 11025:
 142                 return 0x1;
 143         case 12000:
 144                 return 0x2;
 145         case 16000:
 146                 return 0x3;
 147         case 22050:
 148                 return 0x4;
 149         case 24000:
 150                 return 0x5;
 151         case 32000:
 152                 return 0x6;
 153         case 44100:
 154                 return 0x7;
 155         case 48000:
 156                 return 0x8;
 157         case 96000:
 158                 return 0x9;
 159         case 192000:
 160                 return 0xa;
 161         default:
 162                 return -EINVAL;
 163         }
 164 }
 165
 166 static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 167 {
 168         struct sun8i_codec *scodec = snd_soc_codec_get_drvdata(dai->codec);
 169         u32 value;
 170
 171         /* clock masters */
 172         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 173         case SND_SOC_DAIFMT_CBS_CFS: /* DAI Slave */
 174                 value = 0x0; /* Codec Master */
 175                 break;
 176         case SND_SOC_DAIFMT_CBM_CFM: /* DAI Master */
 177                 value = 0x1; /* Codec Slave */
 178                 break;
 179         default:
 180                 return -EINVAL;
 181         }
 182         regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
 183                            BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD),
 184                            value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD);
 185
 186         /* clock inversion */
 187         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 188         case SND_SOC_DAIFMT_NB_NF: /* Normal */
 189                 value = 0x0;
 190                 break;
 191         case SND_SOC_DAIFMT_IB_IF: /* Inversion */
 192                 value = 0x1;
 193                 break;
 194         default:
 195                 return -EINVAL;
 196         }
 197         regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
 198                            BIT(SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV),
 199                            value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV);
 200         regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
 201                            BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV),
 202                            value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV);
 203
 204         /* DAI format */
 205         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 206         case SND_SOC_DAIFMT_I2S:
 207                 value = 0x0;
 208                 break;
 209         case SND_SOC_DAIFMT_LEFT_J:
 210                 value = 0x1;
 211                 break;
 212         case SND_SOC_DAIFMT_RIGHT_J:
 213                 value = 0x2;
 214                 break;
 215         case SND_SOC_DAIFMT_DSP_A:
 216         case SND_SOC_DAIFMT_DSP_B:
 217                 value = 0x3;
 218                 break;
 219         default:
 220                 return -EINVAL;
 221         }
 222         regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
 223                            BIT(SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT),
 224                            value << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT);
 225
 226         return 0;
 227 }
 228
 229 static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
 230                                  struct snd_pcm_hw_params *params,
 231                                  struct snd_soc_dai *dai)
 232 {
 233         struct sun8i_codec *scodec = snd_soc_codec_get_drvdata(dai->codec);
 234         int sample_rate;
 235
 236         /*
 237          * The CPU DAI handles only a sample of 16 bits. Configure the
 238          * codec to handle this type of sample resolution.
 239          */
 240         regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
 241                            SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK,
 242                            SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16);
 243
 244         regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
 245                            SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK,
 246                            SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16);
 247
 248         sample_rate = sun8i_codec_get_hw_rate(params);
 249         if (sample_rate < 0)
 250                 return sample_rate;
 251
 252         regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL,
 253                            SUN8I_SYS_SR_CTRL_AIF1_FS_MASK,
 254                            sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS);
 255         regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL,
 256                            SUN8I_SYS_SR_CTRL_AIF2_FS_MASK,
 257                            sample_rate << SUN8I_SYS_SR_CTRL_AIF2_FS);
 258
 259         return 0;
 260 }
 261
 262 static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = {
 263         SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch",
 264                         SUN8I_DAC_MXR_SRC,
 265                         SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L,
 266                         SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0),
 267         SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch",
 268                         SUN8I_DAC_MXR_SRC,
 269                         SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L,
 270                         SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0),
 271         SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
 272                         SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL,
 273                         SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0),
 274         SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
 275                         SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL,
 276                         SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0),
 277 };
 278
 279 static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
 280         /* Digital parts of the DACs */
 281         SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA,
 282                             0, NULL, 0),
 283
 284         /* Analog DAC AIF */
 285         SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left", "Playback", 0,
 286                             SUN8I_AIF1_DACDAT_CTRL,
 287                             SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0),
 288         SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Right", "Playback", 0,
 289                             SUN8I_AIF1_DACDAT_CTRL,
 290                             SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),
 291
 292         /* DAC Mixers */
 293         SND_SOC_DAPM_MIXER("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
 294                            sun8i_dac_mixer_controls,
 295                            ARRAY_SIZE(sun8i_dac_mixer_controls)),
 296         SND_SOC_DAPM_MIXER("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
 297                            sun8i_dac_mixer_controls,
 298                            ARRAY_SIZE(sun8i_dac_mixer_controls)),
 299
 300         /* Clocks */
 301         SND_SOC_DAPM_SUPPLY("MODCLK AFI1", SUN8I_MOD_CLK_ENA,
 302                             SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0),
 303         SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA,
 304                             SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0),
 305         SND_SOC_DAPM_SUPPLY("AIF1", SUN8I_SYSCLK_CTL,
 306                             SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0),
 307         SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL,
 308                             SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0),
 309
 310         SND_SOC_DAPM_SUPPLY("AIF1 PLL", SUN8I_SYSCLK_CTL,
 311                             SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL, 0, NULL, 0),
 312         /* Inversion as 0=AIF1, 1=AIF2 */
 313         SND_SOC_DAPM_SUPPLY("SYSCLK AIF1", SUN8I_SYSCLK_CTL,
 314                             SUN8I_SYSCLK_CTL_SYSCLK_SRC, 1, NULL, 0),
 315
 316         /* Module reset */
 317         SND_SOC_DAPM_SUPPLY("RST AIF1", SUN8I_MOD_RST_CTL,
 318                             SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0),
 319         SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL,
 320                             SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0),
 321 };
 322
 323 static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
 324         /* Clock Routes */
 325         { "AIF1", NULL, "SYSCLK AIF1" },
 326         { "AIF1 PLL", NULL, "AIF1" },
 327         { "RST AIF1", NULL, "AIF1 PLL" },
 328         { "MODCLK AFI1", NULL, "RST AIF1" },
 329         { "DAC", NULL, "MODCLK AFI1" },
 330
 331         { "RST DAC", NULL, "SYSCLK" },
 332         { "MODCLK DAC", NULL, "RST DAC" },
 333         { "DAC", NULL, "MODCLK DAC" },
 334
 335         /* DAC Routes */
 336         { "AIF1 Slot 0 Right", NULL, "DAC" },
 337         { "AIF1 Slot 0 Left", NULL, "DAC" },
 338
 339         /* DAC Mixer Routes */
 340         { "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
 341           "AIF1 Slot 0 Left"},
 342         { "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
 343           "AIF1 Slot 0 Right"},
 344 };
 345
 346 static struct snd_soc_dai_ops sun8i_codec_dai_ops = {
 347         .hw_params = sun8i_codec_hw_params,
 348         .set_fmt = sun8i_set_fmt,
 349 };
 350
 351 static struct snd_soc_dai_driver sun8i_codec_dai = {
 352         .name = "sun8i",
 353         /* playback capabilities */
 354         .playback = {
 355                 .stream_name = "Playback",
 356                 .channels_min = 1,
 357                 .channels_max = 2,
 358                 .rates = SNDRV_PCM_RATE_8000_192000,
 359                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 360         },
 361         /* pcm operations */
 362         .ops = &sun8i_codec_dai_ops,
 363 };
 364
 365 static struct snd_soc_codec_driver sun8i_soc_codec = {
 366         .component_driver = {
 367                 .dapm_widgets           = sun8i_codec_dapm_widgets,
 368                 .num_dapm_widgets       = ARRAY_SIZE(sun8i_codec_dapm_widgets),
 369                 .dapm_routes            = sun8i_codec_dapm_routes,
 370                 .num_dapm_routes        = ARRAY_SIZE(sun8i_codec_dapm_routes),
 371         },
 372 };
 373
 374 static const struct regmap_config sun8i_codec_regmap_config = {
 375         .reg_bits       = 32,
 376         .reg_stride     = 4,
 377         .val_bits       = 32,
 378         .max_register   = SUN8I_DAC_MXR_SRC,
 379
 380         .cache_type     = REGCACHE_FLAT,
 381 };
 382
 383 static int sun8i_codec_probe(struct platform_device *pdev)
 384 {
 385         struct resource *res_base;
 386         struct sun8i_codec *scodec;
 387         void __iomem *base;
 388         int ret;
 389
 390         scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
 391         if (!scodec)
 392                 return -ENOMEM;
 393
 394         scodec->dev = &pdev->dev;
 395
 396         scodec->clk_module = devm_clk_get(&pdev->dev, "mod");
 397         if (IS_ERR(scodec->clk_module)) {
 398                 dev_err(&pdev->dev, "Failed to get the module clock\n");
 399                 return PTR_ERR(scodec->clk_module);
 400         }
 401
 402         scodec->clk_bus = devm_clk_get(&pdev->dev, "bus");
 403         if (IS_ERR(scodec->clk_bus)) {
 404                 dev_err(&pdev->dev, "Failed to get the bus clock\n");
 405                 return PTR_ERR(scodec->clk_bus);
 406         }
 407
 408         res_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 409         base = devm_ioremap_resource(&pdev->dev, res_base);
 410         if (IS_ERR(base)) {
 411                 dev_err(&pdev->dev, "Failed to map the registers\n");
 412                 return PTR_ERR(base);
 413         }
 414
 415         scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
 416                                                &sun8i_codec_regmap_config);
 417         if (IS_ERR(scodec->regmap)) {
 418                 dev_err(&pdev->dev, "Failed to create our regmap\n");
 419                 return PTR_ERR(scodec->regmap);
 420         }
 421
 422         platform_set_drvdata(pdev, scodec);
 423
 424         pm_runtime_enable(&pdev->dev);
 425         if (!pm_runtime_enabled(&pdev->dev)) {
 426                 ret = sun8i_codec_runtime_resume(&pdev->dev);
 427                 if (ret)
 428                         goto err_pm_disable;
 429         }
 430
 431         ret = snd_soc_register_codec(&pdev->dev, &sun8i_soc_codec,
 432                                      &sun8i_codec_dai, 1);
 433         if (ret) {
 434                 dev_err(&pdev->dev, "Failed to register codec\n");
 435                 goto err_suspend;
 436         }
 437
 438         return ret;
 439
 440 err_suspend:
 441         if (!pm_runtime_status_suspended(&pdev->dev))
 442                 sun8i_codec_runtime_suspend(&pdev->dev);
 443
 444 err_pm_disable:
 445         pm_runtime_disable(&pdev->dev);
 446
 447         return ret;
 448 }
 449
 450 static int sun8i_codec_remove(struct platform_device *pdev)
 451 {
 452         struct snd_soc_card *card = platform_get_drvdata(pdev);
 453         struct sun8i_codec *scodec = snd_soc_card_get_drvdata(card);
 454
 455         pm_runtime_disable(&pdev->dev);
 456         if (!pm_runtime_status_suspended(&pdev->dev))
 457                 sun8i_codec_runtime_suspend(&pdev->dev);
 458
 459         snd_soc_unregister_codec(&pdev->dev);
 460         clk_disable_unprepare(scodec->clk_module);
 461         clk_disable_unprepare(scodec->clk_bus);
 462
 463         return 0;
 464 }
 465
 466 static const struct of_device_id sun8i_codec_of_match[] = {
 467         { .compatible = "allwinner,sun8i-a33-codec" },
 468         {}
 469 };
 470 MODULE_DEVICE_TABLE(of, sun8i_codec_of_match);
 471
 472 static const struct dev_pm_ops sun8i_codec_pm_ops = {
 473         SET_RUNTIME_PM_OPS(sun8i_codec_runtime_suspend,
 474                            sun8i_codec_runtime_resume, NULL)
 475 };
 476
 477 static struct platform_driver sun8i_codec_driver = {
 478         .driver = {
 479                 .name = "sun8i-codec",
 480                 .of_match_table = sun8i_codec_of_match,
 481                 .pm = &sun8i_codec_pm_ops,
 482         },
 483         .probe = sun8i_codec_probe,
 484         .remove = sun8i_codec_remove,
 485 };
 486 module_platform_driver(sun8i_codec_driver);
 487
 488 MODULE_DESCRIPTION("Allwinner A33 (sun8i) codec driver");
 489 MODULE_AUTHOR("Mylène Josserand <mylene.josserand@free-electrons.com>");
 490 MODULE_LICENSE("GPL");
 491 MODULE_ALIAS("platform:sun8i-codec");