sound/soc/sunxi/sun8i-codec.c

   1 /*
   2  * This driver supports the digital controls for the internal codec
   3  * found in Allwinner's A33 SoCs.
   4  *
   5  * (C) Copyright 2010-2016
   6  * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
   7  * huangxin <huangxin@Reuuimllatech.com>
   8  * Mylène Josserand <mylene.josserand@free-electrons.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/regmap.h>
  27
  28 #include <sound/pcm_params.h>
  29 #include <sound/soc.h>
  30 #include <sound/soc-dapm.h>
  31
  32 #define SUN8I_SYSCLK_CTL                                0x00c
  33 #define SUN8I_SYSCLK_CTL_AIF1CLK_ENA                    11
  34 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL                9
  35 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC                    8
  36 #define SUN8I_SYSCLK_CTL_SYSCLK_ENA                     3
  37 #define SUN8I_SYSCLK_CTL_SYSCLK_SRC                     0
  38 #define SUN8I_MOD_CLK_ENA                               0x010
  39 #define SUN8I_MOD_CLK_ENA_AIF1                          15
  40 #define SUN8I_MOD_CLK_ENA_DAC                           2
  41 #define SUN8I_MOD_RST_CTL                               0x014
  42 #define SUN8I_MOD_RST_CTL_AIF1                          15
  43 #define SUN8I_MOD_RST_CTL_DAC                           2
  44 #define SUN8I_SYS_SR_CTRL                               0x018
  45 #define SUN8I_SYS_SR_CTRL_AIF1_FS                       12
  46 #define SUN8I_SYS_SR_CTRL_AIF2_FS                       8
  47 #define SUN8I_AIF1CLK_CTRL                              0x040
  48 #define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD                15
  49 #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV                14
  50 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV                13
  51 #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV                9
  52 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV                6
  53 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16             (1 << 6)
  54 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ                4
  55 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16             (1 << 4)
  56 #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT                2
  57 #define SUN8I_AIF1_DACDAT_CTRL                          0x048
  58 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA            15
  59 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA            14
  60 #define SUN8I_DAC_DIG_CTRL                              0x120
  61 #define SUN8I_DAC_DIG_CTRL_ENDA                 15
  62 #define SUN8I_DAC_MXR_SRC                               0x130
  63 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L 15
  64 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L 14
  65 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL 13
  66 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL             12
  67 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R 11
  68 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R 10
  69 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9
  70 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR             8
  71
  72 #define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK          GENMASK(15, 12)
  73 #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK          GENMASK(11, 8)
  74 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK   GENMASK(5, 4)
  75 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK   GENMASK(8, 6)
  76
  77 struct sun8i_codec {
  78         struct device   *dev;
  79         struct regmap   *regmap;
  80         struct clk      *clk_module;
  81         struct clk      *clk_bus;
  82 };
  83
  84 static int sun8i_codec_runtime_resume(struct device *dev)
  85 {
  86         struct sun8i_codec *scodec = dev_get_drvdata(dev);
  87         int ret;
  88
  89         ret = clk_prepare_enable(scodec->clk_module);
  90         if (ret) {
  91                 dev_err(dev, "Failed to enable the module clock\n");
  92                 return ret;
  93         }
  94
  95         ret = clk_prepare_enable(scodec->clk_bus);
  96         if (ret) {
  97                 dev_err(dev, "Failed to enable the bus clock\n");
  98                 goto err_disable_modclk;
  99         }
 100
 101         regcache_cache_only(scodec->regmap, false);
 102
 103         ret = regcache_sync(scodec->regmap);
 104         if (ret) {
 105                 dev_err(dev, "Failed to sync regmap cache\n");
 106                 goto err_disable_clk;
 107         }
 108
 109         return 0;
 110
 111 err_disable_clk:
 112         clk_disable_unprepare(scodec->clk_bus);
 113
 114 err_disable_modclk:
 115         clk_disable_unprepare(scodec->clk_module);
 116
 117         return ret;
 118 }
 119
 120 static int sun8i_codec_runtime_suspend(struct device *dev)
 121 {
 122         struct sun8i_codec *scodec = dev_get_drvdata(dev);
 123
 124         regcache_cache_only(scodec->regmap, true);
 125         regcache_mark_dirty(scodec->regmap);
 126
 127         clk_disable_unprepare(scodec->clk_module);
 128         clk_disable_unprepare(scodec->clk_bus);
 129
 130         return 0;
 131 }
 132
 133 static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params)
 134 {
 135         unsigned int rate = params_rate(params);
 136
 137         switch (rate) {
 138         case 8000:
 139         case 7350:
 140                 return 0x0;
 141         case 11025:
 142                 return 0x1;
 143         case 12000:
 144                 return 0x2;
 145         case 16000:
 146                 return 0x3;
 147         case 22050:
 148                 return 0x4;
 149         case 24000:
 150                 return 0x5;
 151         case 32000:
 152                 return 0x6;
 153         case 44100:
 154                 return 0x7;
 155         case 48000:
 156                 return 0x8;
 157         case 96000:
 158                 return 0x9;
 159         case 192000:
 160                 return 0xa;
 161         default:
 162                 return -EINVAL;
 163         }
 164 }
 165
 166 static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 167 {
 168         struct sun8i_codec *scodec = snd_soc_codec_get_drvdata(dai->codec);
 169         u32 value;
 170
 171         /* clock masters */
 172         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 173         case SND_SOC_DAIFMT_CBS_CFS: /* DAI Slave */
 174                 value = 0x0; /* Codec Master */
 175                 break;
 176         case SND_SOC_DAIFMT_CBM_CFM: /* DAI Master */
 177                 value = 0x1; /* Codec Slave */
 178                 break;
 179         default:
 180                 return -EINVAL;
 181         }
 182         regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
 183                            BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD),
 184                            value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD);
 185
 186         /* clock inversion */
 187         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 188         case SND_SOC_DAIFMT_NB_NF: /* Normal */
 189                 value = 0x0;
 190                 break;
 191         case SND_SOC_DAIFMT_IB_IF: /* Inversion */
 192                 value = 0x1;
 193                 break;
 194         default:
 195                 return -EINVAL;
 196         }
 197         regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
 198                            BIT(SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV),
 199                            value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV);
 200         regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
 201                            BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV),
 202                            value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV);
 203
 204         /* DAI format */
 205         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 206         case SND_SOC_DAIFMT_I2S:
 207                 value = 0x0;
 208                 break;
 209         case SND_SOC_DAIFMT_LEFT_J:
 210                 value = 0x1;
 211                 break;
 212         case SND_SOC_DAIFMT_RIGHT_J:
 213                 value = 0x2;
 214                 break;
 215         case SND_SOC_DAIFMT_DSP_A:
 216         case SND_SOC_DAIFMT_DSP_B:
 217                 value = 0x3;
 218                 break;
 219         default:
 220                 return -EINVAL;
 221         }
 222         regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
 223                            BIT(SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT),
 224                            value << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT);
 225
 226         return 0;
 227 }
 228
 229 static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
 230                                  struct snd_pcm_hw_params *params,
 231                                  struct snd_soc_dai *dai)
 232 {
 233         struct sun8i_codec *scodec = snd_soc_codec_get_drvdata(dai->codec);
 234         int sample_rate;
 235
 236         /*
 237          * The CPU DAI handles only a sample of 16 bits. Configure the
 238          * codec to handle this type of sample resolution.
 239          */
 240         regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
 241                            SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK,
 242                            SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16);
 243
 244         regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
 245                            SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK,
 246                            SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16);
 247
 248         sample_rate = sun8i_codec_get_hw_rate(params);
 249         if (sample_rate < 0)
 250                 return sample_rate;
 251
 252         regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL,
 253                            SUN8I_SYS_SR_CTRL_AIF1_FS_MASK,
 254                            sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS);
 255         regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL,
 256                            SUN8I_SYS_SR_CTRL_AIF2_FS_MASK,
 257                            sample_rate << SUN8I_SYS_SR_CTRL_AIF2_FS);
 258
 259         return 0;
 260 }
 261
 262 static const struct snd_kcontrol_new sun8i_output_left_mixer_controls[] = {
 263         SOC_DAPM_SINGLE("LSlot 0", SUN8I_DAC_MXR_SRC,
 264                         SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L, 1, 0),
 265         SOC_DAPM_SINGLE("LSlot 1", SUN8I_DAC_MXR_SRC,
 266                         SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L, 1, 0),
 267         SOC_DAPM_SINGLE("DACL", SUN8I_DAC_MXR_SRC,
 268                         SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL, 1, 0),
 269         SOC_DAPM_SINGLE("ADCL", SUN8I_DAC_MXR_SRC,
 270                         SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL, 1, 0),
 271 };
 272
 273 static const struct snd_kcontrol_new sun8i_output_right_mixer_controls[] = {
 274         SOC_DAPM_SINGLE("RSlot 0", SUN8I_DAC_MXR_SRC,
 275                         SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0),
 276         SOC_DAPM_SINGLE("RSlot 1", SUN8I_DAC_MXR_SRC,
 277                         SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0),
 278         SOC_DAPM_SINGLE("DACR", SUN8I_DAC_MXR_SRC,
 279                         SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0),
 280         SOC_DAPM_SINGLE("ADCR", SUN8I_DAC_MXR_SRC,
 281                         SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0),
 282 };
 283
 284 static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
 285         /* Digital parts of the DACs */
 286         SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA,
 287                             0, NULL, 0),
 288
 289         /* Analog DAC */
 290         SND_SOC_DAPM_DAC("Digital Left DAC", "Playback", SUN8I_AIF1_DACDAT_CTRL,
 291                          SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0),
 292         SND_SOC_DAPM_DAC("Digital Right DAC", "Playback", SUN8I_AIF1_DACDAT_CTRL,
 293                          SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),
 294
 295         /* DAC Mixers */
 296         SND_SOC_DAPM_MIXER("Left DAC Mixer", SND_SOC_NOPM, 0, 0,
 297                            sun8i_output_left_mixer_controls,
 298                            ARRAY_SIZE(sun8i_output_left_mixer_controls)),
 299         SND_SOC_DAPM_MIXER("Right DAC Mixer", SND_SOC_NOPM, 0, 0,
 300                            sun8i_output_right_mixer_controls,
 301                            ARRAY_SIZE(sun8i_output_right_mixer_controls)),
 302
 303         /* Clocks */
 304         SND_SOC_DAPM_SUPPLY("MODCLK AFI1", SUN8I_MOD_CLK_ENA,
 305                             SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0),
 306         SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA,
 307                             SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0),
 308         SND_SOC_DAPM_SUPPLY("AIF1", SUN8I_SYSCLK_CTL,
 309                             SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0),
 310         SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL,
 311                             SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0),
 312
 313         SND_SOC_DAPM_SUPPLY("AIF1 PLL", SUN8I_SYSCLK_CTL,
 314                             SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL, 0, NULL, 0),
 315         /* Inversion as 0=AIF1, 1=AIF2 */
 316         SND_SOC_DAPM_SUPPLY("SYSCLK AIF1", SUN8I_SYSCLK_CTL,
 317                             SUN8I_SYSCLK_CTL_SYSCLK_SRC, 1, NULL, 0),
 318
 319         /* Module reset */
 320         SND_SOC_DAPM_SUPPLY("RST AIF1", SUN8I_MOD_RST_CTL,
 321                             SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0),
 322         SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL,
 323                             SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0),
 324
 325         SND_SOC_DAPM_OUTPUT("HP"),
 326 };
 327
 328 static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
 329         /* Clock Routes */
 330         { "AIF1", NULL, "SYSCLK AIF1" },
 331         { "AIF1 PLL", NULL, "AIF1" },
 332         { "RST AIF1", NULL, "AIF1 PLL" },
 333         { "MODCLK AFI1", NULL, "RST AIF1" },
 334         { "DAC", NULL, "MODCLK AFI1" },
 335
 336         { "RST DAC", NULL, "SYSCLK" },
 337         { "MODCLK DAC", NULL, "RST DAC" },
 338         { "DAC", NULL, "MODCLK DAC" },
 339
 340         /* DAC Routes */
 341         { "Digital Left DAC", NULL, "DAC" },
 342         { "Digital Right DAC", NULL, "DAC" },
 343
 344         /* DAC Mixer Routes */
 345         { "Left DAC Mixer", "LSlot 0", "Digital Left DAC"},
 346         { "Right DAC Mixer", "RSlot 0", "Digital Right DAC"},
 347
 348         /* End of route : HP out */
 349         { "HP", NULL, "Left DAC Mixer" },
 350         { "HP", NULL, "Right DAC Mixer" },
 351 };
 352
 353 static struct snd_soc_dai_ops sun8i_codec_dai_ops = {
 354         .hw_params = sun8i_codec_hw_params,
 355         .set_fmt = sun8i_set_fmt,
 356 };
 357
 358 static struct snd_soc_dai_driver sun8i_codec_dai = {
 359         .name = "sun8i",
 360         /* playback capabilities */
 361         .playback = {
 362                 .stream_name = "Playback",
 363                 .channels_min = 1,
 364                 .channels_max = 2,
 365                 .rates = SNDRV_PCM_RATE_8000_192000,
 366                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 367         },
 368         /* pcm operations */
 369         .ops = &sun8i_codec_dai_ops,
 370 };
 371
 372 static struct snd_soc_codec_driver sun8i_soc_codec = {
 373         .component_driver = {
 374                 .dapm_widgets           = sun8i_codec_dapm_widgets,
 375                 .num_dapm_widgets       = ARRAY_SIZE(sun8i_codec_dapm_widgets),
 376                 .dapm_routes            = sun8i_codec_dapm_routes,
 377                 .num_dapm_routes        = ARRAY_SIZE(sun8i_codec_dapm_routes),
 378         },
 379 };
 380
 381 static const struct regmap_config sun8i_codec_regmap_config = {
 382         .reg_bits       = 32,
 383         .reg_stride     = 4,
 384         .val_bits       = 32,
 385         .max_register   = SUN8I_DAC_MXR_SRC,
 386
 387         .cache_type     = REGCACHE_FLAT,
 388 };
 389
 390 static int sun8i_codec_probe(struct platform_device *pdev)
 391 {
 392         struct resource *res_base;
 393         struct sun8i_codec *scodec;
 394         void __iomem *base;
 395         int ret;
 396
 397         scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
 398         if (!scodec)
 399                 return -ENOMEM;
 400
 401         scodec->dev = &pdev->dev;
 402
 403         scodec->clk_module = devm_clk_get(&pdev->dev, "mod");
 404         if (IS_ERR(scodec->clk_module)) {
 405                 dev_err(&pdev->dev, "Failed to get the module clock\n");
 406                 return PTR_ERR(scodec->clk_module);
 407         }
 408
 409         scodec->clk_bus = devm_clk_get(&pdev->dev, "bus");
 410         if (IS_ERR(scodec->clk_bus)) {
 411                 dev_err(&pdev->dev, "Failed to get the bus clock\n");
 412                 return PTR_ERR(scodec->clk_bus);
 413         }
 414
 415         res_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 416         base = devm_ioremap_resource(&pdev->dev, res_base);
 417         if (IS_ERR(base)) {
 418                 dev_err(&pdev->dev, "Failed to map the registers\n");
 419                 return PTR_ERR(base);
 420         }
 421
 422         scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
 423                                                &sun8i_codec_regmap_config);
 424         if (IS_ERR(scodec->regmap)) {
 425                 dev_err(&pdev->dev, "Failed to create our regmap\n");
 426                 return PTR_ERR(scodec->regmap);
 427         }
 428
 429         platform_set_drvdata(pdev, scodec);
 430
 431         pm_runtime_enable(&pdev->dev);
 432         if (!pm_runtime_enabled(&pdev->dev)) {
 433                 ret = sun8i_codec_runtime_resume(&pdev->dev);
 434                 if (ret)
 435                         goto err_pm_disable;
 436         }
 437
 438         ret = snd_soc_register_codec(&pdev->dev, &sun8i_soc_codec,
 439                                      &sun8i_codec_dai, 1);
 440         if (ret) {
 441                 dev_err(&pdev->dev, "Failed to register codec\n");
 442                 goto err_suspend;
 443         }
 444
 445         return ret;
 446
 447 err_suspend:
 448         if (!pm_runtime_status_suspended(&pdev->dev))
 449                 sun8i_codec_runtime_suspend(&pdev->dev);
 450
 451 err_pm_disable:
 452         pm_runtime_disable(&pdev->dev);
 453
 454         return ret;
 455 }
 456
 457 static int sun8i_codec_remove(struct platform_device *pdev)
 458 {
 459         struct snd_soc_card *card = platform_get_drvdata(pdev);
 460         struct sun8i_codec *scodec = snd_soc_card_get_drvdata(card);
 461
 462         pm_runtime_disable(&pdev->dev);
 463         if (!pm_runtime_status_suspended(&pdev->dev))
 464                 sun8i_codec_runtime_suspend(&pdev->dev);
 465
 466         snd_soc_unregister_codec(&pdev->dev);
 467         clk_disable_unprepare(scodec->clk_module);
 468         clk_disable_unprepare(scodec->clk_bus);
 469
 470         return 0;
 471 }
 472
 473 static const struct of_device_id sun8i_codec_of_match[] = {
 474         { .compatible = "allwinner,sun8i-a33-codec" },
 475         {}
 476 };
 477 MODULE_DEVICE_TABLE(of, sun8i_codec_of_match);
 478
 479 static const struct dev_pm_ops sun8i_codec_pm_ops = {
 480         SET_RUNTIME_PM_OPS(sun8i_codec_runtime_suspend,
 481                            sun8i_codec_runtime_resume, NULL)
 482 };
 483
 484 static struct platform_driver sun8i_codec_driver = {
 485         .driver = {
 486                 .name = "sun8i-codec",
 487                 .of_match_table = sun8i_codec_of_match,
 488                 .pm = &sun8i_codec_pm_ops,
 489         },
 490         .probe = sun8i_codec_probe,
 491         .remove = sun8i_codec_remove,
 492 };
 493 module_platform_driver(sun8i_codec_driver);
 494
 495 MODULE_DESCRIPTION("Allwinner A33 (sun8i) codec driver");
 496 MODULE_AUTHOR("Mylène Josserand <mylene.josserand@free-electrons.com>");
 497 MODULE_LICENSE("GPL");
 498 MODULE_ALIAS("platform:sun8i-codec");