2 * This driver supports the digital controls for the internal codec
3 * found in Allwinner's A33 SoCs.
5 * (C) Copyright 2010-2016
6 * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
7 * huangxin <huangxin@Reuuimllatech.com>
8 * Mylène Josserand <mylene.josserand@free-electrons.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 #include <linux/module.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/regmap.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
32 #define SUN8I_SYSCLK_CTL 0x00c
33 #define SUN8I_SYSCLK_CTL_AIF1CLK_ENA 11
34 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL 9
35 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC 8
36 #define SUN8I_SYSCLK_CTL_SYSCLK_ENA 3
37 #define SUN8I_SYSCLK_CTL_SYSCLK_SRC 0
38 #define SUN8I_MOD_CLK_ENA 0x010
39 #define SUN8I_MOD_CLK_ENA_AIF1 15
40 #define SUN8I_MOD_CLK_ENA_DAC 2
41 #define SUN8I_MOD_RST_CTL 0x014
42 #define SUN8I_MOD_RST_CTL_AIF1 15
43 #define SUN8I_MOD_RST_CTL_DAC 2
44 #define SUN8I_SYS_SR_CTRL 0x018
45 #define SUN8I_SYS_SR_CTRL_AIF1_FS 12
46 #define SUN8I_SYS_SR_CTRL_AIF2_FS 8
47 #define SUN8I_AIF1CLK_CTRL 0x040
48 #define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD 15
49 #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV 14
50 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV 13
51 #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9
52 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6
53 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16 (1 << 6)
54 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4
55 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16 (1 << 4)
56 #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2
57 #define SUN8I_AIF1_DACDAT_CTRL 0x048
58 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15
59 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14
60 #define SUN8I_DAC_DIG_CTRL 0x120
61 #define SUN8I_DAC_DIG_CTRL_ENDA 15
62 #define SUN8I_DAC_MXR_SRC 0x130
63 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L 15
64 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L 14
65 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL 13
66 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL 12
67 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R 11
68 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R 10
69 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9
70 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8
72 #define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12)
73 #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8)
74 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4)
75 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6)
79 struct regmap
*regmap
;
80 struct clk
*clk_module
;
84 static int sun8i_codec_runtime_resume(struct device
*dev
)
86 struct sun8i_codec
*scodec
= dev_get_drvdata(dev
);
89 ret
= clk_prepare_enable(scodec
->clk_module
);
91 dev_err(dev
, "Failed to enable the module clock\n");
95 ret
= clk_prepare_enable(scodec
->clk_bus
);
97 dev_err(dev
, "Failed to enable the bus clock\n");
98 goto err_disable_modclk
;
101 regcache_cache_only(scodec
->regmap
, false);
103 ret
= regcache_sync(scodec
->regmap
);
105 dev_err(dev
, "Failed to sync regmap cache\n");
106 goto err_disable_clk
;
112 clk_disable_unprepare(scodec
->clk_bus
);
115 clk_disable_unprepare(scodec
->clk_module
);
120 static int sun8i_codec_runtime_suspend(struct device
*dev
)
122 struct sun8i_codec
*scodec
= dev_get_drvdata(dev
);
124 regcache_cache_only(scodec
->regmap
, true);
125 regcache_mark_dirty(scodec
->regmap
);
127 clk_disable_unprepare(scodec
->clk_module
);
128 clk_disable_unprepare(scodec
->clk_bus
);
133 static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params
*params
)
135 unsigned int rate
= params_rate(params
);
166 static int sun8i_set_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
168 struct sun8i_codec
*scodec
= snd_soc_codec_get_drvdata(dai
->codec
);
172 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
173 case SND_SOC_DAIFMT_CBS_CFS
: /* DAI Slave */
174 value
= 0x0; /* Codec Master */
176 case SND_SOC_DAIFMT_CBM_CFM
: /* DAI Master */
177 value
= 0x1; /* Codec Slave */
182 regmap_update_bits(scodec
->regmap
, SUN8I_AIF1CLK_CTRL
,
183 BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD
),
184 value
<< SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD
);
186 /* clock inversion */
187 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
188 case SND_SOC_DAIFMT_NB_NF
: /* Normal */
191 case SND_SOC_DAIFMT_IB_IF
: /* Inversion */
197 regmap_update_bits(scodec
->regmap
, SUN8I_AIF1CLK_CTRL
,
198 BIT(SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV
),
199 value
<< SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV
);
200 regmap_update_bits(scodec
->regmap
, SUN8I_AIF1CLK_CTRL
,
201 BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV
),
202 value
<< SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV
);
205 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
206 case SND_SOC_DAIFMT_I2S
:
209 case SND_SOC_DAIFMT_LEFT_J
:
212 case SND_SOC_DAIFMT_RIGHT_J
:
215 case SND_SOC_DAIFMT_DSP_A
:
216 case SND_SOC_DAIFMT_DSP_B
:
222 regmap_update_bits(scodec
->regmap
, SUN8I_AIF1CLK_CTRL
,
223 BIT(SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT
),
224 value
<< SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT
);
229 static int sun8i_codec_hw_params(struct snd_pcm_substream
*substream
,
230 struct snd_pcm_hw_params
*params
,
231 struct snd_soc_dai
*dai
)
233 struct sun8i_codec
*scodec
= snd_soc_codec_get_drvdata(dai
->codec
);
237 * The CPU DAI handles only a sample of 16 bits. Configure the
238 * codec to handle this type of sample resolution.
240 regmap_update_bits(scodec
->regmap
, SUN8I_AIF1CLK_CTRL
,
241 SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK
,
242 SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16
);
244 regmap_update_bits(scodec
->regmap
, SUN8I_AIF1CLK_CTRL
,
245 SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK
,
246 SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16
);
248 sample_rate
= sun8i_codec_get_hw_rate(params
);
252 regmap_update_bits(scodec
->regmap
, SUN8I_SYS_SR_CTRL
,
253 SUN8I_SYS_SR_CTRL_AIF1_FS_MASK
,
254 sample_rate
<< SUN8I_SYS_SR_CTRL_AIF1_FS
);
255 regmap_update_bits(scodec
->regmap
, SUN8I_SYS_SR_CTRL
,
256 SUN8I_SYS_SR_CTRL_AIF2_FS_MASK
,
257 sample_rate
<< SUN8I_SYS_SR_CTRL_AIF2_FS
);
262 static const struct snd_kcontrol_new sun8i_dac_mixer_controls
[] = {
263 SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch",
265 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L
,
266 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R
, 1, 0),
267 SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch",
269 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L
,
270 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R
, 1, 0),
271 SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC
,
272 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL
,
273 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR
, 1, 0),
274 SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC
,
275 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL
,
276 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR
, 1, 0),
279 static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets
[] = {
280 /* Digital parts of the DACs */
281 SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL
, SUN8I_DAC_DIG_CTRL_ENDA
,
285 SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left", "Playback", 0,
286 SUN8I_AIF1_DACDAT_CTRL
,
287 SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA
, 0),
288 SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Right", "Playback", 0,
289 SUN8I_AIF1_DACDAT_CTRL
,
290 SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA
, 0),
293 SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM
, 0, 0,
294 sun8i_dac_mixer_controls
),
295 SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM
, 0, 0,
296 sun8i_dac_mixer_controls
),
299 SND_SOC_DAPM_SUPPLY("MODCLK AFI1", SUN8I_MOD_CLK_ENA
,
300 SUN8I_MOD_CLK_ENA_AIF1
, 0, NULL
, 0),
301 SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA
,
302 SUN8I_MOD_CLK_ENA_DAC
, 0, NULL
, 0),
303 SND_SOC_DAPM_SUPPLY("AIF1", SUN8I_SYSCLK_CTL
,
304 SUN8I_SYSCLK_CTL_AIF1CLK_ENA
, 0, NULL
, 0),
305 SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL
,
306 SUN8I_SYSCLK_CTL_SYSCLK_ENA
, 0, NULL
, 0),
308 SND_SOC_DAPM_SUPPLY("AIF1 PLL", SUN8I_SYSCLK_CTL
,
309 SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL
, 0, NULL
, 0),
310 /* Inversion as 0=AIF1, 1=AIF2 */
311 SND_SOC_DAPM_SUPPLY("SYSCLK AIF1", SUN8I_SYSCLK_CTL
,
312 SUN8I_SYSCLK_CTL_SYSCLK_SRC
, 1, NULL
, 0),
315 SND_SOC_DAPM_SUPPLY("RST AIF1", SUN8I_MOD_RST_CTL
,
316 SUN8I_MOD_RST_CTL_AIF1
, 0, NULL
, 0),
317 SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL
,
318 SUN8I_MOD_RST_CTL_DAC
, 0, NULL
, 0),
321 static const struct snd_soc_dapm_route sun8i_codec_dapm_routes
[] = {
323 { "AIF1", NULL
, "SYSCLK AIF1" },
324 { "AIF1 PLL", NULL
, "AIF1" },
325 { "RST AIF1", NULL
, "AIF1 PLL" },
326 { "MODCLK AFI1", NULL
, "RST AIF1" },
327 { "DAC", NULL
, "MODCLK AFI1" },
329 { "RST DAC", NULL
, "SYSCLK" },
330 { "MODCLK DAC", NULL
, "RST DAC" },
331 { "DAC", NULL
, "MODCLK DAC" },
334 { "AIF1 Slot 0 Right", NULL
, "DAC" },
335 { "AIF1 Slot 0 Left", NULL
, "DAC" },
337 /* DAC Mixer Routes */
338 { "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
340 { "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
341 "AIF1 Slot 0 Right"},
344 static const struct snd_soc_dai_ops sun8i_codec_dai_ops
= {
345 .hw_params
= sun8i_codec_hw_params
,
346 .set_fmt
= sun8i_set_fmt
,
349 static struct snd_soc_dai_driver sun8i_codec_dai
= {
351 /* playback capabilities */
353 .stream_name
= "Playback",
356 .rates
= SNDRV_PCM_RATE_8000_192000
,
357 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
360 .ops
= &sun8i_codec_dai_ops
,
363 static const struct snd_soc_codec_driver sun8i_soc_codec
= {
364 .component_driver
= {
365 .dapm_widgets
= sun8i_codec_dapm_widgets
,
366 .num_dapm_widgets
= ARRAY_SIZE(sun8i_codec_dapm_widgets
),
367 .dapm_routes
= sun8i_codec_dapm_routes
,
368 .num_dapm_routes
= ARRAY_SIZE(sun8i_codec_dapm_routes
),
372 static const struct regmap_config sun8i_codec_regmap_config
= {
376 .max_register
= SUN8I_DAC_MXR_SRC
,
378 .cache_type
= REGCACHE_FLAT
,
381 static int sun8i_codec_probe(struct platform_device
*pdev
)
383 struct resource
*res_base
;
384 struct sun8i_codec
*scodec
;
388 scodec
= devm_kzalloc(&pdev
->dev
, sizeof(*scodec
), GFP_KERNEL
);
392 scodec
->dev
= &pdev
->dev
;
394 scodec
->clk_module
= devm_clk_get(&pdev
->dev
, "mod");
395 if (IS_ERR(scodec
->clk_module
)) {
396 dev_err(&pdev
->dev
, "Failed to get the module clock\n");
397 return PTR_ERR(scodec
->clk_module
);
400 scodec
->clk_bus
= devm_clk_get(&pdev
->dev
, "bus");
401 if (IS_ERR(scodec
->clk_bus
)) {
402 dev_err(&pdev
->dev
, "Failed to get the bus clock\n");
403 return PTR_ERR(scodec
->clk_bus
);
406 res_base
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
407 base
= devm_ioremap_resource(&pdev
->dev
, res_base
);
409 dev_err(&pdev
->dev
, "Failed to map the registers\n");
410 return PTR_ERR(base
);
413 scodec
->regmap
= devm_regmap_init_mmio(&pdev
->dev
, base
,
414 &sun8i_codec_regmap_config
);
415 if (IS_ERR(scodec
->regmap
)) {
416 dev_err(&pdev
->dev
, "Failed to create our regmap\n");
417 return PTR_ERR(scodec
->regmap
);
420 platform_set_drvdata(pdev
, scodec
);
422 pm_runtime_enable(&pdev
->dev
);
423 if (!pm_runtime_enabled(&pdev
->dev
)) {
424 ret
= sun8i_codec_runtime_resume(&pdev
->dev
);
429 ret
= snd_soc_register_codec(&pdev
->dev
, &sun8i_soc_codec
,
430 &sun8i_codec_dai
, 1);
432 dev_err(&pdev
->dev
, "Failed to register codec\n");
439 if (!pm_runtime_status_suspended(&pdev
->dev
))
440 sun8i_codec_runtime_suspend(&pdev
->dev
);
443 pm_runtime_disable(&pdev
->dev
);
448 static int sun8i_codec_remove(struct platform_device
*pdev
)
450 struct snd_soc_card
*card
= platform_get_drvdata(pdev
);
451 struct sun8i_codec
*scodec
= snd_soc_card_get_drvdata(card
);
453 pm_runtime_disable(&pdev
->dev
);
454 if (!pm_runtime_status_suspended(&pdev
->dev
))
455 sun8i_codec_runtime_suspend(&pdev
->dev
);
457 snd_soc_unregister_codec(&pdev
->dev
);
458 clk_disable_unprepare(scodec
->clk_module
);
459 clk_disable_unprepare(scodec
->clk_bus
);
464 static const struct of_device_id sun8i_codec_of_match
[] = {
465 { .compatible
= "allwinner,sun8i-a33-codec" },
468 MODULE_DEVICE_TABLE(of
, sun8i_codec_of_match
);
470 static const struct dev_pm_ops sun8i_codec_pm_ops
= {
471 SET_RUNTIME_PM_OPS(sun8i_codec_runtime_suspend
,
472 sun8i_codec_runtime_resume
, NULL
)
475 static struct platform_driver sun8i_codec_driver
= {
477 .name
= "sun8i-codec",
478 .of_match_table
= sun8i_codec_of_match
,
479 .pm
= &sun8i_codec_pm_ops
,
481 .probe
= sun8i_codec_probe
,
482 .remove
= sun8i_codec_remove
,
484 module_platform_driver(sun8i_codec_driver
);
486 MODULE_DESCRIPTION("Allwinner A33 (sun8i) codec driver");
487 MODULE_AUTHOR("Mylène Josserand <mylene.josserand@free-electrons.com>");
488 MODULE_LICENSE("GPL");
489 MODULE_ALIAS("platform:sun8i-codec");