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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[mirror_ubuntu-artful-kernel.git] / sound / sparc / dbri.c
1 /*
2 * Driver for DBRI sound chip found on Sparcs.
3 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
4 *
5 * Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl)
6 *
7 * Based entirely upon drivers/sbus/audio/dbri.c which is:
8 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
9 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
10 *
11 * This is the low level driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
12 * on Sun SPARCStation 10, 20, LX and Voyager models.
13 *
14 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
15 * data time multiplexer with ISDN support (aka T7259)
16 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
17 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
18 * Documentation:
19 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from
20 * Sparc Technology Business (courtesy of Sun Support)
21 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
22 * available from the Lucent (formerly AT&T microelectronics) home
23 * page.
24 * - http://www.freesoft.org/Linux/DBRI/
25 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
26 * Interfaces: CHI, Audio In & Out, 2 bits parallel
27 * Documentation: from the Crystal Semiconductor home page.
28 *
29 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
30 * memory and a serial device (long pipes, no. 0-15) or between two serial
31 * devices (short pipes, no. 16-31), or simply send a fixed data to a serial
32 * device (short pipes).
33 * A timeslot defines the bit-offset and no. of bits read from a serial device.
34 * The timeslots are linked to 6 circular lists, one for each direction for
35 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
36 * (the second one is a monitor/tee pipe, valid only for serial input).
37 *
38 * The mmcodec is connected via the CHI bus and needs the data & some
39 * parameters (volume, output selection) time multiplexed in 8 byte
40 * chunks. It also has a control mode, which serves for audio format setting.
41 *
42 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
43 * the same CHI bus, so I thought perhaps it is possible to use the on-board
44 * & the speakerbox codec simultaneously, giving 2 (not very independent :-)
45 * audio devices. But the SUN HW group decided against it, at least on my
46 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
47 * connected.
48 *
49 * I've tried to stick to the following function naming conventions:
50 * snd_* ALSA stuff
51 * cs4215_* CS4215 codec specific stuff
52 * dbri_* DBRI high-level stuff
53 * other DBRI low-level stuff
54 */
55
56 #include <linux/interrupt.h>
57 #include <linux/delay.h>
58 #include <linux/irq.h>
59 #include <linux/io.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/gfp.h>
62
63 #include <sound/core.h>
64 #include <sound/pcm.h>
65 #include <sound/pcm_params.h>
66 #include <sound/info.h>
67 #include <sound/control.h>
68 #include <sound/initval.h>
69
70 #include <linux/of.h>
71 #include <linux/of_device.h>
72 #include <linux/atomic.h>
73 #include <linux/module.h>
74
75 MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
76 MODULE_DESCRIPTION("Sun DBRI");
77 MODULE_LICENSE("GPL");
78 MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
79
80 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
81 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
82 /* Enable this card */
83 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
84
85 module_param_array(index, int, NULL, 0444);
86 MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
87 module_param_array(id, charp, NULL, 0444);
88 MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
89 module_param_array(enable, bool, NULL, 0444);
90 MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
91
92 #undef DBRI_DEBUG
93
94 #define D_INT (1<<0)
95 #define D_GEN (1<<1)
96 #define D_CMD (1<<2)
97 #define D_MM (1<<3)
98 #define D_USR (1<<4)
99 #define D_DESC (1<<5)
100
101 static int dbri_debug;
102 module_param(dbri_debug, int, 0644);
103 MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
104
105 #ifdef DBRI_DEBUG
106 static char *cmds[] = {
107 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
108 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
109 };
110
111 #define dprintk(a, x...) if (dbri_debug & a) printk(KERN_DEBUG x)
112
113 #else
114 #define dprintk(a, x...) do { } while (0)
115
116 #endif /* DBRI_DEBUG */
117
118 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
119 (intr << 27) | \
120 value)
121
122 /***************************************************************************
123 CS4215 specific definitions and structures
124 ****************************************************************************/
125
126 struct cs4215 {
127 __u8 data[4]; /* Data mode: Time slots 5-8 */
128 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
129 __u8 onboard;
130 __u8 offset; /* Bit offset from frame sync to time slot 1 */
131 volatile __u32 status;
132 volatile __u32 version;
133 __u8 precision; /* In bits, either 8 or 16 */
134 __u8 channels; /* 1 or 2 */
135 };
136
137 /*
138 * Control mode first
139 */
140
141 /* Time Slot 1, Status register */
142 #define CS4215_CLB (1<<2) /* Control Latch Bit */
143 #define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
144 /* 0: line: 2.8V, speaker 8V */
145 #define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
146 #define CS4215_RSRVD_1 (1<<5)
147
148 /* Time Slot 2, Data Format Register */
149 #define CS4215_DFR_LINEAR16 0
150 #define CS4215_DFR_ULAW 1
151 #define CS4215_DFR_ALAW 2
152 #define CS4215_DFR_LINEAR8 3
153 #define CS4215_DFR_STEREO (1<<2)
154 static struct {
155 unsigned short freq;
156 unsigned char xtal;
157 unsigned char csval;
158 } CS4215_FREQ[] = {
159 { 8000, (1 << 4), (0 << 3) },
160 { 16000, (1 << 4), (1 << 3) },
161 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */
162 { 32000, (1 << 4), (3 << 3) },
163 /* { NA, (1 << 4), (4 << 3) }, */
164 /* { NA, (1 << 4), (5 << 3) }, */
165 { 48000, (1 << 4), (6 << 3) },
166 { 9600, (1 << 4), (7 << 3) },
167 { 5512, (2 << 4), (0 << 3) }, /* Actually 5512.5 */
168 { 11025, (2 << 4), (1 << 3) },
169 { 18900, (2 << 4), (2 << 3) },
170 { 22050, (2 << 4), (3 << 3) },
171 { 37800, (2 << 4), (4 << 3) },
172 { 44100, (2 << 4), (5 << 3) },
173 { 33075, (2 << 4), (6 << 3) },
174 { 6615, (2 << 4), (7 << 3) },
175 { 0, 0, 0}
176 };
177
178 #define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
179
180 #define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
181
182 /* Time Slot 3, Serial Port Control register */
183 #define CS4215_XEN (1<<0) /* 0: Enable serial output */
184 #define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
185 #define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */
186 #define CS4215_BSEL_128 (1<<2)
187 #define CS4215_BSEL_256 (2<<2)
188 #define CS4215_MCK_MAST (0<<4) /* Master clock */
189 #define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
190 #define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */
191 #define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */
192 #define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */
193
194 /* Time Slot 4, Test Register */
195 #define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
196 #define CS4215_ENL (1<<1) /* Enable Loopback Testing */
197
198 /* Time Slot 5, Parallel Port Register */
199 /* Read only here and the same as the in data mode */
200
201 /* Time Slot 6, Reserved */
202
203 /* Time Slot 7, Version Register */
204 #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
205
206 /* Time Slot 8, Reserved */
207
208 /*
209 * Data mode
210 */
211 /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
212
213 /* Time Slot 5, Output Setting */
214 #define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
215 #define CS4215_LE (1<<6) /* Line Out Enable */
216 #define CS4215_HE (1<<7) /* Headphone Enable */
217
218 /* Time Slot 6, Output Setting */
219 #define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
220 #define CS4215_SE (1<<6) /* Speaker Enable */
221 #define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
222
223 /* Time Slot 7, Input Setting */
224 #define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
225 #define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
226 #define CS4215_OVR (1<<5) /* 1: Over range condition occurred */
227 #define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
228 #define CS4215_PIO1 (1<<7)
229
230 /* Time Slot 8, Input Setting */
231 #define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
232 #define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
233
234 /***************************************************************************
235 DBRI specific definitions and structures
236 ****************************************************************************/
237
238 /* DBRI main registers */
239 #define REG0 0x00 /* Status and Control */
240 #define REG1 0x04 /* Mode and Interrupt */
241 #define REG2 0x08 /* Parallel IO */
242 #define REG3 0x0c /* Test */
243 #define REG8 0x20 /* Command Queue Pointer */
244 #define REG9 0x24 /* Interrupt Queue Pointer */
245
246 #define DBRI_NO_CMDS 64
247 #define DBRI_INT_BLK 64
248 #define DBRI_NO_DESCS 64
249 #define DBRI_NO_PIPES 32
250 #define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1)
251
252 #define DBRI_REC 0
253 #define DBRI_PLAY 1
254 #define DBRI_NO_STREAMS 2
255
256 /* One transmit/receive descriptor */
257 /* When ba != 0 descriptor is used */
258 struct dbri_mem {
259 volatile __u32 word1;
260 __u32 ba; /* Transmit/Receive Buffer Address */
261 __u32 nda; /* Next Descriptor Address */
262 volatile __u32 word4;
263 };
264
265 /* This structure is in a DMA region where it can accessed by both
266 * the CPU and the DBRI
267 */
268 struct dbri_dma {
269 s32 cmd[DBRI_NO_CMDS]; /* Place for commands */
270 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */
271 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */
272 };
273
274 #define dbri_dma_off(member, elem) \
275 ((u32)(unsigned long) \
276 (&(((struct dbri_dma *)0)->member[elem])))
277
278 enum in_or_out { PIPEinput, PIPEoutput };
279
280 struct dbri_pipe {
281 u32 sdp; /* SDP command word */
282 int nextpipe; /* Next pipe in linked list */
283 int length; /* Length of timeslot (bits) */
284 int first_desc; /* Index of first descriptor */
285 int desc; /* Index of active descriptor */
286 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */
287 };
288
289 /* Per stream (playback or record) information */
290 struct dbri_streaminfo {
291 struct snd_pcm_substream *substream;
292 u32 dvma_buffer; /* Device view of ALSA DMA buffer */
293 int size; /* Size of DMA buffer */
294 size_t offset; /* offset in user buffer */
295 int pipe; /* Data pipe used */
296 int left_gain; /* mixer elements */
297 int right_gain;
298 };
299
300 /* This structure holds the information for both chips (DBRI & CS4215) */
301 struct snd_dbri {
302 int regs_size, irq; /* Needed for unload */
303 struct platform_device *op; /* OF device info */
304 spinlock_t lock;
305
306 struct dbri_dma *dma; /* Pointer to our DMA block */
307 dma_addr_t dma_dvma; /* DBRI visible DMA address */
308
309 void __iomem *regs; /* dbri HW regs */
310 int dbri_irqp; /* intr queue pointer */
311
312 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */
313 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */
314 spinlock_t cmdlock; /* Protects cmd queue accesses */
315 s32 *cmdptr; /* Pointer to the last queued cmd */
316
317 int chi_bpf;
318
319 struct cs4215 mm; /* mmcodec special info */
320 /* per stream (playback/record) info */
321 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
322 };
323
324 #define DBRI_MAX_VOLUME 63 /* Output volume */
325 #define DBRI_MAX_GAIN 15 /* Input gain */
326
327 /* DBRI Reg0 - Status Control Register - defines. (Page 17) */
328 #define D_P (1<<15) /* Program command & queue pointer valid */
329 #define D_G (1<<14) /* Allow 4-Word SBus Burst */
330 #define D_S (1<<13) /* Allow 16-Word SBus Burst */
331 #define D_E (1<<12) /* Allow 8-Word SBus Burst */
332 #define D_X (1<<7) /* Sanity Timer Disable */
333 #define D_T (1<<6) /* Permit activation of the TE interface */
334 #define D_N (1<<5) /* Permit activation of the NT interface */
335 #define D_C (1<<4) /* Permit activation of the CHI interface */
336 #define D_F (1<<3) /* Force Sanity Timer Time-Out */
337 #define D_D (1<<2) /* Disable Master Mode */
338 #define D_H (1<<1) /* Halt for Analysis */
339 #define D_R (1<<0) /* Soft Reset */
340
341 /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
342 #define D_LITTLE_END (1<<8) /* Byte Order */
343 #define D_BIG_END (0<<8) /* Byte Order */
344 #define D_MRR (1<<4) /* Multiple Error Ack on SBus (read only) */
345 #define D_MLE (1<<3) /* Multiple Late Error on SBus (read only) */
346 #define D_LBG (1<<2) /* Lost Bus Grant on SBus (read only) */
347 #define D_MBE (1<<1) /* Burst Error on SBus (read only) */
348 #define D_IR (1<<0) /* Interrupt Indicator (read only) */
349
350 /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
351 #define D_ENPIO3 (1<<7) /* Enable Pin 3 */
352 #define D_ENPIO2 (1<<6) /* Enable Pin 2 */
353 #define D_ENPIO1 (1<<5) /* Enable Pin 1 */
354 #define D_ENPIO0 (1<<4) /* Enable Pin 0 */
355 #define D_ENPIO (0xf0) /* Enable all the pins */
356 #define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */
357 #define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */
358 #define D_PIO1 (1<<1) /* Pin 1: 0: Reset */
359 #define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */
360
361 /* DBRI Commands (Page 20) */
362 #define D_WAIT 0x0 /* Stop execution */
363 #define D_PAUSE 0x1 /* Flush long pipes */
364 #define D_JUMP 0x2 /* New command queue */
365 #define D_IIQ 0x3 /* Initialize Interrupt Queue */
366 #define D_REX 0x4 /* Report command execution via interrupt */
367 #define D_SDP 0x5 /* Setup Data Pipe */
368 #define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */
369 #define D_DTS 0x7 /* Define Time Slot */
370 #define D_SSP 0x8 /* Set short Data Pipe */
371 #define D_CHI 0x9 /* Set CHI Global Mode */
372 #define D_NT 0xa /* NT Command */
373 #define D_TE 0xb /* TE Command */
374 #define D_CDEC 0xc /* Codec setup */
375 #define D_TEST 0xd /* No comment */
376 #define D_CDM 0xe /* CHI Data mode command */
377
378 /* Special bits for some commands */
379 #define D_PIPE(v) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */
380
381 /* Setup Data Pipe */
382 /* IRM */
383 #define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value received */
384 #define D_SDP_CHANGE (2<<18) /* Report any changes */
385 #define D_SDP_EVERY (3<<18) /* Report any changes */
386 #define D_SDP_EOL (1<<17) /* EOL interrupt enable */
387 #define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */
388
389 /* Pipe data MODE */
390 #define D_SDP_MEM (0<<13) /* To/from memory */
391 #define D_SDP_HDLC (2<<13)
392 #define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */
393 #define D_SDP_SER (4<<13) /* Serial to serial */
394 #define D_SDP_FIXED (6<<13) /* Short only */
395 #define D_SDP_MODE(v) ((v)&(7<<13))
396
397 #define D_SDP_TO_SER (1<<12) /* Direction */
398 #define D_SDP_FROM_SER (0<<12) /* Direction */
399 #define D_SDP_MSB (1<<11) /* Bit order within Byte */
400 #define D_SDP_LSB (0<<11) /* Bit order within Byte */
401 #define D_SDP_P (1<<10) /* Pointer Valid */
402 #define D_SDP_A (1<<8) /* Abort */
403 #define D_SDP_C (1<<7) /* Clear */
404
405 /* Define Time Slot */
406 #define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */
407 #define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */
408 #define D_DTS_INS (1<<15) /* Insert Time Slot */
409 #define D_DTS_DEL (0<<15) /* Delete Time Slot */
410 #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
411 #define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
412
413 /* Time Slot defines */
414 #define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
415 #define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
416 #define D_TS_DI (1<<13) /* Data Invert */
417 #define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */
418 #define D_TS_MONITOR (2<<10) /* Monitor pipe */
419 #define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */
420 #define D_TS_ANCHOR (7<<10) /* Starting short pipes */
421 #define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
422 #define D_TS_NEXT(v) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */
423
424 /* Concentration Highway Interface Modes */
425 #define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
426 #define D_CHI_IR (1<<15) /* Immediate Interrupt Report */
427 #define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */
428 #define D_CHI_OD (1<<13) /* Open Drain Enable */
429 #define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */
430 #define D_CHI_FD (1<<11) /* Frame Drive */
431 #define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
432
433 /* NT: These are here for completeness */
434 #define D_NT_FBIT (1<<17) /* Frame Bit */
435 #define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */
436 #define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */
437 #define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */
438 #define D_NT_ISNT (1<<13) /* Configure interface as NT */
439 #define D_NT_FT (1<<12) /* Fixed Timing */
440 #define D_NT_EZ (1<<11) /* Echo Channel is Zeros */
441 #define D_NT_IFA (1<<10) /* Inhibit Final Activation */
442 #define D_NT_ACT (1<<9) /* Activate Interface */
443 #define D_NT_MFE (1<<8) /* Multiframe Enable */
444 #define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
445 #define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
446 #define D_NT_FACT (1<<1) /* Force Activation */
447 #define D_NT_ABV (1<<0) /* Activate Bipolar Violation */
448
449 /* Codec Setup */
450 #define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
451 #define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
452 #define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
453
454 /* Test */
455 #define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
456 #define D_TEST_SIZE(v) ((v)<<11) /* */
457 #define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */
458 #define D_TEST_PROC 0x6 /* Microprocessor test */
459 #define D_TEST_SER 0x7 /* Serial-Controller test */
460 #define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */
461 #define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */
462 #define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */
463 #define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */
464 #define D_TEST_DUMP 0xe /* ROM Dump */
465
466 /* CHI Data Mode */
467 #define D_CDM_THI (1 << 8) /* Transmit Data on CHIDR Pin */
468 #define D_CDM_RHI (1 << 7) /* Receive Data on CHIDX Pin */
469 #define D_CDM_RCE (1 << 6) /* Receive on Rising Edge of CHICK */
470 #define D_CDM_XCE (1 << 2) /* Transmit Data on Rising Edge of CHICK */
471 #define D_CDM_XEN (1 << 1) /* Transmit Highway Enable */
472 #define D_CDM_REN (1 << 0) /* Receive Highway Enable */
473
474 /* The Interrupts */
475 #define D_INTR_BRDY 1 /* Buffer Ready for processing */
476 #define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */
477 #define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */
478 #define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */
479 #define D_INTR_EOL 5 /* End of List */
480 #define D_INTR_CMDI 6 /* Command has bean read */
481 #define D_INTR_XCMP 8 /* Transmission of frame complete */
482 #define D_INTR_SBRI 9 /* BRI status change info */
483 #define D_INTR_FXDT 10 /* Fixed data change */
484 #define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */
485 #define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */
486 #define D_INTR_DBYT 12 /* Dropped by frame slip */
487 #define D_INTR_RBYT 13 /* Repeated by frame slip */
488 #define D_INTR_LINT 14 /* Lost Interrupt */
489 #define D_INTR_UNDR 15 /* DMA underrun */
490
491 #define D_INTR_TE 32
492 #define D_INTR_NT 34
493 #define D_INTR_CHI 36
494 #define D_INTR_CMD 38
495
496 #define D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f)
497 #define D_INTR_GETCODE(v) (((v) >> 20) & 0xf)
498 #define D_INTR_GETCMD(v) (((v) >> 16) & 0xf)
499 #define D_INTR_GETVAL(v) ((v) & 0xffff)
500 #define D_INTR_GETRVAL(v) ((v) & 0xfffff)
501
502 #define D_P_0 0 /* TE receive anchor */
503 #define D_P_1 1 /* TE transmit anchor */
504 #define D_P_2 2 /* NT transmit anchor */
505 #define D_P_3 3 /* NT receive anchor */
506 #define D_P_4 4 /* CHI send data */
507 #define D_P_5 5 /* CHI receive data */
508 #define D_P_6 6 /* */
509 #define D_P_7 7 /* */
510 #define D_P_8 8 /* */
511 #define D_P_9 9 /* */
512 #define D_P_10 10 /* */
513 #define D_P_11 11 /* */
514 #define D_P_12 12 /* */
515 #define D_P_13 13 /* */
516 #define D_P_14 14 /* */
517 #define D_P_15 15 /* */
518 #define D_P_16 16 /* CHI anchor pipe */
519 #define D_P_17 17 /* CHI send */
520 #define D_P_18 18 /* CHI receive */
521 #define D_P_19 19 /* CHI receive */
522 #define D_P_20 20 /* CHI receive */
523 #define D_P_21 21 /* */
524 #define D_P_22 22 /* */
525 #define D_P_23 23 /* */
526 #define D_P_24 24 /* */
527 #define D_P_25 25 /* */
528 #define D_P_26 26 /* */
529 #define D_P_27 27 /* */
530 #define D_P_28 28 /* */
531 #define D_P_29 29 /* */
532 #define D_P_30 30 /* */
533 #define D_P_31 31 /* */
534
535 /* Transmit descriptor defines */
536 #define DBRI_TD_F (1 << 31) /* End of Frame */
537 #define DBRI_TD_D (1 << 30) /* Do not append CRC */
538 #define DBRI_TD_CNT(v) ((v) << 16) /* Number of valid bytes in the buffer */
539 #define DBRI_TD_B (1 << 15) /* Final interrupt */
540 #define DBRI_TD_M (1 << 14) /* Marker interrupt */
541 #define DBRI_TD_I (1 << 13) /* Transmit Idle Characters */
542 #define DBRI_TD_FCNT(v) (v) /* Flag Count */
543 #define DBRI_TD_UNR (1 << 3) /* Underrun: transmitter is out of data */
544 #define DBRI_TD_ABT (1 << 2) /* Abort: frame aborted */
545 #define DBRI_TD_TBC (1 << 0) /* Transmit buffer Complete */
546 #define DBRI_TD_STATUS(v) ((v) & 0xff) /* Transmit status */
547 /* Maximum buffer size per TD: almost 8KB */
548 #define DBRI_TD_MAXCNT ((1 << 13) - 4)
549
550 /* Receive descriptor defines */
551 #define DBRI_RD_F (1 << 31) /* End of Frame */
552 #define DBRI_RD_C (1 << 30) /* Completed buffer */
553 #define DBRI_RD_B (1 << 15) /* Final interrupt */
554 #define DBRI_RD_M (1 << 14) /* Marker interrupt */
555 #define DBRI_RD_BCNT(v) (v) /* Buffer size */
556 #define DBRI_RD_CRC (1 << 7) /* 0: CRC is correct */
557 #define DBRI_RD_BBC (1 << 6) /* 1: Bad Byte received */
558 #define DBRI_RD_ABT (1 << 5) /* Abort: frame aborted */
559 #define DBRI_RD_OVRN (1 << 3) /* Overrun: data lost */
560 #define DBRI_RD_STATUS(v) ((v) & 0xff) /* Receive status */
561 #define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */
562
563 /* stream_info[] access */
564 /* Translate the ALSA direction into the array index */
565 #define DBRI_STREAMNO(substream) \
566 (substream->stream == \
567 SNDRV_PCM_STREAM_PLAYBACK ? DBRI_PLAY: DBRI_REC)
568
569 /* Return a pointer to dbri_streaminfo */
570 #define DBRI_STREAM(dbri, substream) \
571 &dbri->stream_info[DBRI_STREAMNO(substream)]
572
573 /*
574 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
575 * So we have to reverse the bits. Note: not all bit lengths are supported
576 */
577 static __u32 reverse_bytes(__u32 b, int len)
578 {
579 switch (len) {
580 case 32:
581 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
582 case 16:
583 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
584 case 8:
585 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
586 case 4:
587 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
588 case 2:
589 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
590 case 1:
591 case 0:
592 break;
593 default:
594 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
595 }
596
597 return b;
598 }
599
600 /*
601 ****************************************************************************
602 ************** DBRI initialization and command synchronization *************
603 ****************************************************************************
604
605 Commands are sent to the DBRI by building a list of them in memory,
606 then writing the address of the first list item to DBRI register 8.
607 The list is terminated with a WAIT command, which generates a
608 CPU interrupt to signal completion.
609
610 Since the DBRI can run in parallel with the CPU, several means of
611 synchronization present themselves. The method implemented here uses
612 the dbri_cmdwait() to wait for execution of batch of sent commands.
613
614 A circular command buffer is used here. A new command is being added
615 while another can be executed. The scheme works by adding two WAIT commands
616 after each sent batch of commands. When the next batch is prepared it is
617 added after the WAIT commands then the WAITs are replaced with single JUMP
618 command to the new batch. The the DBRI is forced to reread the last WAIT
619 command (replaced by the JUMP by then). If the DBRI is still executing
620 previous commands the request to reread the WAIT command is ignored.
621
622 Every time a routine wants to write commands to the DBRI, it must
623 first call dbri_cmdlock() and get pointer to a free space in
624 dbri->dma->cmd buffer. After this, the commands can be written to
625 the buffer, and dbri_cmdsend() is called with the final pointer value
626 to send them to the DBRI.
627
628 */
629
630 #define MAXLOOPS 20
631 /*
632 * Wait for the current command string to execute
633 */
634 static void dbri_cmdwait(struct snd_dbri *dbri)
635 {
636 int maxloops = MAXLOOPS;
637 unsigned long flags;
638
639 /* Delay if previous commands are still being processed */
640 spin_lock_irqsave(&dbri->lock, flags);
641 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
642 spin_unlock_irqrestore(&dbri->lock, flags);
643 msleep_interruptible(1);
644 spin_lock_irqsave(&dbri->lock, flags);
645 }
646 spin_unlock_irqrestore(&dbri->lock, flags);
647
648 if (maxloops == 0)
649 printk(KERN_ERR "DBRI: Chip never completed command buffer\n");
650 else
651 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
652 MAXLOOPS - maxloops - 1);
653 }
654 /*
655 * Lock the command queue and return pointer to space for len cmd words
656 * It locks the cmdlock spinlock.
657 */
658 static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len)
659 {
660 u32 dvma_addr = (u32)dbri->dma_dvma;
661
662 /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */
663 len += 2;
664 spin_lock(&dbri->cmdlock);
665 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
666 return dbri->cmdptr + 2;
667 else if (len < sbus_readl(dbri->regs + REG8) - dvma_addr)
668 return dbri->dma->cmd;
669 else
670 printk(KERN_ERR "DBRI: no space for commands.");
671
672 return NULL;
673 }
674
675 /*
676 * Send prepared cmd string. It works by writing a JUMP cmd into
677 * the last WAIT cmd and force DBRI to reread the cmd.
678 * The JUMP cmd points to the new cmd string.
679 * It also releases the cmdlock spinlock.
680 *
681 * Lock must be held before calling this.
682 */
683 static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len)
684 {
685 u32 dvma_addr = (u32)dbri->dma_dvma;
686 s32 tmp, addr;
687 static int wait_id = 0;
688
689 wait_id++;
690 wait_id &= 0xffff; /* restrict it to a 16 bit counter. */
691 *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id);
692 *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id);
693
694 /* Replace the last command with JUMP */
695 addr = dvma_addr + (cmd - len - dbri->dma->cmd) * sizeof(s32);
696 *(dbri->cmdptr+1) = addr;
697 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
698
699 #ifdef DBRI_DEBUG
700 if (cmd > dbri->cmdptr) {
701 s32 *ptr;
702
703 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++)
704 dprintk(D_CMD, "cmd: %lx:%08x\n",
705 (unsigned long)ptr, *ptr);
706 } else {
707 s32 *ptr = dbri->cmdptr;
708
709 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
710 ptr++;
711 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
712 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++)
713 dprintk(D_CMD, "cmd: %lx:%08x\n",
714 (unsigned long)ptr, *ptr);
715 }
716 #endif
717
718 /* Reread the last command */
719 tmp = sbus_readl(dbri->regs + REG0);
720 tmp |= D_P;
721 sbus_writel(tmp, dbri->regs + REG0);
722
723 dbri->cmdptr = cmd;
724 spin_unlock(&dbri->cmdlock);
725 }
726
727 /* Lock must be held when calling this */
728 static void dbri_reset(struct snd_dbri *dbri)
729 {
730 int i;
731 u32 tmp;
732
733 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
734 sbus_readl(dbri->regs + REG0),
735 sbus_readl(dbri->regs + REG2),
736 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
737
738 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
739 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
740 udelay(10);
741
742 /* A brute approach - DBRI falls back to working burst size by itself
743 * On SS20 D_S does not work, so do not try so high. */
744 tmp = sbus_readl(dbri->regs + REG0);
745 tmp |= D_G | D_E;
746 tmp &= ~D_S;
747 sbus_writel(tmp, dbri->regs + REG0);
748 }
749
750 /* Lock must not be held before calling this */
751 static void dbri_initialize(struct snd_dbri *dbri)
752 {
753 u32 dvma_addr = (u32)dbri->dma_dvma;
754 s32 *cmd;
755 u32 dma_addr;
756 unsigned long flags;
757 int n;
758
759 spin_lock_irqsave(&dbri->lock, flags);
760
761 dbri_reset(dbri);
762
763 /* Initialize pipes */
764 for (n = 0; n < DBRI_NO_PIPES; n++)
765 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
766
767 spin_lock_init(&dbri->cmdlock);
768 /*
769 * Initialize the interrupt ring buffer.
770 */
771 dma_addr = dvma_addr + dbri_dma_off(intr, 0);
772 dbri->dma->intr[0] = dma_addr;
773 dbri->dbri_irqp = 1;
774 /*
775 * Set up the interrupt queue
776 */
777 spin_lock(&dbri->cmdlock);
778 cmd = dbri->cmdptr = dbri->dma->cmd;
779 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
780 *(cmd++) = dma_addr;
781 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
782 dbri->cmdptr = cmd;
783 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
784 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
785 dma_addr = dvma_addr + dbri_dma_off(cmd, 0);
786 sbus_writel(dma_addr, dbri->regs + REG8);
787 spin_unlock(&dbri->cmdlock);
788
789 spin_unlock_irqrestore(&dbri->lock, flags);
790 dbri_cmdwait(dbri);
791 }
792
793 /*
794 ****************************************************************************
795 ************************** DBRI data pipe management ***********************
796 ****************************************************************************
797
798 While DBRI control functions use the command and interrupt buffers, the
799 main data path takes the form of data pipes, which can be short (command
800 and interrupt driven), or long (attached to DMA buffers). These functions
801 provide a rudimentary means of setting up and managing the DBRI's pipes,
802 but the calling functions have to make sure they respect the pipes' linked
803 list ordering, among other things. The transmit and receive functions
804 here interface closely with the transmit and receive interrupt code.
805
806 */
807 static inline int pipe_active(struct snd_dbri *dbri, int pipe)
808 {
809 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
810 }
811
812 /* reset_pipe(dbri, pipe)
813 *
814 * Called on an in-use pipe to clear anything being transmitted or received
815 * Lock must be held before calling this.
816 */
817 static void reset_pipe(struct snd_dbri *dbri, int pipe)
818 {
819 int sdp;
820 int desc;
821 s32 *cmd;
822
823 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
824 printk(KERN_ERR "DBRI: reset_pipe called with "
825 "illegal pipe number\n");
826 return;
827 }
828
829 sdp = dbri->pipes[pipe].sdp;
830 if (sdp == 0) {
831 printk(KERN_ERR "DBRI: reset_pipe called "
832 "on uninitialized pipe\n");
833 return;
834 }
835
836 cmd = dbri_cmdlock(dbri, 3);
837 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
838 *(cmd++) = 0;
839 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
840 dbri_cmdsend(dbri, cmd, 3);
841
842 desc = dbri->pipes[pipe].first_desc;
843 if (desc >= 0)
844 do {
845 dbri->dma->desc[desc].ba = 0;
846 dbri->dma->desc[desc].nda = 0;
847 desc = dbri->next_desc[desc];
848 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
849
850 dbri->pipes[pipe].desc = -1;
851 dbri->pipes[pipe].first_desc = -1;
852 }
853
854 /*
855 * Lock must be held before calling this.
856 */
857 static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp)
858 {
859 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
860 printk(KERN_ERR "DBRI: setup_pipe called "
861 "with illegal pipe number\n");
862 return;
863 }
864
865 if ((sdp & 0xf800) != sdp) {
866 printk(KERN_ERR "DBRI: setup_pipe called "
867 "with strange SDP value\n");
868 /* sdp &= 0xf800; */
869 }
870
871 /* If this is a fixed receive pipe, arrange for an interrupt
872 * every time its data changes
873 */
874 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
875 sdp |= D_SDP_CHANGE;
876
877 sdp |= D_PIPE(pipe);
878 dbri->pipes[pipe].sdp = sdp;
879 dbri->pipes[pipe].desc = -1;
880 dbri->pipes[pipe].first_desc = -1;
881
882 reset_pipe(dbri, pipe);
883 }
884
885 /*
886 * Lock must be held before calling this.
887 */
888 static void link_time_slot(struct snd_dbri *dbri, int pipe,
889 int prevpipe, int nextpipe,
890 int length, int cycle)
891 {
892 s32 *cmd;
893 int val;
894
895 if (pipe < 0 || pipe > DBRI_MAX_PIPE
896 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
897 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
898 printk(KERN_ERR
899 "DBRI: link_time_slot called with illegal pipe number\n");
900 return;
901 }
902
903 if (dbri->pipes[pipe].sdp == 0
904 || dbri->pipes[prevpipe].sdp == 0
905 || dbri->pipes[nextpipe].sdp == 0) {
906 printk(KERN_ERR "DBRI: link_time_slot called "
907 "on uninitialized pipe\n");
908 return;
909 }
910
911 dbri->pipes[prevpipe].nextpipe = pipe;
912 dbri->pipes[pipe].nextpipe = nextpipe;
913 dbri->pipes[pipe].length = length;
914
915 cmd = dbri_cmdlock(dbri, 4);
916
917 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
918 /* Deal with CHI special case:
919 * "If transmission on edges 0 or 1 is desired, then cycle n
920 * (where n = # of bit times per frame...) must be used."
921 * - DBRI data sheet, page 11
922 */
923 if (prevpipe == 16 && cycle == 0)
924 cycle = dbri->chi_bpf;
925
926 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
927 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
928 *(cmd++) = 0;
929 *(cmd++) =
930 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
931 } else {
932 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
933 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
934 *(cmd++) =
935 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
936 *(cmd++) = 0;
937 }
938 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
939
940 dbri_cmdsend(dbri, cmd, 4);
941 }
942
943 #if 0
944 /*
945 * Lock must be held before calling this.
946 */
947 static void unlink_time_slot(struct snd_dbri *dbri, int pipe,
948 enum in_or_out direction, int prevpipe,
949 int nextpipe)
950 {
951 s32 *cmd;
952 int val;
953
954 if (pipe < 0 || pipe > DBRI_MAX_PIPE
955 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
956 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
957 printk(KERN_ERR
958 "DBRI: unlink_time_slot called with illegal pipe number\n");
959 return;
960 }
961
962 cmd = dbri_cmdlock(dbri, 4);
963
964 if (direction == PIPEinput) {
965 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
966 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
967 *(cmd++) = D_TS_NEXT(nextpipe);
968 *(cmd++) = 0;
969 } else {
970 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
971 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
972 *(cmd++) = 0;
973 *(cmd++) = D_TS_NEXT(nextpipe);
974 }
975 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
976
977 dbri_cmdsend(dbri, cmd, 4);
978 }
979 #endif
980
981 /* xmit_fixed() / recv_fixed()
982 *
983 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
984 * expected to change much, and which we don't need to buffer.
985 * The DBRI only interrupts us when the data changes (receive pipes),
986 * or only changes the data when this function is called (transmit pipes).
987 * Only short pipes (numbers 16-31) can be used in fixed data mode.
988 *
989 * These function operate on a 32-bit field, no matter how large
990 * the actual time slot is. The interrupt handler takes care of bit
991 * ordering and alignment. An 8-bit time slot will always end up
992 * in the low-order 8 bits, filled either MSB-first or LSB-first,
993 * depending on the settings passed to setup_pipe().
994 *
995 * Lock must not be held before calling it.
996 */
997 static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
998 {
999 s32 *cmd;
1000 unsigned long flags;
1001
1002 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
1003 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
1004 return;
1005 }
1006
1007 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
1008 printk(KERN_ERR "DBRI: xmit_fixed: "
1009 "Uninitialized pipe %d\n", pipe);
1010 return;
1011 }
1012
1013 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1014 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
1015 return;
1016 }
1017
1018 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
1019 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n",
1020 pipe);
1021 return;
1022 }
1023
1024 /* DBRI short pipes always transmit LSB first */
1025
1026 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
1027 data = reverse_bytes(data, dbri->pipes[pipe].length);
1028
1029 cmd = dbri_cmdlock(dbri, 3);
1030
1031 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
1032 *(cmd++) = data;
1033 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1034
1035 spin_lock_irqsave(&dbri->lock, flags);
1036 dbri_cmdsend(dbri, cmd, 3);
1037 spin_unlock_irqrestore(&dbri->lock, flags);
1038 dbri_cmdwait(dbri);
1039
1040 }
1041
1042 static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr)
1043 {
1044 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
1045 printk(KERN_ERR "DBRI: recv_fixed called with "
1046 "illegal pipe number\n");
1047 return;
1048 }
1049
1050 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1051 printk(KERN_ERR "DBRI: recv_fixed called on "
1052 "non-fixed pipe %d\n", pipe);
1053 return;
1054 }
1055
1056 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1057 printk(KERN_ERR "DBRI: recv_fixed called on "
1058 "transmit pipe %d\n", pipe);
1059 return;
1060 }
1061
1062 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1063 }
1064
1065 /* setup_descs()
1066 *
1067 * Setup transmit/receive data on a "long" pipe - i.e, one associated
1068 * with a DMA buffer.
1069 *
1070 * Only pipe numbers 0-15 can be used in this mode.
1071 *
1072 * This function takes a stream number pointing to a data buffer,
1073 * and work by building chains of descriptors which identify the
1074 * data buffers. Buffers too large for a single descriptor will
1075 * be spread across multiple descriptors.
1076 *
1077 * All descriptors create a ring buffer.
1078 *
1079 * Lock must be held before calling this.
1080 */
1081 static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period)
1082 {
1083 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1084 u32 dvma_addr = (u32)dbri->dma_dvma;
1085 __u32 dvma_buffer;
1086 int desc;
1087 int len;
1088 int first_desc = -1;
1089 int last_desc = -1;
1090
1091 if (info->pipe < 0 || info->pipe > 15) {
1092 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
1093 return -2;
1094 }
1095
1096 if (dbri->pipes[info->pipe].sdp == 0) {
1097 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
1098 info->pipe);
1099 return -2;
1100 }
1101
1102 dvma_buffer = info->dvma_buffer;
1103 len = info->size;
1104
1105 if (streamno == DBRI_PLAY) {
1106 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1107 printk(KERN_ERR "DBRI: setup_descs: "
1108 "Called on receive pipe %d\n", info->pipe);
1109 return -2;
1110 }
1111 } else {
1112 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1113 printk(KERN_ERR
1114 "DBRI: setup_descs: Called on transmit pipe %d\n",
1115 info->pipe);
1116 return -2;
1117 }
1118 /* Should be able to queue multiple buffers
1119 * to receive on a pipe
1120 */
1121 if (pipe_active(dbri, info->pipe)) {
1122 printk(KERN_ERR "DBRI: recv_on_pipe: "
1123 "Called on active pipe %d\n", info->pipe);
1124 return -2;
1125 }
1126
1127 /* Make sure buffer size is multiple of four */
1128 len &= ~3;
1129 }
1130
1131 /* Free descriptors if pipe has any */
1132 desc = dbri->pipes[info->pipe].first_desc;
1133 if (desc >= 0)
1134 do {
1135 dbri->dma->desc[desc].ba = 0;
1136 dbri->dma->desc[desc].nda = 0;
1137 desc = dbri->next_desc[desc];
1138 } while (desc != -1 &&
1139 desc != dbri->pipes[info->pipe].first_desc);
1140
1141 dbri->pipes[info->pipe].desc = -1;
1142 dbri->pipes[info->pipe].first_desc = -1;
1143
1144 desc = 0;
1145 while (len > 0) {
1146 int mylen;
1147
1148 for (; desc < DBRI_NO_DESCS; desc++) {
1149 if (!dbri->dma->desc[desc].ba)
1150 break;
1151 }
1152
1153 if (desc == DBRI_NO_DESCS) {
1154 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
1155 return -1;
1156 }
1157
1158 if (len > DBRI_TD_MAXCNT)
1159 mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */
1160 else
1161 mylen = len;
1162
1163 if (mylen > period)
1164 mylen = period;
1165
1166 dbri->next_desc[desc] = -1;
1167 dbri->dma->desc[desc].ba = dvma_buffer;
1168 dbri->dma->desc[desc].nda = 0;
1169
1170 if (streamno == DBRI_PLAY) {
1171 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1172 dbri->dma->desc[desc].word4 = 0;
1173 dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B;
1174 } else {
1175 dbri->dma->desc[desc].word1 = 0;
1176 dbri->dma->desc[desc].word4 =
1177 DBRI_RD_B | DBRI_RD_BCNT(mylen);
1178 }
1179
1180 if (first_desc == -1)
1181 first_desc = desc;
1182 else {
1183 dbri->next_desc[last_desc] = desc;
1184 dbri->dma->desc[last_desc].nda =
1185 dvma_addr + dbri_dma_off(desc, desc);
1186 }
1187
1188 last_desc = desc;
1189 dvma_buffer += mylen;
1190 len -= mylen;
1191 }
1192
1193 if (first_desc == -1 || last_desc == -1) {
1194 printk(KERN_ERR "DBRI: setup_descs: "
1195 " Not enough descriptors available\n");
1196 return -1;
1197 }
1198
1199 dbri->dma->desc[last_desc].nda =
1200 dvma_addr + dbri_dma_off(desc, first_desc);
1201 dbri->next_desc[last_desc] = first_desc;
1202 dbri->pipes[info->pipe].first_desc = first_desc;
1203 dbri->pipes[info->pipe].desc = first_desc;
1204
1205 #ifdef DBRI_DEBUG
1206 for (desc = first_desc; desc != -1;) {
1207 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1208 desc,
1209 dbri->dma->desc[desc].word1,
1210 dbri->dma->desc[desc].ba,
1211 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1212 desc = dbri->next_desc[desc];
1213 if (desc == first_desc)
1214 break;
1215 }
1216 #endif
1217 return 0;
1218 }
1219
1220 /*
1221 ****************************************************************************
1222 ************************** DBRI - CHI interface ****************************
1223 ****************************************************************************
1224
1225 The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1226 multiplexed serial interface which the DBRI can operate in either master
1227 (give clock/frame sync) or slave (take clock/frame sync) mode.
1228
1229 */
1230
1231 enum master_or_slave { CHImaster, CHIslave };
1232
1233 /*
1234 * Lock must not be held before calling it.
1235 */
1236 static void reset_chi(struct snd_dbri *dbri,
1237 enum master_or_slave master_or_slave,
1238 int bits_per_frame)
1239 {
1240 s32 *cmd;
1241 int val;
1242
1243 /* Set CHI Anchor: Pipe 16 */
1244
1245 cmd = dbri_cmdlock(dbri, 4);
1246 val = D_DTS_VO | D_DTS_VI | D_DTS_INS
1247 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16);
1248 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1249 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1250 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1251 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1252 dbri_cmdsend(dbri, cmd, 4);
1253
1254 dbri->pipes[16].sdp = 1;
1255 dbri->pipes[16].nextpipe = 16;
1256
1257 cmd = dbri_cmdlock(dbri, 4);
1258
1259 if (master_or_slave == CHIslave) {
1260 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1261 *
1262 * CHICM = 0 (slave mode, 8 kHz frame rate)
1263 * IR = give immediate CHI status interrupt
1264 * EN = give CHI status interrupt upon change
1265 */
1266 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1267 } else {
1268 /* Setup DBRI for CHI Master - generate clock, FS
1269 *
1270 * BPF = bits per 8 kHz frame
1271 * 12.288 MHz / CHICM_divisor = clock rate
1272 * FD = 1 - drive CHIFS on rising edge of CHICK
1273 */
1274 int clockrate = bits_per_frame * 8;
1275 int divisor = 12288 / clockrate;
1276
1277 if (divisor > 255 || divisor * clockrate != 12288)
1278 printk(KERN_ERR "DBRI: illegal bits_per_frame "
1279 "in setup_chi\n");
1280
1281 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1282 | D_CHI_BPF(bits_per_frame));
1283 }
1284
1285 dbri->chi_bpf = bits_per_frame;
1286
1287 /* CHI Data Mode
1288 *
1289 * RCE = 0 - receive on falling edge of CHICK
1290 * XCE = 1 - transmit on rising edge of CHICK
1291 * XEN = 1 - enable transmitter
1292 * REN = 1 - enable receiver
1293 */
1294
1295 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1296 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
1297 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1298
1299 dbri_cmdsend(dbri, cmd, 4);
1300 }
1301
1302 /*
1303 ****************************************************************************
1304 *********************** CS4215 audio codec management **********************
1305 ****************************************************************************
1306
1307 In the standard SPARC audio configuration, the CS4215 codec is attached
1308 to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1309
1310 * Lock must not be held before calling it.
1311
1312 */
1313 static void cs4215_setup_pipes(struct snd_dbri *dbri)
1314 {
1315 unsigned long flags;
1316
1317 spin_lock_irqsave(&dbri->lock, flags);
1318 /*
1319 * Data mode:
1320 * Pipe 4: Send timeslots 1-4 (audio data)
1321 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1322 * Pipe 6: Receive timeslots 1-4 (audio data)
1323 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1324 * interrupt, and the rest of the data (slot 5 and 8) is
1325 * not relevant for us (only for doublechecking).
1326 *
1327 * Control mode:
1328 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1329 * Pipe 18: Receive timeslot 1 (clb).
1330 * Pipe 19: Receive timeslot 7 (version).
1331 */
1332
1333 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1334 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1335 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1336 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1337
1338 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1339 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1340 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1341 spin_unlock_irqrestore(&dbri->lock, flags);
1342
1343 dbri_cmdwait(dbri);
1344 }
1345
1346 static int cs4215_init_data(struct cs4215 *mm)
1347 {
1348 /*
1349 * No action, memory resetting only.
1350 *
1351 * Data Time Slot 5-8
1352 * Speaker,Line and Headphone enable. Gain set to the half.
1353 * Input is mike.
1354 */
1355 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1356 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1357 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1358 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1359
1360 /*
1361 * Control Time Slot 1-4
1362 * 0: Default I/O voltage scale
1363 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1364 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1365 * 3: Tests disabled
1366 */
1367 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1368 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1369 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1370 mm->ctrl[3] = 0;
1371
1372 mm->status = 0;
1373 mm->version = 0xff;
1374 mm->precision = 8; /* For ULAW */
1375 mm->channels = 1;
1376
1377 return 0;
1378 }
1379
1380 static void cs4215_setdata(struct snd_dbri *dbri, int muted)
1381 {
1382 if (muted) {
1383 dbri->mm.data[0] |= 63;
1384 dbri->mm.data[1] |= 63;
1385 dbri->mm.data[2] &= ~15;
1386 dbri->mm.data[3] &= ~15;
1387 } else {
1388 /* Start by setting the playback attenuation. */
1389 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1390 int left_gain = info->left_gain & 0x3f;
1391 int right_gain = info->right_gain & 0x3f;
1392
1393 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1394 dbri->mm.data[1] &= ~0x3f;
1395 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1396 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1397
1398 /* Now set the recording gain. */
1399 info = &dbri->stream_info[DBRI_REC];
1400 left_gain = info->left_gain & 0xf;
1401 right_gain = info->right_gain & 0xf;
1402 dbri->mm.data[2] |= CS4215_LG(left_gain);
1403 dbri->mm.data[3] |= CS4215_RG(right_gain);
1404 }
1405
1406 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1407 }
1408
1409 /*
1410 * Set the CS4215 to data mode.
1411 */
1412 static void cs4215_open(struct snd_dbri *dbri)
1413 {
1414 int data_width;
1415 u32 tmp;
1416 unsigned long flags;
1417
1418 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1419 dbri->mm.channels, dbri->mm.precision);
1420
1421 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1422 * to make sure this takes. This avoids clicking noises.
1423 */
1424
1425 cs4215_setdata(dbri, 1);
1426 udelay(125);
1427
1428 /*
1429 * Data mode:
1430 * Pipe 4: Send timeslots 1-4 (audio data)
1431 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1432 * Pipe 6: Receive timeslots 1-4 (audio data)
1433 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1434 * interrupt, and the rest of the data (slot 5 and 8) is
1435 * not relevant for us (only for doublechecking).
1436 *
1437 * Just like in control mode, the time slots are all offset by eight
1438 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1439 * even if it's the CHI master. Don't ask me...
1440 */
1441 spin_lock_irqsave(&dbri->lock, flags);
1442 tmp = sbus_readl(dbri->regs + REG0);
1443 tmp &= ~(D_C); /* Disable CHI */
1444 sbus_writel(tmp, dbri->regs + REG0);
1445
1446 /* Switch CS4215 to data mode - set PIO3 to 1 */
1447 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1448 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1449
1450 reset_chi(dbri, CHIslave, 128);
1451
1452 /* Note: this next doesn't work for 8-bit stereo, because the two
1453 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1454 * (See CS4215 datasheet Fig 15)
1455 *
1456 * DBRI non-contiguous mode would be required to make this work.
1457 */
1458 data_width = dbri->mm.channels * dbri->mm.precision;
1459
1460 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1461 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1462 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1463 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
1464
1465 /* FIXME: enable CHI after _setdata? */
1466 tmp = sbus_readl(dbri->regs + REG0);
1467 tmp |= D_C; /* Enable CHI */
1468 sbus_writel(tmp, dbri->regs + REG0);
1469 spin_unlock_irqrestore(&dbri->lock, flags);
1470
1471 cs4215_setdata(dbri, 0);
1472 }
1473
1474 /*
1475 * Send the control information (i.e. audio format)
1476 */
1477 static int cs4215_setctrl(struct snd_dbri *dbri)
1478 {
1479 int i, val;
1480 u32 tmp;
1481 unsigned long flags;
1482
1483 /* FIXME - let the CPU do something useful during these delays */
1484
1485 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1486 * to make sure this takes. This avoids clicking noises.
1487 */
1488 cs4215_setdata(dbri, 1);
1489 udelay(125);
1490
1491 /*
1492 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1493 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1494 */
1495 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1496 sbus_writel(val, dbri->regs + REG2);
1497 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1498 udelay(34);
1499
1500 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1501 * operate as CHI master, supplying clocking and frame synchronization.
1502 *
1503 * In Data mode, however, the CS4215 must be CHI master to insure
1504 * that its data stream is synchronous with its codec.
1505 *
1506 * The upshot of all this? We start by putting the DBRI into master
1507 * mode, program the CS4215 in Control mode, then switch the CS4215
1508 * into Data mode and put the DBRI into slave mode. Various timing
1509 * requirements must be observed along the way.
1510 *
1511 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1512 * others?), the addressing of the CS4215's time slots is
1513 * offset by eight bits, so we add eight to all the "cycle"
1514 * values in the Define Time Slot (DTS) commands. This is
1515 * done in hardware by a TI 248 that delays the DBRI->4215
1516 * frame sync signal by eight clock cycles. Anybody know why?
1517 */
1518 spin_lock_irqsave(&dbri->lock, flags);
1519 tmp = sbus_readl(dbri->regs + REG0);
1520 tmp &= ~D_C; /* Disable CHI */
1521 sbus_writel(tmp, dbri->regs + REG0);
1522
1523 reset_chi(dbri, CHImaster, 128);
1524
1525 /*
1526 * Control mode:
1527 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1528 * Pipe 18: Receive timeslot 1 (clb).
1529 * Pipe 19: Receive timeslot 7 (version).
1530 */
1531
1532 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1533 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1534 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
1535 spin_unlock_irqrestore(&dbri->lock, flags);
1536
1537 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1538 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1539 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1540
1541 spin_lock_irqsave(&dbri->lock, flags);
1542 tmp = sbus_readl(dbri->regs + REG0);
1543 tmp |= D_C; /* Enable CHI */
1544 sbus_writel(tmp, dbri->regs + REG0);
1545 spin_unlock_irqrestore(&dbri->lock, flags);
1546
1547 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
1548 msleep_interruptible(1);
1549
1550 if (i == 0) {
1551 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1552 dbri->mm.status);
1553 return -1;
1554 }
1555
1556 /* Disable changes to our copy of the version number, as we are about
1557 * to leave control mode.
1558 */
1559 recv_fixed(dbri, 19, NULL);
1560
1561 /* Terminate CS4215 control mode - data sheet says
1562 * "Set CLB=1 and send two more frames of valid control info"
1563 */
1564 dbri->mm.ctrl[0] |= CS4215_CLB;
1565 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1566
1567 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1568 udelay(250);
1569
1570 cs4215_setdata(dbri, 0);
1571
1572 return 0;
1573 }
1574
1575 /*
1576 * Setup the codec with the sampling rate, audio format and number of
1577 * channels.
1578 * As part of the process we resend the settings for the data
1579 * timeslots as well.
1580 */
1581 static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate,
1582 snd_pcm_format_t format, unsigned int channels)
1583 {
1584 int freq_idx;
1585 int ret = 0;
1586
1587 /* Lookup index for this rate */
1588 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1589 if (CS4215_FREQ[freq_idx].freq == rate)
1590 break;
1591 }
1592 if (CS4215_FREQ[freq_idx].freq != rate) {
1593 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1594 return -1;
1595 }
1596
1597 switch (format) {
1598 case SNDRV_PCM_FORMAT_MU_LAW:
1599 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1600 dbri->mm.precision = 8;
1601 break;
1602 case SNDRV_PCM_FORMAT_A_LAW:
1603 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1604 dbri->mm.precision = 8;
1605 break;
1606 case SNDRV_PCM_FORMAT_U8:
1607 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1608 dbri->mm.precision = 8;
1609 break;
1610 case SNDRV_PCM_FORMAT_S16_BE:
1611 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1612 dbri->mm.precision = 16;
1613 break;
1614 default:
1615 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1616 return -1;
1617 }
1618
1619 /* Add rate parameters */
1620 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1621 dbri->mm.ctrl[2] = CS4215_XCLK |
1622 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1623
1624 dbri->mm.channels = channels;
1625 if (channels == 2)
1626 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1627
1628 ret = cs4215_setctrl(dbri);
1629 if (ret == 0)
1630 cs4215_open(dbri); /* set codec to data mode */
1631
1632 return ret;
1633 }
1634
1635 /*
1636 *
1637 */
1638 static int cs4215_init(struct snd_dbri *dbri)
1639 {
1640 u32 reg2 = sbus_readl(dbri->regs + REG2);
1641 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1642
1643 /* Look for the cs4215 chips */
1644 if (reg2 & D_PIO2) {
1645 dprintk(D_MM, "Onboard CS4215 detected\n");
1646 dbri->mm.onboard = 1;
1647 }
1648 if (reg2 & D_PIO0) {
1649 dprintk(D_MM, "Speakerbox detected\n");
1650 dbri->mm.onboard = 0;
1651
1652 if (reg2 & D_PIO2) {
1653 printk(KERN_INFO "DBRI: Using speakerbox / "
1654 "ignoring onboard mmcodec.\n");
1655 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1656 }
1657 }
1658
1659 if (!(reg2 & (D_PIO0 | D_PIO2))) {
1660 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1661 return -EIO;
1662 }
1663
1664 cs4215_setup_pipes(dbri);
1665 cs4215_init_data(&dbri->mm);
1666
1667 /* Enable capture of the status & version timeslots. */
1668 recv_fixed(dbri, 18, &dbri->mm.status);
1669 recv_fixed(dbri, 19, &dbri->mm.version);
1670
1671 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1672 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1673 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1674 dbri->mm.offset);
1675 return -EIO;
1676 }
1677 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1678
1679 return 0;
1680 }
1681
1682 /*
1683 ****************************************************************************
1684 *************************** DBRI interrupt handler *************************
1685 ****************************************************************************
1686
1687 The DBRI communicates with the CPU mainly via a circular interrupt
1688 buffer. When an interrupt is signaled, the CPU walks through the
1689 buffer and calls dbri_process_one_interrupt() for each interrupt word.
1690 Complicated interrupts are handled by dedicated functions (which
1691 appear first in this file). Any pending interrupts can be serviced by
1692 calling dbri_process_interrupt_buffer(), which works even if the CPU's
1693 interrupts are disabled.
1694
1695 */
1696
1697 /* xmit_descs()
1698 *
1699 * Starts transmitting the current TD's for recording/playing.
1700 * For playback, ALSA has filled the DMA memory with new data (we hope).
1701 */
1702 static void xmit_descs(struct snd_dbri *dbri)
1703 {
1704 struct dbri_streaminfo *info;
1705 u32 dvma_addr;
1706 s32 *cmd;
1707 unsigned long flags;
1708 int first_td;
1709
1710 if (dbri == NULL)
1711 return; /* Disabled */
1712
1713 dvma_addr = (u32)dbri->dma_dvma;
1714 info = &dbri->stream_info[DBRI_REC];
1715 spin_lock_irqsave(&dbri->lock, flags);
1716
1717 if (info->pipe >= 0) {
1718 first_td = dbri->pipes[info->pipe].first_desc;
1719
1720 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1721
1722 /* Stream could be closed by the time we run. */
1723 if (first_td >= 0) {
1724 cmd = dbri_cmdlock(dbri, 2);
1725 *(cmd++) = DBRI_CMD(D_SDP, 0,
1726 dbri->pipes[info->pipe].sdp
1727 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1728 *(cmd++) = dvma_addr +
1729 dbri_dma_off(desc, first_td);
1730 dbri_cmdsend(dbri, cmd, 2);
1731
1732 /* Reset our admin of the pipe. */
1733 dbri->pipes[info->pipe].desc = first_td;
1734 }
1735 }
1736
1737 info = &dbri->stream_info[DBRI_PLAY];
1738
1739 if (info->pipe >= 0) {
1740 first_td = dbri->pipes[info->pipe].first_desc;
1741
1742 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1743
1744 /* Stream could be closed by the time we run. */
1745 if (first_td >= 0) {
1746 cmd = dbri_cmdlock(dbri, 2);
1747 *(cmd++) = DBRI_CMD(D_SDP, 0,
1748 dbri->pipes[info->pipe].sdp
1749 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1750 *(cmd++) = dvma_addr +
1751 dbri_dma_off(desc, first_td);
1752 dbri_cmdsend(dbri, cmd, 2);
1753
1754 /* Reset our admin of the pipe. */
1755 dbri->pipes[info->pipe].desc = first_td;
1756 }
1757 }
1758
1759 spin_unlock_irqrestore(&dbri->lock, flags);
1760 }
1761
1762 /* transmission_complete_intr()
1763 *
1764 * Called by main interrupt handler when DBRI signals transmission complete
1765 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
1766 *
1767 * Walks through the pipe's list of transmit buffer descriptors and marks
1768 * them as available. Stops when the first descriptor is found without
1769 * TBC (Transmit Buffer Complete) set, or we've run through them all.
1770 *
1771 * The DMA buffers are not released. They form a ring buffer and
1772 * they are filled by ALSA while others are transmitted by DMA.
1773 *
1774 */
1775
1776 static void transmission_complete_intr(struct snd_dbri *dbri, int pipe)
1777 {
1778 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1779 int td = dbri->pipes[pipe].desc;
1780 int status;
1781
1782 while (td >= 0) {
1783 if (td >= DBRI_NO_DESCS) {
1784 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1785 return;
1786 }
1787
1788 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1789 if (!(status & DBRI_TD_TBC))
1790 break;
1791
1792 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1793
1794 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
1795 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
1796
1797 td = dbri->next_desc[td];
1798 dbri->pipes[pipe].desc = td;
1799 }
1800
1801 /* Notify ALSA */
1802 spin_unlock(&dbri->lock);
1803 snd_pcm_period_elapsed(info->substream);
1804 spin_lock(&dbri->lock);
1805 }
1806
1807 static void reception_complete_intr(struct snd_dbri *dbri, int pipe)
1808 {
1809 struct dbri_streaminfo *info;
1810 int rd = dbri->pipes[pipe].desc;
1811 s32 status;
1812
1813 if (rd < 0 || rd >= DBRI_NO_DESCS) {
1814 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1815 return;
1816 }
1817
1818 dbri->pipes[pipe].desc = dbri->next_desc[rd];
1819 status = dbri->dma->desc[rd].word1;
1820 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1821
1822 info = &dbri->stream_info[DBRI_REC];
1823 info->offset += DBRI_RD_CNT(status);
1824
1825 /* FIXME: Check status */
1826
1827 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1828 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1829
1830 /* Notify ALSA */
1831 spin_unlock(&dbri->lock);
1832 snd_pcm_period_elapsed(info->substream);
1833 spin_lock(&dbri->lock);
1834 }
1835
1836 static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x)
1837 {
1838 int val = D_INTR_GETVAL(x);
1839 int channel = D_INTR_GETCHAN(x);
1840 int command = D_INTR_GETCMD(x);
1841 int code = D_INTR_GETCODE(x);
1842 #ifdef DBRI_DEBUG
1843 int rval = D_INTR_GETRVAL(x);
1844 #endif
1845
1846 if (channel == D_INTR_CMD) {
1847 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1848 cmds[command], val);
1849 } else {
1850 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1851 channel, code, rval);
1852 }
1853
1854 switch (code) {
1855 case D_INTR_CMDI:
1856 if (command != D_WAIT)
1857 printk(KERN_ERR "DBRI: Command read interrupt\n");
1858 break;
1859 case D_INTR_BRDY:
1860 reception_complete_intr(dbri, channel);
1861 break;
1862 case D_INTR_XCMP:
1863 case D_INTR_MINT:
1864 transmission_complete_intr(dbri, channel);
1865 break;
1866 case D_INTR_UNDR:
1867 /* UNDR - Transmission underrun
1868 * resend SDP command with clear pipe bit (C) set
1869 */
1870 {
1871 /* FIXME: do something useful in case of underrun */
1872 printk(KERN_ERR "DBRI: Underrun error\n");
1873 #if 0
1874 s32 *cmd;
1875 int pipe = channel;
1876 int td = dbri->pipes[pipe].desc;
1877
1878 dbri->dma->desc[td].word4 = 0;
1879 cmd = dbri_cmdlock(dbri, NoGetLock);
1880 *(cmd++) = DBRI_CMD(D_SDP, 0,
1881 dbri->pipes[pipe].sdp
1882 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1883 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1884 dbri_cmdsend(dbri, cmd);
1885 #endif
1886 }
1887 break;
1888 case D_INTR_FXDT:
1889 /* FXDT - Fixed data change */
1890 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1891 val = reverse_bytes(val, dbri->pipes[channel].length);
1892
1893 if (dbri->pipes[channel].recv_fixed_ptr)
1894 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1895 break;
1896 default:
1897 if (channel != D_INTR_CMD)
1898 printk(KERN_WARNING
1899 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1900 }
1901 }
1902
1903 /* dbri_process_interrupt_buffer advances through the DBRI's interrupt
1904 * buffer until it finds a zero word (indicating nothing more to do
1905 * right now). Non-zero words require processing and are handed off
1906 * to dbri_process_one_interrupt AFTER advancing the pointer.
1907 */
1908 static void dbri_process_interrupt_buffer(struct snd_dbri *dbri)
1909 {
1910 s32 x;
1911
1912 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1913 dbri->dma->intr[dbri->dbri_irqp] = 0;
1914 dbri->dbri_irqp++;
1915 if (dbri->dbri_irqp == DBRI_INT_BLK)
1916 dbri->dbri_irqp = 1;
1917
1918 dbri_process_one_interrupt(dbri, x);
1919 }
1920 }
1921
1922 static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id)
1923 {
1924 struct snd_dbri *dbri = dev_id;
1925 static int errcnt = 0;
1926 int x;
1927
1928 if (dbri == NULL)
1929 return IRQ_NONE;
1930 spin_lock(&dbri->lock);
1931
1932 /*
1933 * Read it, so the interrupt goes away.
1934 */
1935 x = sbus_readl(dbri->regs + REG1);
1936
1937 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1938 u32 tmp;
1939
1940 if (x & D_MRR)
1941 printk(KERN_ERR
1942 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1943 x);
1944 if (x & D_MLE)
1945 printk(KERN_ERR
1946 "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1947 x);
1948 if (x & D_LBG)
1949 printk(KERN_ERR
1950 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1951 if (x & D_MBE)
1952 printk(KERN_ERR
1953 "DBRI: Burst Error on SBus reg1=0x%x\n", x);
1954
1955 /* Some of these SBus errors cause the chip's SBus circuitry
1956 * to be disabled, so just re-enable and try to keep going.
1957 *
1958 * The only one I've seen is MRR, which will be triggered
1959 * if you let a transmit pipe underrun, then try to CDP it.
1960 *
1961 * If these things persist, we reset the chip.
1962 */
1963 if ((++errcnt) % 10 == 0) {
1964 dprintk(D_INT, "Interrupt errors exceeded.\n");
1965 dbri_reset(dbri);
1966 } else {
1967 tmp = sbus_readl(dbri->regs + REG0);
1968 tmp &= ~(D_D);
1969 sbus_writel(tmp, dbri->regs + REG0);
1970 }
1971 }
1972
1973 dbri_process_interrupt_buffer(dbri);
1974
1975 spin_unlock(&dbri->lock);
1976
1977 return IRQ_HANDLED;
1978 }
1979
1980 /****************************************************************************
1981 PCM Interface
1982 ****************************************************************************/
1983 static struct snd_pcm_hardware snd_dbri_pcm_hw = {
1984 .info = SNDRV_PCM_INFO_MMAP |
1985 SNDRV_PCM_INFO_INTERLEAVED |
1986 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1987 SNDRV_PCM_INFO_MMAP_VALID |
1988 SNDRV_PCM_INFO_BATCH,
1989 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1990 SNDRV_PCM_FMTBIT_A_LAW |
1991 SNDRV_PCM_FMTBIT_U8 |
1992 SNDRV_PCM_FMTBIT_S16_BE,
1993 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512,
1994 .rate_min = 5512,
1995 .rate_max = 48000,
1996 .channels_min = 1,
1997 .channels_max = 2,
1998 .buffer_bytes_max = 64 * 1024,
1999 .period_bytes_min = 1,
2000 .period_bytes_max = DBRI_TD_MAXCNT,
2001 .periods_min = 1,
2002 .periods_max = 1024,
2003 };
2004
2005 static int snd_hw_rule_format(struct snd_pcm_hw_params *params,
2006 struct snd_pcm_hw_rule *rule)
2007 {
2008 struct snd_interval *c = hw_param_interval(params,
2009 SNDRV_PCM_HW_PARAM_CHANNELS);
2010 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2011 struct snd_mask fmt;
2012
2013 snd_mask_any(&fmt);
2014 if (c->min > 1) {
2015 fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE;
2016 return snd_mask_refine(f, &fmt);
2017 }
2018 return 0;
2019 }
2020
2021 static int snd_hw_rule_channels(struct snd_pcm_hw_params *params,
2022 struct snd_pcm_hw_rule *rule)
2023 {
2024 struct snd_interval *c = hw_param_interval(params,
2025 SNDRV_PCM_HW_PARAM_CHANNELS);
2026 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2027 struct snd_interval ch;
2028
2029 snd_interval_any(&ch);
2030 if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) {
2031 ch.min = 1;
2032 ch.max = 1;
2033 ch.integer = 1;
2034 return snd_interval_refine(c, &ch);
2035 }
2036 return 0;
2037 }
2038
2039 static int snd_dbri_open(struct snd_pcm_substream *substream)
2040 {
2041 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2042 struct snd_pcm_runtime *runtime = substream->runtime;
2043 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2044 unsigned long flags;
2045
2046 dprintk(D_USR, "open audio output.\n");
2047 runtime->hw = snd_dbri_pcm_hw;
2048
2049 spin_lock_irqsave(&dbri->lock, flags);
2050 info->substream = substream;
2051 info->offset = 0;
2052 info->dvma_buffer = 0;
2053 info->pipe = -1;
2054 spin_unlock_irqrestore(&dbri->lock, flags);
2055
2056 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2057 snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT,
2058 -1);
2059 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT,
2060 snd_hw_rule_channels, NULL,
2061 SNDRV_PCM_HW_PARAM_CHANNELS,
2062 -1);
2063
2064 cs4215_open(dbri);
2065
2066 return 0;
2067 }
2068
2069 static int snd_dbri_close(struct snd_pcm_substream *substream)
2070 {
2071 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2072 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2073
2074 dprintk(D_USR, "close audio output.\n");
2075 info->substream = NULL;
2076 info->offset = 0;
2077
2078 return 0;
2079 }
2080
2081 static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
2082 struct snd_pcm_hw_params *hw_params)
2083 {
2084 struct snd_pcm_runtime *runtime = substream->runtime;
2085 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2086 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2087 int direction;
2088 int ret;
2089
2090 /* set sampling rate, audio format and number of channels */
2091 ret = cs4215_prepare(dbri, params_rate(hw_params),
2092 params_format(hw_params),
2093 params_channels(hw_params));
2094 if (ret != 0)
2095 return ret;
2096
2097 if ((ret = snd_pcm_lib_malloc_pages(substream,
2098 params_buffer_bytes(hw_params))) < 0) {
2099 printk(KERN_ERR "malloc_pages failed with %d\n", ret);
2100 return ret;
2101 }
2102
2103 /* hw_params can get called multiple times. Only map the DMA once.
2104 */
2105 if (info->dvma_buffer == 0) {
2106 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2107 direction = DMA_TO_DEVICE;
2108 else
2109 direction = DMA_FROM_DEVICE;
2110
2111 info->dvma_buffer =
2112 dma_map_single(&dbri->op->dev,
2113 runtime->dma_area,
2114 params_buffer_bytes(hw_params),
2115 direction);
2116 }
2117
2118 direction = params_buffer_bytes(hw_params);
2119 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2120 direction, info->dvma_buffer);
2121 return 0;
2122 }
2123
2124 static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
2125 {
2126 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2127 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2128 int direction;
2129
2130 dprintk(D_USR, "hw_free.\n");
2131
2132 /* hw_free can get called multiple times. Only unmap the DMA once.
2133 */
2134 if (info->dvma_buffer) {
2135 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2136 direction = DMA_TO_DEVICE;
2137 else
2138 direction = DMA_FROM_DEVICE;
2139
2140 dma_unmap_single(&dbri->op->dev, info->dvma_buffer,
2141 substream->runtime->buffer_size, direction);
2142 info->dvma_buffer = 0;
2143 }
2144 if (info->pipe != -1) {
2145 reset_pipe(dbri, info->pipe);
2146 info->pipe = -1;
2147 }
2148
2149 return snd_pcm_lib_free_pages(substream);
2150 }
2151
2152 static int snd_dbri_prepare(struct snd_pcm_substream *substream)
2153 {
2154 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2155 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2156 int ret;
2157
2158 info->size = snd_pcm_lib_buffer_bytes(substream);
2159 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2160 info->pipe = 4; /* Send pipe */
2161 else
2162 info->pipe = 6; /* Receive pipe */
2163
2164 spin_lock_irq(&dbri->lock);
2165 info->offset = 0;
2166
2167 /* Setup the all the transmit/receive descriptors to cover the
2168 * whole DMA buffer.
2169 */
2170 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2171 snd_pcm_lib_period_bytes(substream));
2172
2173 spin_unlock_irq(&dbri->lock);
2174
2175 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2176 return ret;
2177 }
2178
2179 static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
2180 {
2181 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2182 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2183 int ret = 0;
2184
2185 switch (cmd) {
2186 case SNDRV_PCM_TRIGGER_START:
2187 dprintk(D_USR, "start audio, period is %d bytes\n",
2188 (int)snd_pcm_lib_period_bytes(substream));
2189 /* Re-submit the TDs. */
2190 xmit_descs(dbri);
2191 break;
2192 case SNDRV_PCM_TRIGGER_STOP:
2193 dprintk(D_USR, "stop audio.\n");
2194 reset_pipe(dbri, info->pipe);
2195 break;
2196 default:
2197 ret = -EINVAL;
2198 }
2199
2200 return ret;
2201 }
2202
2203 static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
2204 {
2205 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2206 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2207 snd_pcm_uframes_t ret;
2208
2209 ret = bytes_to_frames(substream->runtime, info->offset)
2210 % substream->runtime->buffer_size;
2211 dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n",
2212 ret, substream->runtime->buffer_size);
2213 return ret;
2214 }
2215
2216 static struct snd_pcm_ops snd_dbri_ops = {
2217 .open = snd_dbri_open,
2218 .close = snd_dbri_close,
2219 .ioctl = snd_pcm_lib_ioctl,
2220 .hw_params = snd_dbri_hw_params,
2221 .hw_free = snd_dbri_hw_free,
2222 .prepare = snd_dbri_prepare,
2223 .trigger = snd_dbri_trigger,
2224 .pointer = snd_dbri_pointer,
2225 };
2226
2227 static int snd_dbri_pcm(struct snd_card *card)
2228 {
2229 struct snd_pcm *pcm;
2230 int err;
2231
2232 if ((err = snd_pcm_new(card,
2233 /* ID */ "sun_dbri",
2234 /* device */ 0,
2235 /* playback count */ 1,
2236 /* capture count */ 1, &pcm)) < 0)
2237 return err;
2238
2239 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2240 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2241
2242 pcm->private_data = card->private_data;
2243 pcm->info_flags = 0;
2244 strcpy(pcm->name, card->shortname);
2245
2246 if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm,
2247 SNDRV_DMA_TYPE_CONTINUOUS,
2248 snd_dma_continuous_data(GFP_KERNEL),
2249 64 * 1024, 64 * 1024)) < 0)
2250 return err;
2251
2252 return 0;
2253 }
2254
2255 /*****************************************************************************
2256 Mixer interface
2257 *****************************************************************************/
2258
2259 static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2260 struct snd_ctl_elem_info *uinfo)
2261 {
2262 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2263 uinfo->count = 2;
2264 uinfo->value.integer.min = 0;
2265 if (kcontrol->private_value == DBRI_PLAY)
2266 uinfo->value.integer.max = DBRI_MAX_VOLUME;
2267 else
2268 uinfo->value.integer.max = DBRI_MAX_GAIN;
2269 return 0;
2270 }
2271
2272 static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2273 struct snd_ctl_elem_value *ucontrol)
2274 {
2275 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2276 struct dbri_streaminfo *info;
2277
2278 if (snd_BUG_ON(!dbri))
2279 return -EINVAL;
2280 info = &dbri->stream_info[kcontrol->private_value];
2281
2282 ucontrol->value.integer.value[0] = info->left_gain;
2283 ucontrol->value.integer.value[1] = info->right_gain;
2284 return 0;
2285 }
2286
2287 static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2288 struct snd_ctl_elem_value *ucontrol)
2289 {
2290 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2291 struct dbri_streaminfo *info =
2292 &dbri->stream_info[kcontrol->private_value];
2293 unsigned int vol[2];
2294 int changed = 0;
2295
2296 vol[0] = ucontrol->value.integer.value[0];
2297 vol[1] = ucontrol->value.integer.value[1];
2298 if (kcontrol->private_value == DBRI_PLAY) {
2299 if (vol[0] > DBRI_MAX_VOLUME || vol[1] > DBRI_MAX_VOLUME)
2300 return -EINVAL;
2301 } else {
2302 if (vol[0] > DBRI_MAX_GAIN || vol[1] > DBRI_MAX_GAIN)
2303 return -EINVAL;
2304 }
2305
2306 if (info->left_gain != vol[0]) {
2307 info->left_gain = vol[0];
2308 changed = 1;
2309 }
2310 if (info->right_gain != vol[1]) {
2311 info->right_gain = vol[1];
2312 changed = 1;
2313 }
2314 if (changed) {
2315 /* First mute outputs, and wait 1/8000 sec (125 us)
2316 * to make sure this takes. This avoids clicking noises.
2317 */
2318 cs4215_setdata(dbri, 1);
2319 udelay(125);
2320 cs4215_setdata(dbri, 0);
2321 }
2322 return changed;
2323 }
2324
2325 static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2326 struct snd_ctl_elem_info *uinfo)
2327 {
2328 int mask = (kcontrol->private_value >> 16) & 0xff;
2329
2330 uinfo->type = (mask == 1) ?
2331 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2332 uinfo->count = 1;
2333 uinfo->value.integer.min = 0;
2334 uinfo->value.integer.max = mask;
2335 return 0;
2336 }
2337
2338 static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2339 struct snd_ctl_elem_value *ucontrol)
2340 {
2341 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2342 int elem = kcontrol->private_value & 0xff;
2343 int shift = (kcontrol->private_value >> 8) & 0xff;
2344 int mask = (kcontrol->private_value >> 16) & 0xff;
2345 int invert = (kcontrol->private_value >> 24) & 1;
2346
2347 if (snd_BUG_ON(!dbri))
2348 return -EINVAL;
2349
2350 if (elem < 4)
2351 ucontrol->value.integer.value[0] =
2352 (dbri->mm.data[elem] >> shift) & mask;
2353 else
2354 ucontrol->value.integer.value[0] =
2355 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2356
2357 if (invert == 1)
2358 ucontrol->value.integer.value[0] =
2359 mask - ucontrol->value.integer.value[0];
2360 return 0;
2361 }
2362
2363 static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2364 struct snd_ctl_elem_value *ucontrol)
2365 {
2366 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2367 int elem = kcontrol->private_value & 0xff;
2368 int shift = (kcontrol->private_value >> 8) & 0xff;
2369 int mask = (kcontrol->private_value >> 16) & 0xff;
2370 int invert = (kcontrol->private_value >> 24) & 1;
2371 int changed = 0;
2372 unsigned short val;
2373
2374 if (snd_BUG_ON(!dbri))
2375 return -EINVAL;
2376
2377 val = (ucontrol->value.integer.value[0] & mask);
2378 if (invert == 1)
2379 val = mask - val;
2380 val <<= shift;
2381
2382 if (elem < 4) {
2383 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2384 ~(mask << shift)) | val;
2385 changed = (val != dbri->mm.data[elem]);
2386 } else {
2387 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2388 ~(mask << shift)) | val;
2389 changed = (val != dbri->mm.ctrl[elem - 4]);
2390 }
2391
2392 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2393 "mixer-value=%ld, mm-value=0x%x\n",
2394 mask, changed, ucontrol->value.integer.value[0],
2395 dbri->mm.data[elem & 3]);
2396
2397 if (changed) {
2398 /* First mute outputs, and wait 1/8000 sec (125 us)
2399 * to make sure this takes. This avoids clicking noises.
2400 */
2401 cs4215_setdata(dbri, 1);
2402 udelay(125);
2403 cs4215_setdata(dbri, 0);
2404 }
2405 return changed;
2406 }
2407
2408 /* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2409 timeslots. Shift is the bit offset in the timeslot, mask defines the
2410 number of bits. invert is a boolean for use with attenuation.
2411 */
2412 #define CS4215_SINGLE(xname, entry, shift, mask, invert) \
2413 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
2414 .info = snd_cs4215_info_single, \
2415 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
2416 .private_value = (entry) | ((shift) << 8) | ((mask) << 16) | \
2417 ((invert) << 24) },
2418
2419 static struct snd_kcontrol_new dbri_controls[] = {
2420 {
2421 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2422 .name = "Playback Volume",
2423 .info = snd_cs4215_info_volume,
2424 .get = snd_cs4215_get_volume,
2425 .put = snd_cs4215_put_volume,
2426 .private_value = DBRI_PLAY,
2427 },
2428 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2429 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2430 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2431 {
2432 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2433 .name = "Capture Volume",
2434 .info = snd_cs4215_info_volume,
2435 .get = snd_cs4215_get_volume,
2436 .put = snd_cs4215_put_volume,
2437 .private_value = DBRI_REC,
2438 },
2439 /* FIXME: mic/line switch */
2440 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2441 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2442 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2443 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2444 };
2445
2446 static int snd_dbri_mixer(struct snd_card *card)
2447 {
2448 int idx, err;
2449 struct snd_dbri *dbri;
2450
2451 if (snd_BUG_ON(!card || !card->private_data))
2452 return -EINVAL;
2453 dbri = card->private_data;
2454
2455 strcpy(card->mixername, card->shortname);
2456
2457 for (idx = 0; idx < ARRAY_SIZE(dbri_controls); idx++) {
2458 err = snd_ctl_add(card,
2459 snd_ctl_new1(&dbri_controls[idx], dbri));
2460 if (err < 0)
2461 return err;
2462 }
2463
2464 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2465 dbri->stream_info[idx].left_gain = 0;
2466 dbri->stream_info[idx].right_gain = 0;
2467 }
2468
2469 return 0;
2470 }
2471
2472 /****************************************************************************
2473 /proc interface
2474 ****************************************************************************/
2475 static void dbri_regs_read(struct snd_info_entry *entry,
2476 struct snd_info_buffer *buffer)
2477 {
2478 struct snd_dbri *dbri = entry->private_data;
2479
2480 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2481 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2482 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2483 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2484 }
2485
2486 #ifdef DBRI_DEBUG
2487 static void dbri_debug_read(struct snd_info_entry *entry,
2488 struct snd_info_buffer *buffer)
2489 {
2490 struct snd_dbri *dbri = entry->private_data;
2491 int pipe;
2492 snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2493
2494 for (pipe = 0; pipe < 32; pipe++) {
2495 if (pipe_active(dbri, pipe)) {
2496 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2497 snd_iprintf(buffer,
2498 "Pipe %d: %s SDP=0x%x desc=%d, "
2499 "len=%d next %d\n",
2500 pipe,
2501 (pptr->sdp & D_SDP_TO_SER) ? "output" :
2502 "input",
2503 pptr->sdp, pptr->desc,
2504 pptr->length, pptr->nextpipe);
2505 }
2506 }
2507 }
2508 #endif
2509
2510 static void snd_dbri_proc(struct snd_card *card)
2511 {
2512 struct snd_dbri *dbri = card->private_data;
2513 struct snd_info_entry *entry;
2514
2515 if (!snd_card_proc_new(card, "regs", &entry))
2516 snd_info_set_text_ops(entry, dbri, dbri_regs_read);
2517
2518 #ifdef DBRI_DEBUG
2519 if (!snd_card_proc_new(card, "debug", &entry)) {
2520 snd_info_set_text_ops(entry, dbri, dbri_debug_read);
2521 entry->mode = S_IFREG | S_IRUGO; /* Readable only. */
2522 }
2523 #endif
2524 }
2525
2526 /*
2527 ****************************************************************************
2528 **************************** Initialization ********************************
2529 ****************************************************************************
2530 */
2531 static void snd_dbri_free(struct snd_dbri *dbri);
2532
2533 static int snd_dbri_create(struct snd_card *card,
2534 struct platform_device *op,
2535 int irq, int dev)
2536 {
2537 struct snd_dbri *dbri = card->private_data;
2538 int err;
2539
2540 spin_lock_init(&dbri->lock);
2541 dbri->op = op;
2542 dbri->irq = irq;
2543
2544 dbri->dma = dma_zalloc_coherent(&op->dev, sizeof(struct dbri_dma),
2545 &dbri->dma_dvma, GFP_ATOMIC);
2546 if (!dbri->dma)
2547 return -ENOMEM;
2548
2549 dprintk(D_GEN, "DMA Cmd Block 0x%p (%pad)\n",
2550 dbri->dma, dbri->dma_dvma);
2551
2552 /* Map the registers into memory. */
2553 dbri->regs_size = resource_size(&op->resource[0]);
2554 dbri->regs = of_ioremap(&op->resource[0], 0,
2555 dbri->regs_size, "DBRI Registers");
2556 if (!dbri->regs) {
2557 printk(KERN_ERR "DBRI: could not allocate registers\n");
2558 dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
2559 (void *)dbri->dma, dbri->dma_dvma);
2560 return -EIO;
2561 }
2562
2563 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
2564 "DBRI audio", dbri);
2565 if (err) {
2566 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2567 of_iounmap(&op->resource[0], dbri->regs, dbri->regs_size);
2568 dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
2569 (void *)dbri->dma, dbri->dma_dvma);
2570 return err;
2571 }
2572
2573 /* Do low level initialization of the DBRI and CS4215 chips */
2574 dbri_initialize(dbri);
2575 err = cs4215_init(dbri);
2576 if (err) {
2577 snd_dbri_free(dbri);
2578 return err;
2579 }
2580
2581 return 0;
2582 }
2583
2584 static void snd_dbri_free(struct snd_dbri *dbri)
2585 {
2586 dprintk(D_GEN, "snd_dbri_free\n");
2587 dbri_reset(dbri);
2588
2589 if (dbri->irq)
2590 free_irq(dbri->irq, dbri);
2591
2592 if (dbri->regs)
2593 of_iounmap(&dbri->op->resource[0], dbri->regs, dbri->regs_size);
2594
2595 if (dbri->dma)
2596 dma_free_coherent(&dbri->op->dev,
2597 sizeof(struct dbri_dma),
2598 (void *)dbri->dma, dbri->dma_dvma);
2599 }
2600
2601 static int dbri_probe(struct platform_device *op)
2602 {
2603 struct snd_dbri *dbri;
2604 struct resource *rp;
2605 struct snd_card *card;
2606 static int dev = 0;
2607 int irq;
2608 int err;
2609
2610 if (dev >= SNDRV_CARDS)
2611 return -ENODEV;
2612 if (!enable[dev]) {
2613 dev++;
2614 return -ENOENT;
2615 }
2616
2617 irq = op->archdata.irqs[0];
2618 if (irq <= 0) {
2619 printk(KERN_ERR "DBRI-%d: No IRQ.\n", dev);
2620 return -ENODEV;
2621 }
2622
2623 err = snd_card_new(&op->dev, index[dev], id[dev], THIS_MODULE,
2624 sizeof(struct snd_dbri), &card);
2625 if (err < 0)
2626 return err;
2627
2628 strcpy(card->driver, "DBRI");
2629 strcpy(card->shortname, "Sun DBRI");
2630 rp = &op->resource[0];
2631 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
2632 card->shortname,
2633 rp->flags & 0xffL, (unsigned long long)rp->start, irq);
2634
2635 err = snd_dbri_create(card, op, irq, dev);
2636 if (err < 0) {
2637 snd_card_free(card);
2638 return err;
2639 }
2640
2641 dbri = card->private_data;
2642 err = snd_dbri_pcm(card);
2643 if (err < 0)
2644 goto _err;
2645
2646 err = snd_dbri_mixer(card);
2647 if (err < 0)
2648 goto _err;
2649
2650 /* /proc file handling */
2651 snd_dbri_proc(card);
2652 dev_set_drvdata(&op->dev, card);
2653
2654 err = snd_card_register(card);
2655 if (err < 0)
2656 goto _err;
2657
2658 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2659 dev, dbri->regs,
2660 dbri->irq, op->dev.of_node->name[9], dbri->mm.version);
2661 dev++;
2662
2663 return 0;
2664
2665 _err:
2666 snd_dbri_free(dbri);
2667 snd_card_free(card);
2668 return err;
2669 }
2670
2671 static int dbri_remove(struct platform_device *op)
2672 {
2673 struct snd_card *card = dev_get_drvdata(&op->dev);
2674
2675 snd_dbri_free(card->private_data);
2676 snd_card_free(card);
2677
2678 return 0;
2679 }
2680
2681 static const struct of_device_id dbri_match[] = {
2682 {
2683 .name = "SUNW,DBRIe",
2684 },
2685 {
2686 .name = "SUNW,DBRIf",
2687 },
2688 {},
2689 };
2690
2691 MODULE_DEVICE_TABLE(of, dbri_match);
2692
2693 static struct platform_driver dbri_sbus_driver = {
2694 .driver = {
2695 .name = "dbri",
2696 .of_match_table = dbri_match,
2697 },
2698 .probe = dbri_probe,
2699 .remove = dbri_remove,
2700 };
2701
2702 module_platform_driver(dbri_sbus_driver);
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