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1 /*
2 * intel_hdmi_lpe_audio.h - Intel HDMI LPE audio driver
3 *
4 * Copyright (C) 2016 Intel Corp
5 * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
6 * Ramesh Babu K V <ramesh.babu@intel.com>
7 * Vaibhav Agarwal <vaibhav.agarwal@intel.com>
8 * Jerome Anand <jerome.anand@intel.com>
9 * Aravind Siddappaji <aravindx.siddappaji@intel.com>
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
22 */
23 #ifndef __INTEL_HDMI_LPE_AUDIO_H
24 #define __INTEL_HDMI_LPE_AUDIO_H
25
26 #include <linux/types.h>
27 #include <sound/initval.h>
28 #include <linux/version.h>
29 #include <linux/pm_runtime.h>
30 #include <sound/asoundef.h>
31 #include <sound/control.h>
32 #include <sound/pcm.h>
33
34 #define AUD_CONFIG_VALID_BIT (1<<9)
35 #define AUD_CONFIG_DP_MODE (1<<15)
36 #define AUD_CONFIG_BLOCK_BIT (1<<7)
37
38 #define HMDI_LPE_AUDIO_DRIVER_NAME "intel-hdmi-lpe-audio"
39 #define HAD_MAX_DEVICES 1
40 #define HAD_MIN_CHANNEL 2
41 #define HAD_MAX_CHANNEL 8
42 #define HAD_NUM_OF_RING_BUFS 4
43
44 /* Assume 192KHz, 8channel, 25msec period */
45 #define HAD_MAX_BUFFER (600*1024)
46 #define HAD_MIN_BUFFER (32*1024)
47 #define HAD_MAX_PERIODS 4
48 #define HAD_MIN_PERIODS 4
49 #define HAD_MAX_PERIOD_BYTES (HAD_MAX_BUFFER/HAD_MIN_PERIODS)
50 #define HAD_MIN_PERIOD_BYTES 256
51 #define HAD_FIFO_SIZE 0 /* fifo not being used */
52 #define MAX_SPEAKERS 8
53
54 #define AUD_SAMPLE_RATE_32 32000
55 #define AUD_SAMPLE_RATE_44_1 44100
56 #define AUD_SAMPLE_RATE_48 48000
57 #define AUD_SAMPLE_RATE_88_2 88200
58 #define AUD_SAMPLE_RATE_96 96000
59 #define AUD_SAMPLE_RATE_176_4 176400
60 #define AUD_SAMPLE_RATE_192 192000
61
62 #define HAD_MIN_RATE AUD_SAMPLE_RATE_32
63 #define HAD_MAX_RATE AUD_SAMPLE_RATE_192
64
65 #define DIS_SAMPLE_RATE_25_2 25200
66 #define DIS_SAMPLE_RATE_27 27000
67 #define DIS_SAMPLE_RATE_54 54000
68 #define DIS_SAMPLE_RATE_74_25 74250
69 #define DIS_SAMPLE_RATE_148_5 148500
70 #define HAD_REG_WIDTH 0x08
71 #define HAD_MAX_HW_BUFS 0x04
72 #define HAD_MAX_DIP_WORDS 16
73 #define INTEL_HAD "IntelHdmiLpeAudio"
74
75 /* DP Link Rates */
76 #define DP_2_7_GHZ 270000
77 #define DP_1_62_GHZ 162000
78
79 /* Maud Values */
80 #define AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL 1988
81 #define AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL 2740
82 #define AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL 2982
83 #define AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL 5480
84 #define AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL 5965
85 #define AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL 10961
86 #define HAD_MAX_RATE_DP_2_7_MAUD_VAL 11930
87 #define AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL 3314
88 #define AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL 4567
89 #define AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL 4971
90 #define AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL 9134
91 #define AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL 9942
92 #define AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL 18268
93 #define HAD_MAX_RATE_DP_1_62_MAUD_VAL 19884
94
95 /* Naud Value */
96 #define DP_NAUD_VAL 32768
97
98 /* _AUD_CONFIG register MASK */
99 #define AUD_CONFIG_MASK_UNDERRUN 0xC0000000
100 #define AUD_CONFIG_MASK_SRDBG 0x00000002
101 #define AUD_CONFIG_MASK_FUNCRST 0x00000001
102
103 #define MAX_CNT 0xFF
104 #define HAD_SUSPEND_DELAY 1000
105
106 #define OTM_HDMI_ELD_SIZE 128
107
108 union otm_hdmi_eld_t {
109 unsigned char eld_data[OTM_HDMI_ELD_SIZE];
110 struct {
111 /* Byte[0] = ELD Version Number */
112 union {
113 unsigned char byte0;
114 struct {
115 unsigned char reserved:3; /* Reserf */
116 unsigned char eld_ver:5; /* ELD Version Number */
117 /* 00000b - reserved
118 * 00001b - first rev, obsoleted
119 * 00010b - version 2, supporting CEA version
120 * 861D or below
121 * 00011b:11111b - reserved
122 * for future
123 */
124 };
125 };
126
127 /* Byte[1] = Vendor Version Field */
128 union {
129 unsigned char vendor_version;
130 struct {
131 unsigned char reserved1:3;
132 unsigned char veld_ver:5; /* Version number of the ELD
133 * extension. This value is
134 * provisioned and unique to
135 * each vendor.
136 */
137 };
138 };
139
140 /* Byte[2] = Baseline Length field */
141 unsigned char baseline_eld_length; /* Length of the Baseline structure
142 * divided by Four.
143 */
144
145 /* Byte [3] = Reserved for future use */
146 unsigned char byte3;
147
148 /* Starting of the BaseLine EELD structure
149 * Byte[4] = Monitor Name Length
150 */
151 union {
152 unsigned char byte4;
153 struct {
154 unsigned char mnl:5;
155 unsigned char cea_edid_rev_id:3;
156 };
157 };
158
159 /* Byte[5] = Capabilities */
160 union {
161 unsigned char capabilities;
162 struct {
163 unsigned char hdcp:1; /* HDCP support */
164 unsigned char ai_support:1; /* AI support */
165 unsigned char connection_type:2; /* Connection type
166 * 00 - HDMI
167 * 01 - DP
168 * 10 -11 Reserved
169 * for future
170 * connection types
171 */
172 unsigned char sadc:4; /* Indicates number of 3 bytes
173 * Short Audio Descriptors.
174 */
175 };
176 };
177
178 /* Byte[6] = Audio Synch Delay */
179 unsigned char audio_synch_delay; /* Amount of time reported by the
180 * sink that the video trails audio
181 * in milliseconds.
182 */
183
184 /* Byte[7] = Speaker Allocation Block */
185 union {
186 unsigned char speaker_allocation_block;
187 struct {
188 unsigned char flr:1; /*Front Left and Right channels*/
189 unsigned char lfe:1; /*Low Frequency Effect channel*/
190 unsigned char fc:1; /*Center transmission channel*/
191 unsigned char rlr:1; /*Rear Left and Right channels*/
192 unsigned char rc:1; /*Rear Center channel*/
193 unsigned char flrc:1; /*Front left and Right of Center
194 *transmission channels
195 */
196 unsigned char rlrc:1; /*Rear left and Right of Center
197 *transmission channels
198 */
199 unsigned char reserved3:1; /* Reserved */
200 };
201 };
202
203 /* Byte[8 - 15] - 8 Byte port identification value */
204 unsigned char port_id_value[8];
205
206 /* Byte[16 - 17] - 2 Byte Manufacturer ID */
207 unsigned char manufacturer_id[2];
208
209 /* Byte[18 - 19] - 2 Byte Product ID */
210 unsigned char product_id[2];
211
212 /* Byte [20-83] - 64 Bytes of BaseLine Data */
213 unsigned char mn_sand_sads[64]; /* This will include
214 * - ASCII string of Monitor name
215 * - List of 3 byte SADs
216 * - Zero padding
217 */
218
219 /* Vendor ELD Block should continue here!
220 * No Vendor ELD block defined as of now.
221 */
222 } __packed;
223 };
224
225 /**
226 * enum had_status - Audio stream states
227 *
228 * @STREAM_INIT: Stream initialized
229 * @STREAM_RUNNING: Stream running
230 * @STREAM_PAUSED: Stream paused
231 * @STREAM_DROPPED: Stream dropped
232 */
233 enum had_stream_status {
234 STREAM_INIT = 0,
235 STREAM_RUNNING = 1,
236 STREAM_PAUSED = 2,
237 STREAM_DROPPED = 3
238 };
239
240 /**
241 * enum had_status_stream - HAD stream states
242 */
243 enum had_status_stream {
244 HAD_INIT = 0,
245 HAD_RUNNING_STREAM,
246 };
247
248 enum had_drv_status {
249 HAD_DRV_CONNECTED,
250 HAD_DRV_RUNNING,
251 HAD_DRV_DISCONNECTED,
252 HAD_DRV_SUSPENDED,
253 HAD_DRV_ERR,
254 };
255
256 /* enum intel_had_aud_buf_type - HDMI controller ring buffer types */
257 enum intel_had_aud_buf_type {
258 HAD_BUF_TYPE_A = 0,
259 HAD_BUF_TYPE_B = 1,
260 HAD_BUF_TYPE_C = 2,
261 HAD_BUF_TYPE_D = 3,
262 };
263
264 enum num_aud_ch {
265 CH_STEREO = 0,
266 CH_THREE_FOUR = 1,
267 CH_FIVE_SIX = 2,
268 CH_SEVEN_EIGHT = 3
269 };
270
271 /* HDMI Controller register offsets - audio domain common */
272 /* Base address for below regs = 0x65000 */
273 enum hdmi_ctrl_reg_offset_common {
274 AUDIO_HDMI_CONFIG_A = 0x000,
275 AUDIO_HDMI_CONFIG_B = 0x800,
276 AUDIO_HDMI_CONFIG_C = 0x900,
277 };
278 /* HDMI controller register offsets */
279 enum hdmi_ctrl_reg_offset_v1 {
280 AUD_CONFIG = 0x0,
281 AUD_CH_STATUS_0 = 0x08,
282 AUD_CH_STATUS_1 = 0x0C,
283 AUD_HDMI_CTS = 0x10,
284 AUD_N_ENABLE = 0x14,
285 AUD_SAMPLE_RATE = 0x18,
286 AUD_BUF_CONFIG = 0x20,
287 AUD_BUF_CH_SWAP = 0x24,
288 AUD_BUF_A_ADDR = 0x40,
289 AUD_BUF_A_LENGTH = 0x44,
290 AUD_BUF_B_ADDR = 0x48,
291 AUD_BUF_B_LENGTH = 0x4c,
292 AUD_BUF_C_ADDR = 0x50,
293 AUD_BUF_C_LENGTH = 0x54,
294 AUD_BUF_D_ADDR = 0x58,
295 AUD_BUF_D_LENGTH = 0x5c,
296 AUD_CNTL_ST = 0x60,
297 AUD_HDMI_STATUS = 0x68,
298 AUD_HDMIW_INFOFR = 0x114,
299 };
300
301 /*
302 * Delta changes in HDMI controller register offsets
303 * compare to v1 version
304 */
305
306 enum hdmi_ctrl_reg_offset_v2 {
307 AUD_HDMI_STATUS_v2 = 0x64,
308 AUD_HDMIW_INFOFR_v2 = 0x68,
309 };
310
311 /*
312 * CEA speaker placement:
313 *
314 * FL FLC FC FRC FR
315 *
316 * LFE
317 *
318 * RL RLC RC RRC RR
319 *
320 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M
321 * corresponds to CEA RL/RR; The SMPTE channel _assignment_ C/LFE is
322 * swapped to CEA LFE/FC.
323 */
324 enum cea_speaker_placement {
325 FL = (1 << 0), /* Front Left */
326 FC = (1 << 1), /* Front Center */
327 FR = (1 << 2), /* Front Right */
328 FLC = (1 << 3), /* Front Left Center */
329 FRC = (1 << 4), /* Front Right Center */
330 RL = (1 << 5), /* Rear Left */
331 RC = (1 << 6), /* Rear Center */
332 RR = (1 << 7), /* Rear Right */
333 RLC = (1 << 8), /* Rear Left Center */
334 RRC = (1 << 9), /* Rear Right Center */
335 LFE = (1 << 10), /* Low Frequency Effect */
336 };
337
338 struct cea_channel_speaker_allocation {
339 int ca_index;
340 int speakers[8];
341
342 /* derived values, just for convenience */
343 int channels;
344 int spk_mask;
345 };
346
347 struct channel_map_table {
348 unsigned char map; /* ALSA API channel map position */
349 unsigned char cea_slot; /* CEA slot value */
350 int spk_mask; /* speaker position bit mask */
351 };
352
353 /**
354 * union aud_cfg - Audio configuration
355 *
356 * @cfg_regx: individual register bits
357 * @cfg_regval: full register value
358 *
359 */
360 union aud_cfg {
361 struct {
362 u32 aud_en:1;
363 u32 layout:1;
364 u32 fmt:2;
365 u32 num_ch:2;
366 u32 rsvd0:1;
367 u32 set:1;
368 u32 flat:1;
369 u32 val_bit:1;
370 u32 user_bit:1;
371 u32 underrun:1;
372 u32 rsvd1:20;
373 } cfg_regx;
374 struct {
375 u32 aud_en:1;
376 u32 layout:1;
377 u32 fmt:2;
378 u32 num_ch:3;
379 u32 set:1;
380 u32 flat:1;
381 u32 val_bit:1;
382 u32 user_bit:1;
383 u32 underrun:1;
384 u32 packet_mode:1;
385 u32 left_align:1;
386 u32 bogus_sample:1;
387 u32 dp_modei:1;
388 u32 rsvd:16;
389 } cfg_regx_v2;
390 u32 cfg_regval;
391 };
392
393 /**
394 * union aud_ch_status_0 - Audio Channel Status 0 Attributes
395 *
396 * @status_0_regx:individual register bits
397 * @status_0_regval:full register value
398 *
399 */
400 union aud_ch_status_0 {
401 struct {
402 u32 ch_status:1;
403 u32 lpcm_id:1;
404 u32 cp_info:1;
405 u32 format:3;
406 u32 mode:2;
407 u32 ctg_code:8;
408 u32 src_num:4;
409 u32 ch_num:4;
410 u32 samp_freq:4;
411 u32 clk_acc:2;
412 u32 rsvd:2;
413 } status_0_regx;
414 u32 status_0_regval;
415 };
416
417 /**
418 * union aud_ch_status_1 - Audio Channel Status 1 Attributes
419 *
420 * @status_1_regx: individual register bits
421 * @status_1_regval: full register value
422 *
423 */
424 union aud_ch_status_1 {
425 struct {
426 u32 max_wrd_len:1;
427 u32 wrd_len:3;
428 u32 rsvd:28;
429 } status_1_regx;
430 u32 status_1_regval;
431 };
432
433 /**
434 * union aud_hdmi_cts - CTS register
435 *
436 * @cts_regx: individual register bits
437 * @cts_regval: full register value
438 *
439 */
440 union aud_hdmi_cts {
441 struct {
442 u32 cts_val:20;
443 u32 en_cts_prog:1;
444 u32 rsvd:11;
445 } cts_regx;
446 struct {
447 u32 cts_val:24;
448 u32 en_cts_prog:1;
449 u32 rsvd:7;
450 } cts_regx_v2;
451 u32 cts_regval;
452 };
453
454 /**
455 * union aud_hdmi_n_enable - N register
456 *
457 * @n_regx: individual register bits
458 * @n_regval: full register value
459 *
460 */
461 union aud_hdmi_n_enable {
462 struct {
463 u32 n_val:20;
464 u32 en_n_prog:1;
465 u32 rsvd:11;
466 } n_regx;
467 struct {
468 u32 n_val:24;
469 u32 en_n_prog:1;
470 u32 rsvd:7;
471 } n_regx_v2;
472 u32 n_regval;
473 };
474
475 /**
476 * union aud_buf_config - Audio Buffer configurations
477 *
478 * @buf_cfg_regx: individual register bits
479 * @buf_cfgval: full register value
480 *
481 */
482 union aud_buf_config {
483 struct {
484 u32 fifo_width:8;
485 u32 rsvd0:8;
486 u32 aud_delay:8;
487 u32 rsvd1:8;
488 } buf_cfg_regx;
489 struct {
490 u32 audio_fifo_watermark:8;
491 u32 dma_fifo_watermark:3;
492 u32 rsvd0:5;
493 u32 aud_delay:8;
494 u32 rsvd1:8;
495 } buf_cfg_regx_v2;
496 u32 buf_cfgval;
497 };
498
499 /**
500 * union aud_buf_ch_swap - Audio Sample Swapping offset
501 *
502 * @buf_ch_swap_regx: individual register bits
503 * @buf_ch_swap_val: full register value
504 *
505 */
506 union aud_buf_ch_swap {
507 struct {
508 u32 first_0:3;
509 u32 second_0:3;
510 u32 first_1:3;
511 u32 second_1:3;
512 u32 first_2:3;
513 u32 second_2:3;
514 u32 first_3:3;
515 u32 second_3:3;
516 u32 rsvd:8;
517 } buf_ch_swap_regx;
518 u32 buf_ch_swap_val;
519 };
520
521 /**
522 * union aud_buf_addr - Address for Audio Buffer
523 *
524 * @buf_addr_regx: individual register bits
525 * @buf_addr_val: full register value
526 *
527 */
528 union aud_buf_addr {
529 struct {
530 u32 valid:1;
531 u32 intr_en:1;
532 u32 rsvd:4;
533 u32 addr:26;
534 } buf_addr_regx;
535 u32 buf_addr_val;
536 };
537
538 /**
539 * union aud_buf_len - Length of Audio Buffer
540 *
541 * @buf_len_regx: individual register bits
542 * @buf_len_val: full register value
543 *
544 */
545 union aud_buf_len {
546 struct {
547 u32 buf_len:20;
548 u32 rsvd:12;
549 } buf_len_regx;
550 u32 buf_len_val;
551 };
552
553 /**
554 * union aud_ctrl_st - Audio Control State Register offset
555 *
556 * @ctrl_regx: individual register bits
557 * @ctrl_val: full register value
558 *
559 */
560 union aud_ctrl_st {
561 struct {
562 u32 ram_addr:4;
563 u32 eld_ack:1;
564 u32 eld_addr:4;
565 u32 eld_buf_size:5;
566 u32 eld_valid:1;
567 u32 cp_ready:1;
568 u32 dip_freq:2;
569 u32 dip_idx:3;
570 u32 dip_en_sta:4;
571 u32 rsvd:7;
572 } ctrl_regx;
573 u32 ctrl_val;
574 };
575
576 /**
577 * union aud_info_frame1 - Audio HDMI Widget Data Island Packet offset
578 *
579 * @fr1_regx: individual register bits
580 * @fr1_val: full register value
581 *
582 */
583 union aud_info_frame1 {
584 struct {
585 u32 pkt_type:8;
586 u32 ver_num:8;
587 u32 len:5;
588 u32 rsvd:11;
589 } fr1_regx;
590 u32 fr1_val;
591 };
592
593 /**
594 * union aud_info_frame2 - DIP frame 2
595 *
596 * @fr2_regx: individual register bits
597 * @fr2_val: full register value
598 *
599 */
600 union aud_info_frame2 {
601 struct {
602 u32 chksum:8;
603 u32 chnl_cnt:3;
604 u32 rsvd0:1;
605 u32 coding_type:4;
606 u32 smpl_size:2;
607 u32 smpl_freq:3;
608 u32 rsvd1:3;
609 u32 format:8;
610 } fr2_regx;
611 u32 fr2_val;
612 };
613
614 /**
615 * union aud_info_frame3 - DIP frame 3
616 *
617 * @fr3_regx: individual register bits
618 * @fr3_val: full register value
619 *
620 */
621 union aud_info_frame3 {
622 struct {
623 u32 chnl_alloc:8;
624 u32 rsvd0:3;
625 u32 lsv:4;
626 u32 dm_inh:1;
627 u32 rsvd1:16;
628 } fr3_regx;
629 u32 fr3_val;
630 };
631
632 enum hdmi_connector_status {
633 hdmi_connector_status_connected = 1,
634 hdmi_connector_status_disconnected = 2,
635 hdmi_connector_status_unknown = 3,
636 };
637
638 #define HDMI_AUDIO_UNDERRUN (1UL<<31)
639 #define HDMI_AUDIO_BUFFER_DONE (1UL<<29)
640
641
642 #define PORT_ENABLE (1 << 31)
643 #define SDVO_AUDIO_ENABLE (1 << 6)
644
645 enum had_caps_list {
646 HAD_GET_ELD = 1,
647 HAD_GET_DISPLAY_RATE,
648 HAD_GET_DP_OUTPUT,
649 HAD_GET_LINK_RATE,
650 HAD_SET_ENABLE_AUDIO,
651 HAD_SET_DISABLE_AUDIO,
652 HAD_SET_ENABLE_AUDIO_INT,
653 HAD_SET_DISABLE_AUDIO_INT,
654 };
655
656 enum had_event_type {
657 HAD_EVENT_HOT_PLUG = 1,
658 HAD_EVENT_HOT_UNPLUG,
659 HAD_EVENT_MODE_CHANGING,
660 HAD_EVENT_AUDIO_BUFFER_DONE,
661 HAD_EVENT_AUDIO_BUFFER_UNDERRUN,
662 HAD_EVENT_QUERY_IS_AUDIO_BUSY,
663 HAD_EVENT_QUERY_IS_AUDIO_SUSPENDED,
664 };
665
666 /*
667 * HDMI Display Controller Audio Interface
668 *
669 */
670 typedef int (*had_event_call_back) (enum had_event_type event_type,
671 void *ctxt_info);
672
673 struct hdmi_audio_registers_ops {
674 int (*hdmi_audio_get_register_base)(u32 **reg_base,
675 u32 *config_offset);
676 int (*hdmi_audio_read_register)(u32 reg_addr, u32 *data);
677 int (*hdmi_audio_write_register)(u32 reg_addr, u32 data);
678 int (*hdmi_audio_read_modify)(u32 reg_addr, u32 data,
679 u32 mask);
680 };
681
682 struct hdmi_audio_query_set_ops {
683 int (*hdmi_audio_get_caps)(enum had_caps_list query_element,
684 void *capabilties);
685 int (*hdmi_audio_set_caps)(enum had_caps_list set_element,
686 void *capabilties);
687 };
688
689 struct hdmi_audio_event {
690 int type;
691 };
692
693 struct snd_intel_had_interface {
694 const char *name;
695 int (*query)(void *had_data, struct hdmi_audio_event event);
696 int (*suspend)(void *had_data, struct hdmi_audio_event event);
697 int (*resume)(void *had_data);
698 };
699
700 bool mid_hdmi_audio_is_busy(void *dev);
701 bool mid_hdmi_audio_suspend(void *dev);
702 void mid_hdmi_audio_resume(void *dev);
703 void mid_hdmi_audio_signal_event(enum had_event_type event);
704 int mid_hdmi_audio_setup(
705 had_event_call_back audio_callbacks,
706 struct hdmi_audio_registers_ops *reg_ops,
707 struct hdmi_audio_query_set_ops *query_ops);
708 int mid_hdmi_audio_register(
709 struct snd_intel_had_interface *driver,
710 void *had_data);
711
712 #endif