2 * intel_hdmi_lpe_audio.h - Intel HDMI LPE audio driver
4 * Copyright (C) 2016 Intel Corp
5 * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
6 * Ramesh Babu K V <ramesh.babu@intel.com>
7 * Vaibhav Agarwal <vaibhav.agarwal@intel.com>
8 * Jerome Anand <jerome.anand@intel.com>
9 * Aravind Siddappaji <aravindx.siddappaji@intel.com>
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
23 #ifndef __INTEL_HDMI_LPE_AUDIO_H
24 #define __INTEL_HDMI_LPE_AUDIO_H
26 #include <linux/types.h>
27 #include <sound/initval.h>
28 #include <linux/version.h>
29 #include <linux/pm_runtime.h>
30 #include <sound/asoundef.h>
31 #include <sound/control.h>
32 #include <sound/pcm.h>
34 #define AUD_CONFIG_VALID_BIT (1<<9)
35 #define AUD_CONFIG_DP_MODE (1<<15)
36 #define AUD_CONFIG_BLOCK_BIT (1<<7)
38 #define HMDI_LPE_AUDIO_DRIVER_NAME "intel-hdmi-lpe-audio"
39 #define HAD_MAX_DEVICES 1
40 #define HAD_MIN_CHANNEL 2
41 #define HAD_MAX_CHANNEL 8
42 #define HAD_NUM_OF_RING_BUFS 4
44 /* Assume 192KHz, 8channel, 25msec period */
45 #define HAD_MAX_BUFFER (600*1024)
46 #define HAD_MIN_BUFFER (32*1024)
47 #define HAD_MAX_PERIODS 4
48 #define HAD_MIN_PERIODS 4
49 #define HAD_MAX_PERIOD_BYTES (HAD_MAX_BUFFER/HAD_MIN_PERIODS)
50 #define HAD_MIN_PERIOD_BYTES 256
51 #define HAD_FIFO_SIZE 0 /* fifo not being used */
52 #define MAX_SPEAKERS 8
54 #define AUD_SAMPLE_RATE_32 32000
55 #define AUD_SAMPLE_RATE_44_1 44100
56 #define AUD_SAMPLE_RATE_48 48000
57 #define AUD_SAMPLE_RATE_88_2 88200
58 #define AUD_SAMPLE_RATE_96 96000
59 #define AUD_SAMPLE_RATE_176_4 176400
60 #define AUD_SAMPLE_RATE_192 192000
62 #define HAD_MIN_RATE AUD_SAMPLE_RATE_32
63 #define HAD_MAX_RATE AUD_SAMPLE_RATE_192
65 #define DIS_SAMPLE_RATE_25_2 25200
66 #define DIS_SAMPLE_RATE_27 27000
67 #define DIS_SAMPLE_RATE_54 54000
68 #define DIS_SAMPLE_RATE_74_25 74250
69 #define DIS_SAMPLE_RATE_148_5 148500
70 #define HAD_REG_WIDTH 0x08
71 #define HAD_MAX_HW_BUFS 0x04
72 #define HAD_MAX_DIP_WORDS 16
73 #define INTEL_HAD "IntelHdmiLpeAudio"
76 #define DP_2_7_GHZ 270000
77 #define DP_1_62_GHZ 162000
80 #define AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL 1988
81 #define AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL 2740
82 #define AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL 2982
83 #define AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL 5480
84 #define AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL 5965
85 #define AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL 10961
86 #define HAD_MAX_RATE_DP_2_7_MAUD_VAL 11930
87 #define AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL 3314
88 #define AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL 4567
89 #define AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL 4971
90 #define AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL 9134
91 #define AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL 9942
92 #define AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL 18268
93 #define HAD_MAX_RATE_DP_1_62_MAUD_VAL 19884
96 #define DP_NAUD_VAL 32768
98 /* _AUD_CONFIG register MASK */
99 #define AUD_CONFIG_MASK_UNDERRUN 0xC0000000
100 #define AUD_CONFIG_MASK_SRDBG 0x00000002
101 #define AUD_CONFIG_MASK_FUNCRST 0x00000001
104 #define HAD_SUSPEND_DELAY 1000
106 #define OTM_HDMI_ELD_SIZE 128
108 union otm_hdmi_eld_t
{
109 unsigned char eld_data
[OTM_HDMI_ELD_SIZE
];
111 /* Byte[0] = ELD Version Number */
115 unsigned char reserved
:3; /* Reserf */
116 unsigned char eld_ver
:5; /* ELD Version Number */
118 * 00001b - first rev, obsoleted
119 * 00010b - version 2, supporting CEA version
121 * 00011b:11111b - reserved
127 /* Byte[1] = Vendor Version Field */
129 unsigned char vendor_version
;
131 unsigned char reserved1
:3;
132 unsigned char veld_ver
:5; /* Version number of the ELD
133 * extension. This value is
134 * provisioned and unique to
140 /* Byte[2] = Baseline Length field */
141 unsigned char baseline_eld_length
; /* Length of the Baseline structure
145 /* Byte [3] = Reserved for future use */
148 /* Starting of the BaseLine EELD structure
149 * Byte[4] = Monitor Name Length
155 unsigned char cea_edid_rev_id
:3;
159 /* Byte[5] = Capabilities */
161 unsigned char capabilities
;
163 unsigned char hdcp
:1; /* HDCP support */
164 unsigned char ai_support
:1; /* AI support */
165 unsigned char connection_type
:2; /* Connection type
172 unsigned char sadc
:4; /* Indicates number of 3 bytes
173 * Short Audio Descriptors.
178 /* Byte[6] = Audio Synch Delay */
179 unsigned char audio_synch_delay
; /* Amount of time reported by the
180 * sink that the video trails audio
184 /* Byte[7] = Speaker Allocation Block */
186 unsigned char speaker_allocation_block
;
188 unsigned char flr
:1; /*Front Left and Right channels*/
189 unsigned char lfe
:1; /*Low Frequency Effect channel*/
190 unsigned char fc
:1; /*Center transmission channel*/
191 unsigned char rlr
:1; /*Rear Left and Right channels*/
192 unsigned char rc
:1; /*Rear Center channel*/
193 unsigned char flrc
:1; /*Front left and Right of Center
194 *transmission channels
196 unsigned char rlrc
:1; /*Rear left and Right of Center
197 *transmission channels
199 unsigned char reserved3
:1; /* Reserved */
203 /* Byte[8 - 15] - 8 Byte port identification value */
204 unsigned char port_id_value
[8];
206 /* Byte[16 - 17] - 2 Byte Manufacturer ID */
207 unsigned char manufacturer_id
[2];
209 /* Byte[18 - 19] - 2 Byte Product ID */
210 unsigned char product_id
[2];
212 /* Byte [20-83] - 64 Bytes of BaseLine Data */
213 unsigned char mn_sand_sads
[64]; /* This will include
214 * - ASCII string of Monitor name
215 * - List of 3 byte SADs
219 /* Vendor ELD Block should continue here!
220 * No Vendor ELD block defined as of now.
226 * enum had_status - Audio stream states
228 * @STREAM_INIT: Stream initialized
229 * @STREAM_RUNNING: Stream running
230 * @STREAM_PAUSED: Stream paused
231 * @STREAM_DROPPED: Stream dropped
233 enum had_stream_status
{
241 * enum had_status_stream - HAD stream states
243 enum had_status_stream
{
248 enum had_drv_status
{
251 HAD_DRV_DISCONNECTED
,
256 /* enum intel_had_aud_buf_type - HDMI controller ring buffer types */
257 enum intel_had_aud_buf_type
{
271 /* HDMI Controller register offsets - audio domain common */
272 /* Base address for below regs = 0x65000 */
273 enum hdmi_ctrl_reg_offset_common
{
274 AUDIO_HDMI_CONFIG_A
= 0x000,
275 AUDIO_HDMI_CONFIG_B
= 0x800,
276 AUDIO_HDMI_CONFIG_C
= 0x900,
278 /* HDMI controller register offsets */
279 enum hdmi_ctrl_reg_offset_v1
{
281 AUD_CH_STATUS_0
= 0x08,
282 AUD_CH_STATUS_1
= 0x0C,
285 AUD_SAMPLE_RATE
= 0x18,
286 AUD_BUF_CONFIG
= 0x20,
287 AUD_BUF_CH_SWAP
= 0x24,
288 AUD_BUF_A_ADDR
= 0x40,
289 AUD_BUF_A_LENGTH
= 0x44,
290 AUD_BUF_B_ADDR
= 0x48,
291 AUD_BUF_B_LENGTH
= 0x4c,
292 AUD_BUF_C_ADDR
= 0x50,
293 AUD_BUF_C_LENGTH
= 0x54,
294 AUD_BUF_D_ADDR
= 0x58,
295 AUD_BUF_D_LENGTH
= 0x5c,
297 AUD_HDMI_STATUS
= 0x68,
298 AUD_HDMIW_INFOFR
= 0x114,
302 * Delta changes in HDMI controller register offsets
303 * compare to v1 version
306 enum hdmi_ctrl_reg_offset_v2
{
307 AUD_HDMI_STATUS_v2
= 0x64,
308 AUD_HDMIW_INFOFR_v2
= 0x68,
312 * CEA speaker placement:
320 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M
321 * corresponds to CEA RL/RR; The SMPTE channel _assignment_ C/LFE is
322 * swapped to CEA LFE/FC.
324 enum cea_speaker_placement
{
325 FL
= (1 << 0), /* Front Left */
326 FC
= (1 << 1), /* Front Center */
327 FR
= (1 << 2), /* Front Right */
328 FLC
= (1 << 3), /* Front Left Center */
329 FRC
= (1 << 4), /* Front Right Center */
330 RL
= (1 << 5), /* Rear Left */
331 RC
= (1 << 6), /* Rear Center */
332 RR
= (1 << 7), /* Rear Right */
333 RLC
= (1 << 8), /* Rear Left Center */
334 RRC
= (1 << 9), /* Rear Right Center */
335 LFE
= (1 << 10), /* Low Frequency Effect */
338 struct cea_channel_speaker_allocation
{
342 /* derived values, just for convenience */
347 struct channel_map_table
{
348 unsigned char map
; /* ALSA API channel map position */
349 unsigned char cea_slot
; /* CEA slot value */
350 int spk_mask
; /* speaker position bit mask */
354 * union aud_cfg - Audio configuration
356 * @cfg_regx: individual register bits
357 * @cfg_regval: full register value
394 * union aud_ch_status_0 - Audio Channel Status 0 Attributes
396 * @status_0_regx:individual register bits
397 * @status_0_regval:full register value
400 union aud_ch_status_0
{
418 * union aud_ch_status_1 - Audio Channel Status 1 Attributes
420 * @status_1_regx: individual register bits
421 * @status_1_regval: full register value
424 union aud_ch_status_1
{
434 * union aud_hdmi_cts - CTS register
436 * @cts_regx: individual register bits
437 * @cts_regval: full register value
455 * union aud_hdmi_n_enable - N register
457 * @n_regx: individual register bits
458 * @n_regval: full register value
461 union aud_hdmi_n_enable
{
476 * union aud_buf_config - Audio Buffer configurations
478 * @buf_cfg_regx: individual register bits
479 * @buf_cfgval: full register value
482 union aud_buf_config
{
490 u32 audio_fifo_watermark
:8;
491 u32 dma_fifo_watermark
:3;
500 * union aud_buf_ch_swap - Audio Sample Swapping offset
502 * @buf_ch_swap_regx: individual register bits
503 * @buf_ch_swap_val: full register value
506 union aud_buf_ch_swap
{
522 * union aud_buf_addr - Address for Audio Buffer
524 * @buf_addr_regx: individual register bits
525 * @buf_addr_val: full register value
539 * union aud_buf_len - Length of Audio Buffer
541 * @buf_len_regx: individual register bits
542 * @buf_len_val: full register value
554 * union aud_ctrl_st - Audio Control State Register offset
556 * @ctrl_regx: individual register bits
557 * @ctrl_val: full register value
577 * union aud_info_frame1 - Audio HDMI Widget Data Island Packet offset
579 * @fr1_regx: individual register bits
580 * @fr1_val: full register value
583 union aud_info_frame1
{
594 * union aud_info_frame2 - DIP frame 2
596 * @fr2_regx: individual register bits
597 * @fr2_val: full register value
600 union aud_info_frame2
{
615 * union aud_info_frame3 - DIP frame 3
617 * @fr3_regx: individual register bits
618 * @fr3_val: full register value
621 union aud_info_frame3
{
632 enum hdmi_connector_status
{
633 hdmi_connector_status_connected
= 1,
634 hdmi_connector_status_disconnected
= 2,
635 hdmi_connector_status_unknown
= 3,
638 #define HDMI_AUDIO_UNDERRUN (1UL<<31)
639 #define HDMI_AUDIO_BUFFER_DONE (1UL<<29)
642 #define PORT_ENABLE (1 << 31)
643 #define SDVO_AUDIO_ENABLE (1 << 6)
647 HAD_GET_DISPLAY_RATE
,
650 HAD_SET_ENABLE_AUDIO
,
651 HAD_SET_DISABLE_AUDIO
,
652 HAD_SET_ENABLE_AUDIO_INT
,
653 HAD_SET_DISABLE_AUDIO_INT
,
656 enum had_event_type
{
657 HAD_EVENT_HOT_PLUG
= 1,
658 HAD_EVENT_HOT_UNPLUG
,
659 HAD_EVENT_MODE_CHANGING
,
660 HAD_EVENT_AUDIO_BUFFER_DONE
,
661 HAD_EVENT_AUDIO_BUFFER_UNDERRUN
,
662 HAD_EVENT_QUERY_IS_AUDIO_BUSY
,
663 HAD_EVENT_QUERY_IS_AUDIO_SUSPENDED
,
667 * HDMI Display Controller Audio Interface
670 typedef int (*had_event_call_back
) (enum had_event_type event_type
,
673 struct hdmi_audio_registers_ops
{
674 int (*hdmi_audio_get_register_base
)(u32
**reg_base
,
676 int (*hdmi_audio_read_register
)(u32 reg_addr
, u32
*data
);
677 int (*hdmi_audio_write_register
)(u32 reg_addr
, u32 data
);
678 int (*hdmi_audio_read_modify
)(u32 reg_addr
, u32 data
,
682 struct hdmi_audio_query_set_ops
{
683 int (*hdmi_audio_get_caps
)(enum had_caps_list query_element
,
685 int (*hdmi_audio_set_caps
)(enum had_caps_list set_element
,
689 struct hdmi_audio_event
{
693 struct snd_intel_had_interface
{
695 int (*query
)(void *had_data
, struct hdmi_audio_event event
);
696 int (*suspend
)(void *had_data
, struct hdmi_audio_event event
);
697 int (*resume
)(void *had_data
);
700 bool mid_hdmi_audio_is_busy(void *dev
);
701 bool mid_hdmi_audio_suspend(void *dev
);
702 void mid_hdmi_audio_resume(void *dev
);
703 void mid_hdmi_audio_signal_event(enum had_event_type event
);
704 int mid_hdmi_audio_setup(
705 had_event_call_back audio_callbacks
,
706 struct hdmi_audio_registers_ops
*reg_ops
,
707 struct hdmi_audio_query_set_ops
*query_ops
);
708 int mid_hdmi_audio_register(
709 struct snd_intel_had_interface
*driver
,