sound/x86/intel_hdmi_lpe_audio.h

   1 /*
   2  *   intel_hdmi_lpe_audio.h - Intel HDMI LPE audio driver
   3  *
   4  *  Copyright (C) 2016 Intel Corp
   5  *  Authors:    Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
   6  *              Ramesh Babu K V <ramesh.babu@intel.com>
   7  *              Vaibhav Agarwal <vaibhav.agarwal@intel.com>
   8  *              Jerome Anand <jerome.anand@intel.com>
   9  *              Aravind Siddappaji <aravindx.siddappaji@intel.com>
  10  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  11  *
  12  *  This program is free software; you can redistribute it and/or modify
  13  *  it under the terms of the GNU General Public License as published by
  14  *  the Free Software Foundation; version 2 of the License.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but
  17  *  WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  *  General Public License for more details.
  20  *
  21  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  22  */
  23 #ifndef __INTEL_HDMI_LPE_AUDIO_H
  24 #define __INTEL_HDMI_LPE_AUDIO_H
  25
  26 #include <linux/types.h>
  27 #include <sound/initval.h>
  28 #include <linux/version.h>
  29 #include <linux/pm_runtime.h>
  30 #include <sound/asoundef.h>
  31 #include <sound/control.h>
  32 #include <sound/pcm.h>
  33
  34 #define HMDI_LPE_AUDIO_DRIVER_NAME              "intel-hdmi-lpe-audio"
  35 #define HAD_MAX_DEVICES         1
  36 #define HAD_MIN_CHANNEL         2
  37 #define HAD_MAX_CHANNEL         8
  38 #define HAD_NUM_OF_RING_BUFS    4
  39
  40 /* Assume 192KHz, 8channel, 25msec period */
  41 #define HAD_MAX_BUFFER          (600*1024)
  42 #define HAD_MIN_BUFFER          (32*1024)
  43 #define HAD_MAX_PERIODS         4
  44 #define HAD_MIN_PERIODS         4
  45 #define HAD_MAX_PERIOD_BYTES    (HAD_MAX_BUFFER/HAD_MIN_PERIODS)
  46 #define HAD_MIN_PERIOD_BYTES    256
  47 #define HAD_FIFO_SIZE           0 /* fifo not being used */
  48 #define MAX_SPEAKERS            8
  49
  50 #define AUD_SAMPLE_RATE_32      32000
  51 #define AUD_SAMPLE_RATE_44_1    44100
  52 #define AUD_SAMPLE_RATE_48      48000
  53 #define AUD_SAMPLE_RATE_88_2    88200
  54 #define AUD_SAMPLE_RATE_96      96000
  55 #define AUD_SAMPLE_RATE_176_4   176400
  56 #define AUD_SAMPLE_RATE_192     192000
  57
  58 #define HAD_MIN_RATE            AUD_SAMPLE_RATE_32
  59 #define HAD_MAX_RATE            AUD_SAMPLE_RATE_192
  60
  61 #define DIS_SAMPLE_RATE_25_2    25200
  62 #define DIS_SAMPLE_RATE_27      27000
  63 #define DIS_SAMPLE_RATE_54      54000
  64 #define DIS_SAMPLE_RATE_74_25   74250
  65 #define DIS_SAMPLE_RATE_148_5   148500
  66 #define HAD_REG_WIDTH           0x08
  67 #define HAD_MAX_HW_BUFS         0x04
  68 #define HAD_MAX_DIP_WORDS               16
  69 #define INTEL_HAD               "IntelHdmiLpeAudio"
  70
  71 /* _AUD_CONFIG register MASK */
  72 #define AUD_CONFIG_MASK_UNDERRUN        0xC0000000
  73 #define AUD_CONFIG_MASK_SRDBG           0x00000002
  74 #define AUD_CONFIG_MASK_FUNCRST         0x00000001
  75
  76 #define MAX_CNT                 0xFF
  77 #define HAD_SUSPEND_DELAY       1000
  78
  79 #define OTM_HDMI_ELD_SIZE 128
  80
  81 union otm_hdmi_eld_t {
  82         unsigned char eld_data[OTM_HDMI_ELD_SIZE];
  83         struct {
  84                 /* Byte[0] = ELD Version Number */
  85                 union {
  86                         unsigned char   byte0;
  87                         struct {
  88                                 unsigned char reserved:3; /* Reserf */
  89                                 unsigned char eld_ver:5; /* ELD Version Number */
  90                                 /* 00000b - reserved
  91                                  * 00001b - first rev, obsoleted
  92                                  * 00010b - version 2, supporting CEA version
  93                                  *                      861D or below
  94                                  * 00011b:11111b - reserved
  95                                  * for future
  96                                  */
  97                         };
  98                 };
  99
 100                 /* Byte[1] = Vendor Version Field */
 101                 union {
 102                         unsigned char vendor_version;
 103                         struct {
 104                                 unsigned char reserved1:3;
 105                                 unsigned char veld_ver:5; /* Version number of the ELD
 106                                                      * extension. This value is
 107                                                      * provisioned and unique to
 108                                                      * each vendor.
 109                                                      */
 110                         };
 111                 };
 112
 113                 /* Byte[2] = Baseline Length field */
 114                 unsigned char baseline_eld_length; /* Length of the Baseline structure
 115                                               * divided by Four.
 116                                               */
 117
 118                 /* Byte [3] = Reserved for future use */
 119                 unsigned char byte3;
 120
 121                 /* Starting of the BaseLine EELD structure
 122                  * Byte[4] = Monitor Name Length
 123                  */
 124                 union {
 125                         unsigned char byte4;
 126                         struct {
 127                                 unsigned char mnl:5;
 128                                 unsigned char cea_edid_rev_id:3;
 129                         };
 130                 };
 131
 132                 /* Byte[5] = Capabilities */
 133                 union {
 134                         unsigned char capabilities;
 135                         struct {
 136                                 unsigned char hdcp:1; /* HDCP support */
 137                                 unsigned char ai_support:1;   /* AI support */
 138                                 unsigned char connection_type:2; /* Connection type
 139                                                             * 00 - HDMI
 140                                                             * 01 - DP
 141                                                             * 10 -11  Reserved
 142                                                             * for future
 143                                                             * connection types
 144                                                             */
 145                                 unsigned char sadc:4; /* Indicates number of 3 bytes
 146                                                  * Short Audio Descriptors.
 147                                                  */
 148                         };
 149                 };
 150
 151                 /* Byte[6] = Audio Synch Delay */
 152                 unsigned char audio_synch_delay; /* Amount of time reported by the
 153                                             * sink that the video trails audio
 154                                             * in milliseconds.
 155                                             */
 156
 157                 /* Byte[7] = Speaker Allocation Block */
 158                 union {
 159                         unsigned char speaker_allocation_block;
 160                         struct {
 161                                 unsigned char flr:1; /*Front Left and Right channels*/
 162                                 unsigned char lfe:1; /*Low Frequency Effect channel*/
 163                                 unsigned char fc:1;  /*Center transmission channel*/
 164                                 unsigned char rlr:1; /*Rear Left and Right channels*/
 165                                 unsigned char rc:1; /*Rear Center channel*/
 166                                 unsigned char flrc:1; /*Front left and Right of Center
 167                                                  *transmission channels
 168                                                  */
 169                                 unsigned char rlrc:1; /*Rear left and Right of Center
 170                                                  *transmission channels
 171                                                  */
 172                                 unsigned char reserved3:1; /* Reserved */
 173                         };
 174                 };
 175
 176                 /* Byte[8 - 15] - 8 Byte port identification value */
 177                 unsigned char port_id_value[8];
 178
 179                 /* Byte[16 - 17] - 2 Byte Manufacturer ID */
 180                 unsigned char manufacturer_id[2];
 181
 182                 /* Byte[18 - 19] - 2 Byte Product ID */
 183                 unsigned char product_id[2];
 184
 185                 /* Byte [20-83] - 64 Bytes of BaseLine Data */
 186                 unsigned char mn_sand_sads[64]; /* This will include
 187                                            * - ASCII string of Monitor name
 188                                            * - List of 3 byte SADs
 189                                            * - Zero padding
 190                                            */
 191
 192                 /* Vendor ELD Block should continue here!
 193                  * No Vendor ELD block defined as of now.
 194                  */
 195         } __packed;
 196 };
 197
 198 /**
 199  * enum had_status - Audio stream states
 200  *
 201  * @STREAM_INIT: Stream initialized
 202  * @STREAM_RUNNING: Stream running
 203  * @STREAM_PAUSED: Stream paused
 204  * @STREAM_DROPPED: Stream dropped
 205  */
 206 enum had_stream_status {
 207         STREAM_INIT = 0,
 208         STREAM_RUNNING = 1,
 209         STREAM_PAUSED = 2,
 210         STREAM_DROPPED = 3
 211 };
 212
 213 /**
 214  * enum had_status_stream - HAD stream states
 215  */
 216 enum had_status_stream {
 217         HAD_INIT = 0,
 218         HAD_RUNNING_STREAM,
 219 };
 220
 221 enum had_drv_status {
 222         HAD_DRV_CONNECTED,
 223         HAD_DRV_RUNNING,
 224         HAD_DRV_DISCONNECTED,
 225         HAD_DRV_SUSPENDED,
 226         HAD_DRV_ERR,
 227 };
 228
 229 /* enum intel_had_aud_buf_type - HDMI controller ring buffer types */
 230 enum intel_had_aud_buf_type {
 231         HAD_BUF_TYPE_A = 0,
 232         HAD_BUF_TYPE_B = 1,
 233         HAD_BUF_TYPE_C = 2,
 234         HAD_BUF_TYPE_D = 3,
 235 };
 236
 237 enum num_aud_ch {
 238         CH_STEREO = 0,
 239         CH_THREE_FOUR = 1,
 240         CH_FIVE_SIX = 2,
 241         CH_SEVEN_EIGHT = 3
 242 };
 243
 244 /* HDMI Controller register offsets - audio domain common */
 245 /* Base address for below regs = 0x65000 */
 246 enum hdmi_ctrl_reg_offset_common {
 247         AUDIO_HDMI_CONFIG_A     = 0x000,
 248         AUDIO_HDMI_CONFIG_B = 0x800,
 249         AUDIO_HDMI_CONFIG_C = 0x900,
 250 };
 251 /* HDMI controller register offsets */
 252 enum hdmi_ctrl_reg_offset_v1 {
 253         AUD_CONFIG              = 0x0,
 254         AUD_CH_STATUS_0         = 0x08,
 255         AUD_CH_STATUS_1         = 0x0C,
 256         AUD_HDMI_CTS            = 0x10,
 257         AUD_N_ENABLE            = 0x14,
 258         AUD_SAMPLE_RATE         = 0x18,
 259         AUD_BUF_CONFIG          = 0x20,
 260         AUD_BUF_CH_SWAP         = 0x24,
 261         AUD_BUF_A_ADDR          = 0x40,
 262         AUD_BUF_A_LENGTH        = 0x44,
 263         AUD_BUF_B_ADDR          = 0x48,
 264         AUD_BUF_B_LENGTH        = 0x4c,
 265         AUD_BUF_C_ADDR          = 0x50,
 266         AUD_BUF_C_LENGTH        = 0x54,
 267         AUD_BUF_D_ADDR          = 0x58,
 268         AUD_BUF_D_LENGTH        = 0x5c,
 269         AUD_CNTL_ST             = 0x60,
 270         AUD_HDMI_STATUS         = 0x68,
 271         AUD_HDMIW_INFOFR        = 0x114,
 272 };
 273
 274 /*
 275  * Delta changes in HDMI controller register offsets
 276  * compare to v1 version
 277  */
 278
 279 enum hdmi_ctrl_reg_offset_v2 {
 280         AUD_HDMI_STATUS_v2      = 0x64,
 281         AUD_HDMIW_INFOFR_v2     = 0x68,
 282 };
 283
 284 /*
 285  *      CEA speaker placement:
 286  *
 287  *      FL  FLC   FC   FRC   FR
 288  *
 289  *                                              LFE
 290  *
 291  *      RL  RLC   RC   RRC   RR
 292  *
 293  *      The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M
 294  *      corresponds to CEA RL/RR; The SMPTE channel _assignment_ C/LFE is
 295  *      swapped to CEA LFE/FC.
 296  */
 297 enum cea_speaker_placement {
 298         FL  = (1 <<  0),        /* Front Left           */
 299         FC  = (1 <<  1),        /* Front Center         */
 300         FR  = (1 <<  2),        /* Front Right          */
 301         FLC = (1 <<  3),        /* Front Left Center    */
 302         FRC = (1 <<  4),        /* Front Right Center   */
 303         RL  = (1 <<  5),        /* Rear Left            */
 304         RC  = (1 <<  6),        /* Rear Center          */
 305         RR  = (1 <<  7),        /* Rear Right           */
 306         RLC = (1 <<  8),        /* Rear Left Center     */
 307         RRC = (1 <<  9),        /* Rear Right Center    */
 308         LFE = (1 << 10),        /* Low Frequency Effect */
 309 };
 310
 311 struct cea_channel_speaker_allocation {
 312         int ca_index;
 313         int speakers[8];
 314
 315         /* derived values, just for convenience */
 316         int channels;
 317         int spk_mask;
 318 };
 319
 320 struct channel_map_table {
 321         unsigned char map;              /* ALSA API channel map position */
 322         unsigned char cea_slot;         /* CEA slot value */
 323         int spk_mask;                   /* speaker position bit mask */
 324 };
 325
 326 /**
 327  * union aud_cfg - Audio configuration
 328  *
 329  * @cfg_regx: individual register bits
 330  * @cfg_regval: full register value
 331  *
 332  */
 333 union aud_cfg {
 334         struct {
 335                 u32 aud_en:1;
 336                 u32 layout:1;
 337                 u32 fmt:2;
 338                 u32 num_ch:2;
 339                 u32 rsvd0:1;
 340                 u32 set:1;
 341                 u32 flat:1;
 342                 u32 val_bit:1;
 343                 u32 user_bit:1;
 344                 u32 underrun:1;
 345                 u32 rsvd1:20;
 346         } cfg_regx;
 347         struct {
 348                 u32 aud_en:1;
 349                 u32 layout:1;
 350                 u32 fmt:2;
 351                 u32 num_ch:3;
 352                 u32 set:1;
 353                 u32 flat:1;
 354                 u32 val_bit:1;
 355                 u32 user_bit:1;
 356                 u32 underrun:1;
 357                 u32 packet_mode:1;
 358                 u32 left_align:1;
 359                 u32 bogus_sample:1;
 360                 u32 dp_modei:1;
 361                 u32 rsvd:16;
 362         } cfg_regx_v2;
 363         u32 cfg_regval;
 364 };
 365
 366 /**
 367  * union aud_ch_status_0 - Audio Channel Status 0 Attributes
 368  *
 369  * @status_0_regx:individual register bits
 370  * @status_0_regval:full register value
 371  *
 372  */
 373 union aud_ch_status_0 {
 374         struct {
 375                 u32 ch_status:1;
 376                 u32 lpcm_id:1;
 377                 u32 cp_info:1;
 378                 u32 format:3;
 379                 u32 mode:2;
 380                 u32 ctg_code:8;
 381                 u32 src_num:4;
 382                 u32 ch_num:4;
 383                 u32 samp_freq:4;
 384                 u32 clk_acc:2;
 385                 u32 rsvd:2;
 386         } status_0_regx;
 387         u32 status_0_regval;
 388 };
 389
 390 /**
 391  * union aud_ch_status_1 - Audio Channel Status 1 Attributes
 392  *
 393  * @status_1_regx: individual register bits
 394  * @status_1_regval: full register value
 395  *
 396  */
 397 union aud_ch_status_1 {
 398         struct {
 399                 u32 max_wrd_len:1;
 400                 u32 wrd_len:3;
 401                 u32 rsvd:28;
 402                 } status_1_regx;
 403         u32 status_1_regval;
 404 };
 405
 406 /**
 407  * union aud_hdmi_cts - CTS register
 408  *
 409  * @cts_regx: individual register bits
 410  * @cts_regval: full register value
 411  *
 412  */
 413 union aud_hdmi_cts {
 414         struct {
 415                 u32 cts_val:20;
 416                 u32 en_cts_prog:1;
 417                 u32 rsvd:11;
 418         } cts_regx;
 419         struct {
 420                 u32 cts_val:24;
 421                 u32 en_cts_prog:1;
 422                 u32 rsvd:7;
 423         } cts_regx_v2;
 424         u32 cts_regval;
 425 };
 426
 427 /**
 428  * union aud_hdmi_n_enable - N register
 429  *
 430  * @n_regx: individual register bits
 431  * @n_regval: full register value
 432  *
 433  */
 434 union aud_hdmi_n_enable {
 435         struct {
 436                 u32 n_val:20;
 437                 u32 en_n_prog:1;
 438                 u32 rsvd:11;
 439         } n_regx;
 440         struct {
 441                 u32 n_val:24;
 442                 u32 en_n_prog:1;
 443                 u32 rsvd:7;
 444         } n_regx_v2;
 445         u32 n_regval;
 446 };
 447
 448 /**
 449  * union aud_buf_config -  Audio Buffer configurations
 450  *
 451  * @buf_cfg_regx: individual register bits
 452  * @buf_cfgval: full register value
 453  *
 454  */
 455 union aud_buf_config {
 456         struct {
 457                 u32 fifo_width:8;
 458                 u32 rsvd0:8;
 459                 u32 aud_delay:8;
 460                 u32 rsvd1:8;
 461         } buf_cfg_regx;
 462         struct {
 463                 u32 audio_fifo_watermark:8;
 464                 u32 dma_fifo_watermark:3;
 465                 u32 rsvd0:5;
 466                 u32 aud_delay:8;
 467                 u32 rsvd1:8;
 468         } buf_cfg_regx_v2;
 469         u32 buf_cfgval;
 470 };
 471
 472 /**
 473  * union aud_buf_ch_swap - Audio Sample Swapping offset
 474  *
 475  * @buf_ch_swap_regx: individual register bits
 476  * @buf_ch_swap_val: full register value
 477  *
 478  */
 479 union aud_buf_ch_swap {
 480         struct {
 481                 u32 first_0:3;
 482                 u32 second_0:3;
 483                 u32 first_1:3;
 484                 u32 second_1:3;
 485                 u32 first_2:3;
 486                 u32 second_2:3;
 487                 u32 first_3:3;
 488                 u32 second_3:3;
 489                 u32 rsvd:8;
 490         } buf_ch_swap_regx;
 491         u32 buf_ch_swap_val;
 492 };
 493
 494 /**
 495  * union aud_buf_addr - Address for Audio Buffer
 496  *
 497  * @buf_addr_regx: individual register bits
 498  * @buf_addr_val: full register value
 499  *
 500  */
 501 union aud_buf_addr {
 502         struct {
 503                 u32 valid:1;
 504                 u32 intr_en:1;
 505                 u32 rsvd:4;
 506                 u32 addr:26;
 507         } buf_addr_regx;
 508         u32 buf_addr_val;
 509 };
 510
 511 /**
 512  * union aud_buf_len - Length of Audio Buffer
 513  *
 514  * @buf_len_regx: individual register bits
 515  * @buf_len_val: full register value
 516  *
 517  */
 518 union aud_buf_len {
 519         struct {
 520                 u32 buf_len:20;
 521                 u32 rsvd:12;
 522         } buf_len_regx;
 523         u32 buf_len_val;
 524 };
 525
 526 /**
 527  * union aud_ctrl_st - Audio Control State Register offset
 528  *
 529  * @ctrl_regx: individual register bits
 530  * @ctrl_val: full register value
 531  *
 532  */
 533 union aud_ctrl_st {
 534         struct {
 535                 u32 ram_addr:4;
 536                 u32 eld_ack:1;
 537                 u32 eld_addr:4;
 538                 u32 eld_buf_size:5;
 539                 u32 eld_valid:1;
 540                 u32 cp_ready:1;
 541                 u32 dip_freq:2;
 542                 u32 dip_idx:3;
 543                 u32 dip_en_sta:4;
 544                 u32 rsvd:7;
 545         } ctrl_regx;
 546         u32 ctrl_val;
 547 };
 548
 549 /**
 550  * union aud_info_frame1 - Audio HDMI Widget Data Island Packet offset
 551  *
 552  * @fr1_regx: individual register bits
 553  * @fr1_val: full register value
 554  *
 555  */
 556 union aud_info_frame1 {
 557         struct {
 558                 u32 pkt_type:8;
 559                 u32 ver_num:8;
 560                 u32 len:5;
 561                 u32 rsvd:11;
 562         } fr1_regx;
 563         u32 fr1_val;
 564 };
 565
 566 /**
 567  * union aud_info_frame2 - DIP frame 2
 568  *
 569  * @fr2_regx: individual register bits
 570  * @fr2_val: full register value
 571  *
 572  */
 573 union aud_info_frame2 {
 574         struct {
 575                 u32 chksum:8;
 576                 u32 chnl_cnt:3;
 577                 u32 rsvd0:1;
 578                 u32 coding_type:4;
 579                 u32 smpl_size:2;
 580                 u32 smpl_freq:3;
 581                 u32 rsvd1:3;
 582                 u32 format:8;
 583         } fr2_regx;
 584         u32 fr2_val;
 585 };
 586
 587 /**
 588  * union aud_info_frame3 - DIP frame 3
 589  *
 590  * @fr3_regx: individual register bits
 591  * @fr3_val: full register value
 592  *
 593  */
 594 union aud_info_frame3 {
 595         struct {
 596                 u32 chnl_alloc:8;
 597                 u32 rsvd0:3;
 598                 u32 lsv:4;
 599                 u32 dm_inh:1;
 600                 u32 rsvd1:16;
 601         } fr3_regx;
 602         u32 fr3_val;
 603 };
 604
 605 enum hdmi_connector_status {
 606         hdmi_connector_status_connected = 1,
 607         hdmi_connector_status_disconnected = 2,
 608         hdmi_connector_status_unknown = 3,
 609 };
 610
 611 #define HDMI_AUDIO_UNDERRUN     (1UL<<31)
 612 #define HDMI_AUDIO_BUFFER_DONE  (1UL<<29)
 613
 614
 615 #define PORT_ENABLE                     (1 << 31)
 616 #define SDVO_AUDIO_ENABLE       (1 << 6)
 617
 618 enum had_caps_list {
 619         HAD_GET_ELD = 1,
 620         HAD_GET_DISPLAY_RATE,
 621         HAD_SET_ENABLE_AUDIO,
 622         HAD_SET_DISABLE_AUDIO,
 623         HAD_SET_ENABLE_AUDIO_INT,
 624         HAD_SET_DISABLE_AUDIO_INT,
 625 };
 626
 627 enum had_event_type {
 628         HAD_EVENT_HOT_PLUG = 1,
 629         HAD_EVENT_HOT_UNPLUG,
 630         HAD_EVENT_MODE_CHANGING,
 631         HAD_EVENT_AUDIO_BUFFER_DONE,
 632         HAD_EVENT_AUDIO_BUFFER_UNDERRUN,
 633         HAD_EVENT_QUERY_IS_AUDIO_BUSY,
 634         HAD_EVENT_QUERY_IS_AUDIO_SUSPENDED,
 635 };
 636
 637 /*
 638  * HDMI Display Controller Audio Interface
 639  *
 640  */
 641 typedef int (*had_event_call_back) (enum had_event_type event_type,
 642                 void *ctxt_info);
 643
 644 struct hdmi_audio_registers_ops {
 645         int (*hdmi_audio_get_register_base)(u32 **reg_base,
 646                         u32 *config_offset);
 647         int (*hdmi_audio_read_register)(u32 reg_addr, u32 *data);
 648         int (*hdmi_audio_write_register)(u32 reg_addr, u32 data);
 649         int (*hdmi_audio_read_modify)(u32 reg_addr, u32 data,
 650                         u32 mask);
 651 };
 652
 653 struct hdmi_audio_query_set_ops {
 654         int (*hdmi_audio_get_caps)(enum had_caps_list query_element,
 655                         void *capabilties);
 656         int (*hdmi_audio_set_caps)(enum had_caps_list set_element,
 657                         void *capabilties);
 658 };
 659
 660 struct hdmi_audio_event {
 661         int type;
 662 };
 663
 664 struct snd_intel_had_interface {
 665         const char *name;
 666         int (*query)(void *had_data, struct hdmi_audio_event event);
 667         int (*suspend)(void *had_data, struct hdmi_audio_event event);
 668         int (*resume)(void *had_data);
 669 };
 670
 671 bool mid_hdmi_audio_is_busy(void *dev);
 672 bool mid_hdmi_audio_suspend(void *dev);
 673 void mid_hdmi_audio_resume(void *dev);
 674 void mid_hdmi_audio_signal_event(enum had_event_type event);
 675 int mid_hdmi_audio_setup(
 676         had_event_call_back audio_callbacks,
 677         struct hdmi_audio_registers_ops *reg_ops,
 678         struct hdmi_audio_query_set_ops *query_ops);
 679 int mid_hdmi_audio_register(
 680         struct snd_intel_had_interface *driver,
 681         void *had_data);
 682
 683 #endif