1 // Copyright 2015 The Rust Project Developers. See the COPYRIGHT
2 // file at the top-level directory of this distribution and at
3 // http://rust-lang.org/COPYRIGHT.
5 // Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
6 // http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
7 // <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
8 // option. This file may not be copied, modified, or distributed
9 // except according to those terms.
11 // DO NOT EDIT: autogenerated by etc/platform-intrinsics/generator.py
12 // ignore-tidy-linelength
14 #![allow(unused_imports)]
16 use {Intrinsic, Type}
;
17 use IntrinsicDef
::Named
;
19 // The default inlining settings trigger a pathological behaviour in
20 // LLVM, which causes makes compilation very slow. See #28273.
22 pub fn find(name
: &str) -> Option
<Intrinsic
> {
23 if !name
.starts_with("aarch64_v") { return None }
24 Some(match &name
["aarch64_v".len()..] {
25 "hadd_s8" => Intrinsic
{
26 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
28 definition
: Named("llvm.aarch64.neon.shadd.v8i8")
30 "hadd_u8" => Intrinsic
{
31 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
33 definition
: Named("llvm.aarch64.neon.uhadd.v8i8")
35 "hadd_s16" => Intrinsic
{
36 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
38 definition
: Named("llvm.aarch64.neon.shadd.v4i16")
40 "hadd_u16" => Intrinsic
{
41 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
43 definition
: Named("llvm.aarch64.neon.uhadd.v4i16")
45 "hadd_s32" => Intrinsic
{
46 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
48 definition
: Named("llvm.aarch64.neon.shadd.v2i32")
50 "hadd_u32" => Intrinsic
{
51 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
53 definition
: Named("llvm.aarch64.neon.uhadd.v2i32")
55 "haddq_s8" => Intrinsic
{
56 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
58 definition
: Named("llvm.aarch64.neon.shadd.v16i8")
60 "haddq_u8" => Intrinsic
{
61 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
63 definition
: Named("llvm.aarch64.neon.uhadd.v16i8")
65 "haddq_s16" => Intrinsic
{
66 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
68 definition
: Named("llvm.aarch64.neon.shadd.v8i16")
70 "haddq_u16" => Intrinsic
{
71 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
73 definition
: Named("llvm.aarch64.neon.uhadd.v8i16")
75 "haddq_s32" => Intrinsic
{
76 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
78 definition
: Named("llvm.aarch64.neon.shadd.v4i32")
80 "haddq_u32" => Intrinsic
{
81 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
83 definition
: Named("llvm.aarch64.neon.uhadd.v4i32")
85 "rhadd_s8" => Intrinsic
{
86 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
88 definition
: Named("llvm.aarch64.neon.srhadd.v8i8")
90 "rhadd_u8" => Intrinsic
{
91 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
93 definition
: Named("llvm.aarch64.neon.urhadd.v8i8")
95 "rhadd_s16" => Intrinsic
{
96 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
98 definition
: Named("llvm.aarch64.neon.srhadd.v4i16")
100 "rhadd_u16" => Intrinsic
{
101 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
103 definition
: Named("llvm.aarch64.neon.urhadd.v4i16")
105 "rhadd_s32" => Intrinsic
{
106 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
108 definition
: Named("llvm.aarch64.neon.srhadd.v2i32")
110 "rhadd_u32" => Intrinsic
{
111 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
113 definition
: Named("llvm.aarch64.neon.urhadd.v2i32")
115 "rhaddq_s8" => Intrinsic
{
116 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
118 definition
: Named("llvm.aarch64.neon.srhadd.v16i8")
120 "rhaddq_u8" => Intrinsic
{
121 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
123 definition
: Named("llvm.aarch64.neon.urhadd.v16i8")
125 "rhaddq_s16" => Intrinsic
{
126 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
128 definition
: Named("llvm.aarch64.neon.srhadd.v8i16")
130 "rhaddq_u16" => Intrinsic
{
131 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
133 definition
: Named("llvm.aarch64.neon.urhadd.v8i16")
135 "rhaddq_s32" => Intrinsic
{
136 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
138 definition
: Named("llvm.aarch64.neon.srhadd.v4i32")
140 "rhaddq_u32" => Intrinsic
{
141 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
143 definition
: Named("llvm.aarch64.neon.urhadd.v4i32")
145 "qadd_s8" => Intrinsic
{
146 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
148 definition
: Named("llvm.aarch64.neon.sqadd.v8i8")
150 "qadd_u8" => Intrinsic
{
151 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
153 definition
: Named("llvm.aarch64.neon.uqadd.v8i8")
155 "qadd_s16" => Intrinsic
{
156 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
158 definition
: Named("llvm.aarch64.neon.sqadd.v4i16")
160 "qadd_u16" => Intrinsic
{
161 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
163 definition
: Named("llvm.aarch64.neon.uqadd.v4i16")
165 "qadd_s32" => Intrinsic
{
166 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
168 definition
: Named("llvm.aarch64.neon.sqadd.v2i32")
170 "qadd_u32" => Intrinsic
{
171 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
173 definition
: Named("llvm.aarch64.neon.uqadd.v2i32")
175 "qadd_s64" => Intrinsic
{
176 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }
,
178 definition
: Named("llvm.aarch64.neon.sqadd.v1i64")
180 "qadd_u64" => Intrinsic
{
181 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS }
,
183 definition
: Named("llvm.aarch64.neon.uqadd.v1i64")
185 "qaddq_s8" => Intrinsic
{
186 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
188 definition
: Named("llvm.aarch64.neon.sqadd.v16i8")
190 "qaddq_u8" => Intrinsic
{
191 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
193 definition
: Named("llvm.aarch64.neon.uqadd.v16i8")
195 "qaddq_s16" => Intrinsic
{
196 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
198 definition
: Named("llvm.aarch64.neon.sqadd.v8i16")
200 "qaddq_u16" => Intrinsic
{
201 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
203 definition
: Named("llvm.aarch64.neon.uqadd.v8i16")
205 "qaddq_s32" => Intrinsic
{
206 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
208 definition
: Named("llvm.aarch64.neon.sqadd.v4i32")
210 "qaddq_u32" => Intrinsic
{
211 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
213 definition
: Named("llvm.aarch64.neon.uqadd.v4i32")
215 "qaddq_s64" => Intrinsic
{
216 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
218 definition
: Named("llvm.aarch64.neon.sqadd.v2i64")
220 "qaddq_u64" => Intrinsic
{
221 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }
,
223 definition
: Named("llvm.aarch64.neon.uqadd.v2i64")
225 "uqadd_s8" => Intrinsic
{
226 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::U8x16]; &INPUTS }
,
228 definition
: Named("llvm.aarch64.neon.suqadd.v16i8")
230 "uqadd_s16" => Intrinsic
{
231 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U16x8]; &INPUTS }
,
233 definition
: Named("llvm.aarch64.neon.suqadd.v8i16")
235 "uqadd_s32" => Intrinsic
{
236 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32x4]; &INPUTS }
,
238 definition
: Named("llvm.aarch64.neon.suqadd.v4i32")
240 "uqadd_s64" => Intrinsic
{
241 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U64x2]; &INPUTS }
,
243 definition
: Named("llvm.aarch64.neon.suqadd.v2i64")
245 "sqadd_u8" => Intrinsic
{
246 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }
,
248 definition
: Named("llvm.aarch64.neon.usqadd.v16i8")
250 "sqadd_u16" => Intrinsic
{
251 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }
,
253 definition
: Named("llvm.aarch64.neon.usqadd.v8i16")
255 "sqadd_u32" => Intrinsic
{
256 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }
,
258 definition
: Named("llvm.aarch64.neon.usqadd.v4i32")
260 "sqadd_u64" => Intrinsic
{
261 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }
,
263 definition
: Named("llvm.aarch64.neon.usqadd.v2i64")
265 "raddhn_s16" => Intrinsic
{
266 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
268 definition
: Named("llvm.aarch64.neon.raddhn.v8i8")
270 "raddhn_u16" => Intrinsic
{
271 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
273 definition
: Named("llvm.aarch64.neon.raddhn.v8i8")
275 "raddhn_s32" => Intrinsic
{
276 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
278 definition
: Named("llvm.aarch64.neon.raddhn.v4i16")
280 "raddhn_u32" => Intrinsic
{
281 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
283 definition
: Named("llvm.aarch64.neon.raddhn.v4i16")
285 "raddhn_s64" => Intrinsic
{
286 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
288 definition
: Named("llvm.aarch64.neon.raddhn.v2i32")
290 "raddhn_u64" => Intrinsic
{
291 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }
,
293 definition
: Named("llvm.aarch64.neon.raddhn.v2i32")
295 "fmulx_f32" => Intrinsic
{
296 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
298 definition
: Named("llvm.aarch64.neon.fmulx.v2f32")
300 "fmulx_f64" => Intrinsic
{
301 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS }
,
303 definition
: Named("llvm.aarch64.neon.fmulx.v1f64")
305 "fmulxq_f32" => Intrinsic
{
306 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
308 definition
: Named("llvm.aarch64.neon.fmulx.v4f32")
310 "fmulxq_f64" => Intrinsic
{
311 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }
,
313 definition
: Named("llvm.aarch64.neon.fmulx.v2f64")
315 "fma_f32" => Intrinsic
{
316 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
318 definition
: Named("llvm.fma.v2f32")
320 "fma_f64" => Intrinsic
{
321 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS }
,
323 definition
: Named("llvm.fma.v1f64")
325 "fmaq_f32" => Intrinsic
{
326 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
328 definition
: Named("llvm.fma.v4f32")
330 "fmaq_f64" => Intrinsic
{
331 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }
,
333 definition
: Named("llvm.fma.v2f64")
335 "qdmulh_s16" => Intrinsic
{
336 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
338 definition
: Named("llvm.aarch64.neon.sqdmulh.v4i16")
340 "qdmulh_s32" => Intrinsic
{
341 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
343 definition
: Named("llvm.aarch64.neon.sqdmulh.v2i32")
345 "qdmulhq_s16" => Intrinsic
{
346 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
348 definition
: Named("llvm.aarch64.neon.sqdmulh.v8i16")
350 "qdmulhq_s32" => Intrinsic
{
351 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
353 definition
: Named("llvm.aarch64.neon.sqdmulh.v4i32")
355 "qrdmulh_s16" => Intrinsic
{
356 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
358 definition
: Named("llvm.aarch64.neon.sqrdmulh.v4i16")
360 "qrdmulh_s32" => Intrinsic
{
361 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
363 definition
: Named("llvm.aarch64.neon.sqrdmulh.v2i32")
365 "qrdmulhq_s16" => Intrinsic
{
366 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
368 definition
: Named("llvm.aarch64.neon.sqrdmulh.v8i16")
370 "qrdmulhq_s32" => Intrinsic
{
371 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
373 definition
: Named("llvm.aarch64.neon.sqrdmulh.v4i32")
375 "mull_s8" => Intrinsic
{
376 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
378 definition
: Named("llvm.aarch64.neon.smull.v8i16")
380 "mull_u8" => Intrinsic
{
381 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
383 definition
: Named("llvm.aarch64.neon.umull.v8i16")
385 "mull_s16" => Intrinsic
{
386 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
388 definition
: Named("llvm.aarch64.neon.smull.v4i32")
390 "mull_u16" => Intrinsic
{
391 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
393 definition
: Named("llvm.aarch64.neon.umull.v4i32")
395 "mull_s32" => Intrinsic
{
396 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
398 definition
: Named("llvm.aarch64.neon.smull.v2i64")
400 "mull_u32" => Intrinsic
{
401 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
403 definition
: Named("llvm.aarch64.neon.umull.v2i64")
405 "qdmullq_s8" => Intrinsic
{
406 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
408 definition
: Named("llvm.aarch64.neon.sqdmull.v8i16")
410 "qdmullq_s16" => Intrinsic
{
411 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
413 definition
: Named("llvm.aarch64.neon.sqdmull.v4i32")
415 "hsub_s8" => Intrinsic
{
416 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
418 definition
: Named("llvm.aarch64.neon.shsub.v8i8")
420 "hsub_u8" => Intrinsic
{
421 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
423 definition
: Named("llvm.aarch64.neon.uhsub.v8i8")
425 "hsub_s16" => Intrinsic
{
426 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
428 definition
: Named("llvm.aarch64.neon.shsub.v4i16")
430 "hsub_u16" => Intrinsic
{
431 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
433 definition
: Named("llvm.aarch64.neon.uhsub.v4i16")
435 "hsub_s32" => Intrinsic
{
436 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
438 definition
: Named("llvm.aarch64.neon.shsub.v2i32")
440 "hsub_u32" => Intrinsic
{
441 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
443 definition
: Named("llvm.aarch64.neon.uhsub.v2i32")
445 "hsubq_s8" => Intrinsic
{
446 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
448 definition
: Named("llvm.aarch64.neon.shsub.v16i8")
450 "hsubq_u8" => Intrinsic
{
451 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
453 definition
: Named("llvm.aarch64.neon.uhsub.v16i8")
455 "hsubq_s16" => Intrinsic
{
456 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
458 definition
: Named("llvm.aarch64.neon.shsub.v8i16")
460 "hsubq_u16" => Intrinsic
{
461 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
463 definition
: Named("llvm.aarch64.neon.uhsub.v8i16")
465 "hsubq_s32" => Intrinsic
{
466 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
468 definition
: Named("llvm.aarch64.neon.shsub.v4i32")
470 "hsubq_u32" => Intrinsic
{
471 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
473 definition
: Named("llvm.aarch64.neon.uhsub.v4i32")
475 "qsub_s8" => Intrinsic
{
476 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
478 definition
: Named("llvm.aarch64.neon.sqsub.v8i8")
480 "qsub_u8" => Intrinsic
{
481 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
483 definition
: Named("llvm.aarch64.neon.uqsub.v8i8")
485 "qsub_s16" => Intrinsic
{
486 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
488 definition
: Named("llvm.aarch64.neon.sqsub.v4i16")
490 "qsub_u16" => Intrinsic
{
491 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
493 definition
: Named("llvm.aarch64.neon.uqsub.v4i16")
495 "qsub_s32" => Intrinsic
{
496 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
498 definition
: Named("llvm.aarch64.neon.sqsub.v2i32")
500 "qsub_u32" => Intrinsic
{
501 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
503 definition
: Named("llvm.aarch64.neon.uqsub.v2i32")
505 "qsub_s64" => Intrinsic
{
506 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }
,
508 definition
: Named("llvm.aarch64.neon.sqsub.v1i64")
510 "qsub_u64" => Intrinsic
{
511 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS }
,
513 definition
: Named("llvm.aarch64.neon.uqsub.v1i64")
515 "qsubq_s8" => Intrinsic
{
516 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
518 definition
: Named("llvm.aarch64.neon.sqsub.v16i8")
520 "qsubq_u8" => Intrinsic
{
521 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
523 definition
: Named("llvm.aarch64.neon.uqsub.v16i8")
525 "qsubq_s16" => Intrinsic
{
526 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
528 definition
: Named("llvm.aarch64.neon.sqsub.v8i16")
530 "qsubq_u16" => Intrinsic
{
531 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
533 definition
: Named("llvm.aarch64.neon.uqsub.v8i16")
535 "qsubq_s32" => Intrinsic
{
536 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
538 definition
: Named("llvm.aarch64.neon.sqsub.v4i32")
540 "qsubq_u32" => Intrinsic
{
541 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
543 definition
: Named("llvm.aarch64.neon.uqsub.v4i32")
545 "qsubq_s64" => Intrinsic
{
546 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
548 definition
: Named("llvm.aarch64.neon.sqsub.v2i64")
550 "qsubq_u64" => Intrinsic
{
551 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }
,
553 definition
: Named("llvm.aarch64.neon.uqsub.v2i64")
555 "rsubhn_s16" => Intrinsic
{
556 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
558 definition
: Named("llvm.aarch64.neon.rsubhn.v8i8")
560 "rsubhn_u16" => Intrinsic
{
561 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
563 definition
: Named("llvm.aarch64.neon.rsubhn.v8i8")
565 "rsubhn_s32" => Intrinsic
{
566 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
568 definition
: Named("llvm.aarch64.neon.rsubhn.v4i16")
570 "rsubhn_u32" => Intrinsic
{
571 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
573 definition
: Named("llvm.aarch64.neon.rsubhn.v4i16")
575 "rsubhn_s64" => Intrinsic
{
576 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
578 definition
: Named("llvm.aarch64.neon.rsubhn.v2i32")
580 "rsubhn_u64" => Intrinsic
{
581 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }
,
583 definition
: Named("llvm.aarch64.neon.rsubhn.v2i32")
585 "abd_s8" => Intrinsic
{
586 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
588 definition
: Named("llvm.aarch64.neon.sabd.v8i8")
590 "abd_u8" => Intrinsic
{
591 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
593 definition
: Named("llvm.aarch64.neon.uabd.v8i8")
595 "abd_s16" => Intrinsic
{
596 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
598 definition
: Named("llvm.aarch64.neon.sabd.v4i16")
600 "abd_u16" => Intrinsic
{
601 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
603 definition
: Named("llvm.aarch64.neon.uabd.v4i16")
605 "abd_s32" => Intrinsic
{
606 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
608 definition
: Named("llvm.aarch64.neon.sabd.v2i32")
610 "abd_u32" => Intrinsic
{
611 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
613 definition
: Named("llvm.aarch64.neon.uabd.v2i32")
615 "abd_f32" => Intrinsic
{
616 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
618 definition
: Named("llvm.aarch64.neon.fabd.v2f32")
620 "abd_f64" => Intrinsic
{
621 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS }
,
623 definition
: Named("llvm.aarch64.neon.fabd.v1f64")
625 "abdq_s8" => Intrinsic
{
626 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
628 definition
: Named("llvm.aarch64.neon.sabd.v16i8")
630 "abdq_u8" => Intrinsic
{
631 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
633 definition
: Named("llvm.aarch64.neon.uabd.v16i8")
635 "abdq_s16" => Intrinsic
{
636 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
638 definition
: Named("llvm.aarch64.neon.sabd.v8i16")
640 "abdq_u16" => Intrinsic
{
641 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
643 definition
: Named("llvm.aarch64.neon.uabd.v8i16")
645 "abdq_s32" => Intrinsic
{
646 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
648 definition
: Named("llvm.aarch64.neon.sabd.v4i32")
650 "abdq_u32" => Intrinsic
{
651 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
653 definition
: Named("llvm.aarch64.neon.uabd.v4i32")
655 "abdq_f32" => Intrinsic
{
656 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
658 definition
: Named("llvm.aarch64.neon.fabd.v4f32")
660 "abdq_f64" => Intrinsic
{
661 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }
,
663 definition
: Named("llvm.aarch64.neon.fabd.v2f64")
665 "max_s8" => Intrinsic
{
666 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
668 definition
: Named("llvm.aarch64.neon.smax.v8i8")
670 "max_u8" => Intrinsic
{
671 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
673 definition
: Named("llvm.aarch64.neon.umax.v8i8")
675 "max_s16" => Intrinsic
{
676 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
678 definition
: Named("llvm.aarch64.neon.smax.v4i16")
680 "max_u16" => Intrinsic
{
681 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
683 definition
: Named("llvm.aarch64.neon.umax.v4i16")
685 "max_s32" => Intrinsic
{
686 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
688 definition
: Named("llvm.aarch64.neon.smax.v2i32")
690 "max_u32" => Intrinsic
{
691 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
693 definition
: Named("llvm.aarch64.neon.umax.v2i32")
695 "max_f32" => Intrinsic
{
696 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
698 definition
: Named("llvm.aarch64.neon.fmax.v2f32")
700 "max_f64" => Intrinsic
{
701 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS }
,
703 definition
: Named("llvm.aarch64.neon.fmax.v1f64")
705 "maxq_s8" => Intrinsic
{
706 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
708 definition
: Named("llvm.aarch64.neon.smax.v16i8")
710 "maxq_u8" => Intrinsic
{
711 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
713 definition
: Named("llvm.aarch64.neon.umax.v16i8")
715 "maxq_s16" => Intrinsic
{
716 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
718 definition
: Named("llvm.aarch64.neon.smax.v8i16")
720 "maxq_u16" => Intrinsic
{
721 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
723 definition
: Named("llvm.aarch64.neon.umax.v8i16")
725 "maxq_s32" => Intrinsic
{
726 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
728 definition
: Named("llvm.aarch64.neon.smax.v4i32")
730 "maxq_u32" => Intrinsic
{
731 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
733 definition
: Named("llvm.aarch64.neon.umax.v4i32")
735 "maxq_f32" => Intrinsic
{
736 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
738 definition
: Named("llvm.aarch64.neon.fmax.v4f32")
740 "maxq_f64" => Intrinsic
{
741 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }
,
743 definition
: Named("llvm.aarch64.neon.fmax.v2f64")
745 "min_s8" => Intrinsic
{
746 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
748 definition
: Named("llvm.aarch64.neon.smin.v8i8")
750 "min_u8" => Intrinsic
{
751 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
753 definition
: Named("llvm.aarch64.neon.umin.v8i8")
755 "min_s16" => Intrinsic
{
756 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
758 definition
: Named("llvm.aarch64.neon.smin.v4i16")
760 "min_u16" => Intrinsic
{
761 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
763 definition
: Named("llvm.aarch64.neon.umin.v4i16")
765 "min_s32" => Intrinsic
{
766 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
768 definition
: Named("llvm.aarch64.neon.smin.v2i32")
770 "min_u32" => Intrinsic
{
771 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
773 definition
: Named("llvm.aarch64.neon.umin.v2i32")
775 "min_f32" => Intrinsic
{
776 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
778 definition
: Named("llvm.aarch64.neon.fmin.v2f32")
780 "min_f64" => Intrinsic
{
781 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS }
,
783 definition
: Named("llvm.aarch64.neon.fmin.v1f64")
785 "minq_s8" => Intrinsic
{
786 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
788 definition
: Named("llvm.aarch64.neon.smin.v16i8")
790 "minq_u8" => Intrinsic
{
791 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
793 definition
: Named("llvm.aarch64.neon.umin.v16i8")
795 "minq_s16" => Intrinsic
{
796 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
798 definition
: Named("llvm.aarch64.neon.smin.v8i16")
800 "minq_u16" => Intrinsic
{
801 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
803 definition
: Named("llvm.aarch64.neon.umin.v8i16")
805 "minq_s32" => Intrinsic
{
806 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
808 definition
: Named("llvm.aarch64.neon.smin.v4i32")
810 "minq_u32" => Intrinsic
{
811 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
813 definition
: Named("llvm.aarch64.neon.umin.v4i32")
815 "minq_f32" => Intrinsic
{
816 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
818 definition
: Named("llvm.aarch64.neon.fmin.v4f32")
820 "minq_f64" => Intrinsic
{
821 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }
,
823 definition
: Named("llvm.aarch64.neon.fmin.v2f64")
825 "maxnm_f32" => Intrinsic
{
826 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
828 definition
: Named("llvm.aarch64.neon.fmaxnm.v2f32")
830 "maxnm_f64" => Intrinsic
{
831 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS }
,
833 definition
: Named("llvm.aarch64.neon.fmaxnm.v1f64")
835 "maxnmq_f32" => Intrinsic
{
836 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
838 definition
: Named("llvm.aarch64.neon.fmaxnm.v4f32")
840 "maxnmq_f64" => Intrinsic
{
841 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }
,
843 definition
: Named("llvm.aarch64.neon.fmaxnm.v2f64")
845 "minnm_f32" => Intrinsic
{
846 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
848 definition
: Named("llvm.aarch64.neon.fminnm.v2f32")
850 "minnm_f64" => Intrinsic
{
851 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS }
,
853 definition
: Named("llvm.aarch64.neon.fminnm.v1f64")
855 "minnmq_f32" => Intrinsic
{
856 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
858 definition
: Named("llvm.aarch64.neon.fminnm.v4f32")
860 "minnmq_f64" => Intrinsic
{
861 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }
,
863 definition
: Named("llvm.aarch64.neon.fminnm.v2f64")
865 "shl_s8" => Intrinsic
{
866 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
868 definition
: Named("llvm.aarch64.neon.sshl.v8i8")
870 "shl_u8" => Intrinsic
{
871 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS }
,
873 definition
: Named("llvm.aarch64.neon.ushl.v8i8")
875 "shl_s16" => Intrinsic
{
876 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
878 definition
: Named("llvm.aarch64.neon.sshl.v4i16")
880 "shl_u16" => Intrinsic
{
881 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS }
,
883 definition
: Named("llvm.aarch64.neon.ushl.v4i16")
885 "shl_s32" => Intrinsic
{
886 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
888 definition
: Named("llvm.aarch64.neon.sshl.v2i32")
890 "shl_u32" => Intrinsic
{
891 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS }
,
893 definition
: Named("llvm.aarch64.neon.ushl.v2i32")
895 "shl_s64" => Intrinsic
{
896 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }
,
898 definition
: Named("llvm.aarch64.neon.sshl.v1i64")
900 "shl_u64" => Intrinsic
{
901 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS }
,
903 definition
: Named("llvm.aarch64.neon.ushl.v1i64")
905 "shlq_s8" => Intrinsic
{
906 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
908 definition
: Named("llvm.aarch64.neon.sshl.v16i8")
910 "shlq_u8" => Intrinsic
{
911 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }
,
913 definition
: Named("llvm.aarch64.neon.ushl.v16i8")
915 "shlq_s16" => Intrinsic
{
916 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
918 definition
: Named("llvm.aarch64.neon.sshl.v8i16")
920 "shlq_u16" => Intrinsic
{
921 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }
,
923 definition
: Named("llvm.aarch64.neon.ushl.v8i16")
925 "shlq_s32" => Intrinsic
{
926 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
928 definition
: Named("llvm.aarch64.neon.sshl.v4i32")
930 "shlq_u32" => Intrinsic
{
931 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }
,
933 definition
: Named("llvm.aarch64.neon.ushl.v4i32")
935 "shlq_s64" => Intrinsic
{
936 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
938 definition
: Named("llvm.aarch64.neon.sshl.v2i64")
940 "shlq_u64" => Intrinsic
{
941 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }
,
943 definition
: Named("llvm.aarch64.neon.ushl.v2i64")
945 "qshl_s8" => Intrinsic
{
946 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
948 definition
: Named("llvm.aarch64.neon.sqshl.v8i8")
950 "qshl_u8" => Intrinsic
{
951 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS }
,
953 definition
: Named("llvm.aarch64.neon.uqshl.v8i8")
955 "qshl_s16" => Intrinsic
{
956 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
958 definition
: Named("llvm.aarch64.neon.sqshl.v4i16")
960 "qshl_u16" => Intrinsic
{
961 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS }
,
963 definition
: Named("llvm.aarch64.neon.uqshl.v4i16")
965 "qshl_s32" => Intrinsic
{
966 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
968 definition
: Named("llvm.aarch64.neon.sqshl.v2i32")
970 "qshl_u32" => Intrinsic
{
971 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS }
,
973 definition
: Named("llvm.aarch64.neon.uqshl.v2i32")
975 "qshl_s64" => Intrinsic
{
976 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }
,
978 definition
: Named("llvm.aarch64.neon.sqshl.v1i64")
980 "qshl_u64" => Intrinsic
{
981 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS }
,
983 definition
: Named("llvm.aarch64.neon.uqshl.v1i64")
985 "qshlq_s8" => Intrinsic
{
986 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
988 definition
: Named("llvm.aarch64.neon.sqshl.v16i8")
990 "qshlq_u8" => Intrinsic
{
991 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }
,
993 definition
: Named("llvm.aarch64.neon.uqshl.v16i8")
995 "qshlq_s16" => Intrinsic
{
996 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
998 definition
: Named("llvm.aarch64.neon.sqshl.v8i16")
1000 "qshlq_u16" => Intrinsic
{
1001 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }
,
1003 definition
: Named("llvm.aarch64.neon.uqshl.v8i16")
1005 "qshlq_s32" => Intrinsic
{
1006 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
1008 definition
: Named("llvm.aarch64.neon.sqshl.v4i32")
1010 "qshlq_u32" => Intrinsic
{
1011 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }
,
1013 definition
: Named("llvm.aarch64.neon.uqshl.v4i32")
1015 "qshlq_s64" => Intrinsic
{
1016 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
1018 definition
: Named("llvm.aarch64.neon.sqshl.v2i64")
1020 "qshlq_u64" => Intrinsic
{
1021 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }
,
1023 definition
: Named("llvm.aarch64.neon.uqshl.v2i64")
1025 "rshl_s8" => Intrinsic
{
1026 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
1028 definition
: Named("llvm.aarch64.neon.srshl.v8i8")
1030 "rshl_u8" => Intrinsic
{
1031 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS }
,
1033 definition
: Named("llvm.aarch64.neon.urshl.v8i8")
1035 "rshl_s16" => Intrinsic
{
1036 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
1038 definition
: Named("llvm.aarch64.neon.srshl.v4i16")
1040 "rshl_u16" => Intrinsic
{
1041 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS }
,
1043 definition
: Named("llvm.aarch64.neon.urshl.v4i16")
1045 "rshl_s32" => Intrinsic
{
1046 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
1048 definition
: Named("llvm.aarch64.neon.srshl.v2i32")
1050 "rshl_u32" => Intrinsic
{
1051 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS }
,
1053 definition
: Named("llvm.aarch64.neon.urshl.v2i32")
1055 "rshl_s64" => Intrinsic
{
1056 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }
,
1058 definition
: Named("llvm.aarch64.neon.srshl.v1i64")
1060 "rshl_u64" => Intrinsic
{
1061 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS }
,
1063 definition
: Named("llvm.aarch64.neon.urshl.v1i64")
1065 "rshlq_s8" => Intrinsic
{
1066 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
1068 definition
: Named("llvm.aarch64.neon.srshl.v16i8")
1070 "rshlq_u8" => Intrinsic
{
1071 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }
,
1073 definition
: Named("llvm.aarch64.neon.urshl.v16i8")
1075 "rshlq_s16" => Intrinsic
{
1076 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
1078 definition
: Named("llvm.aarch64.neon.srshl.v8i16")
1080 "rshlq_u16" => Intrinsic
{
1081 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }
,
1083 definition
: Named("llvm.aarch64.neon.urshl.v8i16")
1085 "rshlq_s32" => Intrinsic
{
1086 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
1088 definition
: Named("llvm.aarch64.neon.srshl.v4i32")
1090 "rshlq_u32" => Intrinsic
{
1091 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }
,
1093 definition
: Named("llvm.aarch64.neon.urshl.v4i32")
1095 "rshlq_s64" => Intrinsic
{
1096 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
1098 definition
: Named("llvm.aarch64.neon.srshl.v2i64")
1100 "rshlq_u64" => Intrinsic
{
1101 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }
,
1103 definition
: Named("llvm.aarch64.neon.urshl.v2i64")
1105 "qrshl_s8" => Intrinsic
{
1106 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
1108 definition
: Named("llvm.aarch64.neon.sqrshl.v8i8")
1110 "qrshl_u8" => Intrinsic
{
1111 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS }
,
1113 definition
: Named("llvm.aarch64.neon.uqrshl.v8i8")
1115 "qrshl_s16" => Intrinsic
{
1116 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
1118 definition
: Named("llvm.aarch64.neon.sqrshl.v4i16")
1120 "qrshl_u16" => Intrinsic
{
1121 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS }
,
1123 definition
: Named("llvm.aarch64.neon.uqrshl.v4i16")
1125 "qrshl_s32" => Intrinsic
{
1126 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
1128 definition
: Named("llvm.aarch64.neon.sqrshl.v2i32")
1130 "qrshl_u32" => Intrinsic
{
1131 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS }
,
1133 definition
: Named("llvm.aarch64.neon.uqrshl.v2i32")
1135 "qrshl_s64" => Intrinsic
{
1136 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }
,
1138 definition
: Named("llvm.aarch64.neon.sqrshl.v1i64")
1140 "qrshl_u64" => Intrinsic
{
1141 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS }
,
1143 definition
: Named("llvm.aarch64.neon.uqrshl.v1i64")
1145 "qrshlq_s8" => Intrinsic
{
1146 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
1148 definition
: Named("llvm.aarch64.neon.sqrshl.v16i8")
1150 "qrshlq_u8" => Intrinsic
{
1151 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }
,
1153 definition
: Named("llvm.aarch64.neon.uqrshl.v16i8")
1155 "qrshlq_s16" => Intrinsic
{
1156 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
1158 definition
: Named("llvm.aarch64.neon.sqrshl.v8i16")
1160 "qrshlq_u16" => Intrinsic
{
1161 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }
,
1163 definition
: Named("llvm.aarch64.neon.uqrshl.v8i16")
1165 "qrshlq_s32" => Intrinsic
{
1166 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
1168 definition
: Named("llvm.aarch64.neon.sqrshl.v4i32")
1170 "qrshlq_u32" => Intrinsic
{
1171 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }
,
1173 definition
: Named("llvm.aarch64.neon.uqrshl.v4i32")
1175 "qrshlq_s64" => Intrinsic
{
1176 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
1178 definition
: Named("llvm.aarch64.neon.sqrshl.v2i64")
1180 "qrshlq_u64" => Intrinsic
{
1181 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }
,
1183 definition
: Named("llvm.aarch64.neon.uqrshl.v2i64")
1185 "qshrun_n_s16" => Intrinsic
{
1186 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }
,
1188 definition
: Named("llvm.aarch64.neon.sqshrun.v8i8")
1190 "qshrun_n_s32" => Intrinsic
{
1191 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }
,
1193 definition
: Named("llvm.aarch64.neon.sqshrun.v4i16")
1195 "qshrun_n_s64" => Intrinsic
{
1196 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }
,
1198 definition
: Named("llvm.aarch64.neon.sqshrun.v2i32")
1200 "qrshrun_n_s16" => Intrinsic
{
1201 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }
,
1203 definition
: Named("llvm.aarch64.neon.sqrshrun.v8i8")
1205 "qrshrun_n_s32" => Intrinsic
{
1206 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }
,
1208 definition
: Named("llvm.aarch64.neon.sqrshrun.v4i16")
1210 "qrshrun_n_s64" => Intrinsic
{
1211 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }
,
1213 definition
: Named("llvm.aarch64.neon.sqrshrun.v2i32")
1215 "qshrn_n_s16" => Intrinsic
{
1216 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }
,
1218 definition
: Named("llvm.aarch64.neon.sqshrn.v8i8")
1220 "qshrn_n_u16" => Intrinsic
{
1221 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS }
,
1223 definition
: Named("llvm.aarch64.neon.uqshrn.v8i8")
1225 "qshrn_n_s32" => Intrinsic
{
1226 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }
,
1228 definition
: Named("llvm.aarch64.neon.sqshrn.v4i16")
1230 "qshrn_n_u32" => Intrinsic
{
1231 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS }
,
1233 definition
: Named("llvm.aarch64.neon.uqshrn.v4i16")
1235 "qshrn_n_s64" => Intrinsic
{
1236 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }
,
1238 definition
: Named("llvm.aarch64.neon.sqshrn.v2i32")
1240 "qshrn_n_u64" => Intrinsic
{
1241 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS }
,
1243 definition
: Named("llvm.aarch64.neon.uqshrn.v2i32")
1245 "rshrn_n_s16" => Intrinsic
{
1246 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }
,
1248 definition
: Named("llvm.aarch64.neon.rshrn.v8i8")
1250 "rshrn_n_u16" => Intrinsic
{
1251 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS }
,
1253 definition
: Named("llvm.aarch64.neon.rshrn.v8i8")
1255 "rshrn_n_s32" => Intrinsic
{
1256 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }
,
1258 definition
: Named("llvm.aarch64.neon.rshrn.v4i16")
1260 "rshrn_n_u32" => Intrinsic
{
1261 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS }
,
1263 definition
: Named("llvm.aarch64.neon.rshrn.v4i16")
1265 "rshrn_n_s64" => Intrinsic
{
1266 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }
,
1268 definition
: Named("llvm.aarch64.neon.rshrn.v2i32")
1270 "rshrn_n_u64" => Intrinsic
{
1271 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS }
,
1273 definition
: Named("llvm.aarch64.neon.rshrn.v2i32")
1275 "qrshrn_n_s16" => Intrinsic
{
1276 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }
,
1278 definition
: Named("llvm.aarch64.neon.sqrshrn.v8i8")
1280 "qrshrn_n_u16" => Intrinsic
{
1281 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS }
,
1283 definition
: Named("llvm.aarch64.neon.uqrshrn.v8i8")
1285 "qrshrn_n_s32" => Intrinsic
{
1286 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }
,
1288 definition
: Named("llvm.aarch64.neon.sqrshrn.v4i16")
1290 "qrshrn_n_u32" => Intrinsic
{
1291 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS }
,
1293 definition
: Named("llvm.aarch64.neon.uqrshrn.v4i16")
1295 "qrshrn_n_s64" => Intrinsic
{
1296 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }
,
1298 definition
: Named("llvm.aarch64.neon.sqrshrn.v2i32")
1300 "qrshrn_n_u64" => Intrinsic
{
1301 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS }
,
1303 definition
: Named("llvm.aarch64.neon.uqrshrn.v2i32")
1305 "sri_s8" => Intrinsic
{
1306 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
1308 definition
: Named("llvm.aarch64.neon.vsri.v8i8")
1310 "sri_u8" => Intrinsic
{
1311 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
1313 definition
: Named("llvm.aarch64.neon.vsri.v8i8")
1315 "sri_s16" => Intrinsic
{
1316 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
1318 definition
: Named("llvm.aarch64.neon.vsri.v4i16")
1320 "sri_u16" => Intrinsic
{
1321 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
1323 definition
: Named("llvm.aarch64.neon.vsri.v4i16")
1325 "sri_s32" => Intrinsic
{
1326 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
1328 definition
: Named("llvm.aarch64.neon.vsri.v2i32")
1330 "sri_u32" => Intrinsic
{
1331 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
1333 definition
: Named("llvm.aarch64.neon.vsri.v2i32")
1335 "sri_s64" => Intrinsic
{
1336 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }
,
1338 definition
: Named("llvm.aarch64.neon.vsri.v1i64")
1340 "sri_u64" => Intrinsic
{
1341 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS }
,
1343 definition
: Named("llvm.aarch64.neon.vsri.v1i64")
1345 "sriq_s8" => Intrinsic
{
1346 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
1348 definition
: Named("llvm.aarch64.neon.vsri.v16i8")
1350 "sriq_u8" => Intrinsic
{
1351 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
1353 definition
: Named("llvm.aarch64.neon.vsri.v16i8")
1355 "sriq_s16" => Intrinsic
{
1356 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
1358 definition
: Named("llvm.aarch64.neon.vsri.v8i16")
1360 "sriq_u16" => Intrinsic
{
1361 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
1363 definition
: Named("llvm.aarch64.neon.vsri.v8i16")
1365 "sriq_s32" => Intrinsic
{
1366 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
1368 definition
: Named("llvm.aarch64.neon.vsri.v4i32")
1370 "sriq_u32" => Intrinsic
{
1371 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
1373 definition
: Named("llvm.aarch64.neon.vsri.v4i32")
1375 "sriq_s64" => Intrinsic
{
1376 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
1378 definition
: Named("llvm.aarch64.neon.vsri.v2i64")
1380 "sriq_u64" => Intrinsic
{
1381 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }
,
1383 definition
: Named("llvm.aarch64.neon.vsri.v2i64")
1385 "sli_s8" => Intrinsic
{
1386 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
1388 definition
: Named("llvm.aarch64.neon.vsli.v8i8")
1390 "sli_u8" => Intrinsic
{
1391 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
1393 definition
: Named("llvm.aarch64.neon.vsli.v8i8")
1395 "sli_s16" => Intrinsic
{
1396 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
1398 definition
: Named("llvm.aarch64.neon.vsli.v4i16")
1400 "sli_u16" => Intrinsic
{
1401 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
1403 definition
: Named("llvm.aarch64.neon.vsli.v4i16")
1405 "sli_s32" => Intrinsic
{
1406 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
1408 definition
: Named("llvm.aarch64.neon.vsli.v2i32")
1410 "sli_u32" => Intrinsic
{
1411 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
1413 definition
: Named("llvm.aarch64.neon.vsli.v2i32")
1415 "sli_s64" => Intrinsic
{
1416 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }
,
1418 definition
: Named("llvm.aarch64.neon.vsli.v1i64")
1420 "sli_u64" => Intrinsic
{
1421 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS }
,
1423 definition
: Named("llvm.aarch64.neon.vsli.v1i64")
1425 "sliq_s8" => Intrinsic
{
1426 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
1428 definition
: Named("llvm.aarch64.neon.vsli.v16i8")
1430 "sliq_u8" => Intrinsic
{
1431 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
1433 definition
: Named("llvm.aarch64.neon.vsli.v16i8")
1435 "sliq_s16" => Intrinsic
{
1436 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
1438 definition
: Named("llvm.aarch64.neon.vsli.v8i16")
1440 "sliq_u16" => Intrinsic
{
1441 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
1443 definition
: Named("llvm.aarch64.neon.vsli.v8i16")
1445 "sliq_s32" => Intrinsic
{
1446 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
1448 definition
: Named("llvm.aarch64.neon.vsli.v4i32")
1450 "sliq_u32" => Intrinsic
{
1451 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
1453 definition
: Named("llvm.aarch64.neon.vsli.v4i32")
1455 "sliq_s64" => Intrinsic
{
1456 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
1458 definition
: Named("llvm.aarch64.neon.vsli.v2i64")
1460 "sliq_u64" => Intrinsic
{
1461 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }
,
1463 definition
: Named("llvm.aarch64.neon.vsli.v2i64")
1465 "vqmovn_s16" => Intrinsic
{
1466 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }
,
1468 definition
: Named("llvm.aarch64.neon.sqxtn.v8i8")
1470 "vqmovn_u16" => Intrinsic
{
1471 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }
,
1473 definition
: Named("llvm.aarch64.neon.uqxtn.v8i8")
1475 "vqmovn_s32" => Intrinsic
{
1476 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }
,
1478 definition
: Named("llvm.aarch64.neon.sqxtn.v4i16")
1480 "vqmovn_u32" => Intrinsic
{
1481 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }
,
1483 definition
: Named("llvm.aarch64.neon.uqxtn.v4i16")
1485 "vqmovn_s64" => Intrinsic
{
1486 inputs
: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS }
,
1488 definition
: Named("llvm.aarch64.neon.sqxtn.v2i32")
1490 "vqmovn_u64" => Intrinsic
{
1491 inputs
: { static INPUTS: [&'static Type; 1] = [&::U64x2]; &INPUTS }
,
1493 definition
: Named("llvm.aarch64.neon.uqxtn.v2i32")
1495 "abs_s8" => Intrinsic
{
1496 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }
,
1498 definition
: Named("llvm.aarch64.neon.abs.v8i8")
1500 "abs_s16" => Intrinsic
{
1501 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }
,
1503 definition
: Named("llvm.aarch64.neon.abs.v4i16")
1505 "abs_s32" => Intrinsic
{
1506 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }
,
1508 definition
: Named("llvm.aarch64.neon.abs.v2i32")
1510 "abs_s64" => Intrinsic
{
1511 inputs
: { static INPUTS: [&'static Type; 1] = [&::I64x1]; &INPUTS }
,
1513 definition
: Named("llvm.aarch64.neon.abs.v1i64")
1515 "absq_s8" => Intrinsic
{
1516 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }
,
1518 definition
: Named("llvm.aarch64.neon.abs.v16i8")
1520 "absq_s16" => Intrinsic
{
1521 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }
,
1523 definition
: Named("llvm.aarch64.neon.abs.v8i16")
1525 "absq_s32" => Intrinsic
{
1526 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }
,
1528 definition
: Named("llvm.aarch64.neon.abs.v4i32")
1530 "absq_s64" => Intrinsic
{
1531 inputs
: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS }
,
1533 definition
: Named("llvm.aarch64.neon.abs.v2i64")
1535 "abs_f32" => Intrinsic
{
1536 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }
,
1538 definition
: Named("llvm.fabs.v2f32")
1540 "abs_f64" => Intrinsic
{
1541 inputs
: { static INPUTS: [&'static Type; 1] = [&::F64x1]; &INPUTS }
,
1543 definition
: Named("llvm.fabs.v1f64")
1545 "absq_f32" => Intrinsic
{
1546 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }
,
1548 definition
: Named("llvm.fabs.v4f32")
1550 "absq_f64" => Intrinsic
{
1551 inputs
: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }
,
1553 definition
: Named("llvm.fabs.v2f64")
1555 "qabs_s8" => Intrinsic
{
1556 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }
,
1558 definition
: Named("llvm.aarch64.neon.sqabs.v8i8")
1560 "qabs_s16" => Intrinsic
{
1561 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }
,
1563 definition
: Named("llvm.aarch64.neon.sqabs.v4i16")
1565 "qabs_s32" => Intrinsic
{
1566 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }
,
1568 definition
: Named("llvm.aarch64.neon.sqabs.v2i32")
1570 "qabs_s64" => Intrinsic
{
1571 inputs
: { static INPUTS: [&'static Type; 1] = [&::I64x1]; &INPUTS }
,
1573 definition
: Named("llvm.aarch64.neon.sqabs.v1i64")
1575 "qabsq_s8" => Intrinsic
{
1576 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }
,
1578 definition
: Named("llvm.aarch64.neon.sqabs.v16i8")
1580 "qabsq_s16" => Intrinsic
{
1581 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }
,
1583 definition
: Named("llvm.aarch64.neon.sqabs.v8i16")
1585 "qabsq_s32" => Intrinsic
{
1586 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }
,
1588 definition
: Named("llvm.aarch64.neon.sqabs.v4i32")
1590 "qabsq_s64" => Intrinsic
{
1591 inputs
: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS }
,
1593 definition
: Named("llvm.aarch64.neon.sqabs.v2i64")
1595 "qneg_s8" => Intrinsic
{
1596 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }
,
1598 definition
: Named("llvm.aarch64.neon.sqneg.v8i8")
1600 "qneg_s16" => Intrinsic
{
1601 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }
,
1603 definition
: Named("llvm.aarch64.neon.sqneg.v4i16")
1605 "qneg_s32" => Intrinsic
{
1606 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }
,
1608 definition
: Named("llvm.aarch64.neon.sqneg.v2i32")
1610 "qneg_s64" => Intrinsic
{
1611 inputs
: { static INPUTS: [&'static Type; 1] = [&::I64x1]; &INPUTS }
,
1613 definition
: Named("llvm.aarch64.neon.sqneg.v1i64")
1615 "qnegq_s8" => Intrinsic
{
1616 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }
,
1618 definition
: Named("llvm.aarch64.neon.sqneg.v16i8")
1620 "qnegq_s16" => Intrinsic
{
1621 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }
,
1623 definition
: Named("llvm.aarch64.neon.sqneg.v8i16")
1625 "qnegq_s32" => Intrinsic
{
1626 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }
,
1628 definition
: Named("llvm.aarch64.neon.sqneg.v4i32")
1630 "qnegq_s64" => Intrinsic
{
1631 inputs
: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS }
,
1633 definition
: Named("llvm.aarch64.neon.sqneg.v2i64")
1635 "clz_s8" => Intrinsic
{
1636 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }
,
1638 definition
: Named("llvm.ctlz.v8i8")
1640 "clz_u8" => Intrinsic
{
1641 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }
,
1643 definition
: Named("llvm.ctlz.v8i8")
1645 "clz_s16" => Intrinsic
{
1646 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }
,
1648 definition
: Named("llvm.ctlz.v4i16")
1650 "clz_u16" => Intrinsic
{
1651 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }
,
1653 definition
: Named("llvm.ctlz.v4i16")
1655 "clz_s32" => Intrinsic
{
1656 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }
,
1658 definition
: Named("llvm.ctlz.v2i32")
1660 "clz_u32" => Intrinsic
{
1661 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }
,
1663 definition
: Named("llvm.ctlz.v2i32")
1665 "clzq_s8" => Intrinsic
{
1666 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }
,
1668 definition
: Named("llvm.ctlz.v16i8")
1670 "clzq_u8" => Intrinsic
{
1671 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }
,
1673 definition
: Named("llvm.ctlz.v16i8")
1675 "clzq_s16" => Intrinsic
{
1676 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }
,
1678 definition
: Named("llvm.ctlz.v8i16")
1680 "clzq_u16" => Intrinsic
{
1681 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }
,
1683 definition
: Named("llvm.ctlz.v8i16")
1685 "clzq_s32" => Intrinsic
{
1686 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }
,
1688 definition
: Named("llvm.ctlz.v4i32")
1690 "clzq_u32" => Intrinsic
{
1691 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }
,
1693 definition
: Named("llvm.ctlz.v4i32")
1695 "cls_s8" => Intrinsic
{
1696 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }
,
1698 definition
: Named("llvm.aarch64.neon.cls.v8i8")
1700 "cls_u8" => Intrinsic
{
1701 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }
,
1703 definition
: Named("llvm.aarch64.neon.cls.v8i8")
1705 "cls_s16" => Intrinsic
{
1706 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }
,
1708 definition
: Named("llvm.aarch64.neon.cls.v4i16")
1710 "cls_u16" => Intrinsic
{
1711 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }
,
1713 definition
: Named("llvm.aarch64.neon.cls.v4i16")
1715 "cls_s32" => Intrinsic
{
1716 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }
,
1718 definition
: Named("llvm.aarch64.neon.cls.v2i32")
1720 "cls_u32" => Intrinsic
{
1721 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }
,
1723 definition
: Named("llvm.aarch64.neon.cls.v2i32")
1725 "clsq_s8" => Intrinsic
{
1726 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }
,
1728 definition
: Named("llvm.aarch64.neon.cls.v16i8")
1730 "clsq_u8" => Intrinsic
{
1731 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }
,
1733 definition
: Named("llvm.aarch64.neon.cls.v16i8")
1735 "clsq_s16" => Intrinsic
{
1736 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }
,
1738 definition
: Named("llvm.aarch64.neon.cls.v8i16")
1740 "clsq_u16" => Intrinsic
{
1741 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }
,
1743 definition
: Named("llvm.aarch64.neon.cls.v8i16")
1745 "clsq_s32" => Intrinsic
{
1746 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }
,
1748 definition
: Named("llvm.aarch64.neon.cls.v4i32")
1750 "clsq_u32" => Intrinsic
{
1751 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }
,
1753 definition
: Named("llvm.aarch64.neon.cls.v4i32")
1755 "cnt_s8" => Intrinsic
{
1756 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }
,
1758 definition
: Named("llvm.ctpop.v8i8")
1760 "cnt_u8" => Intrinsic
{
1761 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }
,
1763 definition
: Named("llvm.ctpop.v8i8")
1765 "cntq_s8" => Intrinsic
{
1766 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }
,
1768 definition
: Named("llvm.ctpop.v16i8")
1770 "cntq_u8" => Intrinsic
{
1771 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }
,
1773 definition
: Named("llvm.ctpop.v16i8")
1775 "recpe_u32" => Intrinsic
{
1776 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }
,
1778 definition
: Named("llvm.aarch64.neon.urecpe.v2i32")
1780 "recpe_f32" => Intrinsic
{
1781 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }
,
1783 definition
: Named("llvm.aarch64.neon.frecpe.v2f32")
1785 "recpe_f64" => Intrinsic
{
1786 inputs
: { static INPUTS: [&'static Type; 1] = [&::F64x1]; &INPUTS }
,
1788 definition
: Named("llvm.aarch64.neon.frecpe.v1f64")
1790 "recpeq_u32" => Intrinsic
{
1791 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }
,
1793 definition
: Named("llvm.aarch64.neon.urecpe.v4i32")
1795 "recpeq_f32" => Intrinsic
{
1796 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }
,
1798 definition
: Named("llvm.aarch64.neon.frecpe.v4f32")
1800 "recpeq_f64" => Intrinsic
{
1801 inputs
: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }
,
1803 definition
: Named("llvm.aarch64.neon.frecpe.v2f64")
1805 "recps_f32" => Intrinsic
{
1806 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
1808 definition
: Named("llvm.aarch64.neon.frecps.v2f32")
1810 "recps_f64" => Intrinsic
{
1811 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS }
,
1813 definition
: Named("llvm.aarch64.neon.frecps.v1f64")
1815 "recpsq_f32" => Intrinsic
{
1816 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
1818 definition
: Named("llvm.aarch64.neon.frecps.v4f32")
1820 "recpsq_f64" => Intrinsic
{
1821 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }
,
1823 definition
: Named("llvm.aarch64.neon.frecps.v2f64")
1825 "sqrt_f32" => Intrinsic
{
1826 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }
,
1828 definition
: Named("llvm.sqrt.v2f32")
1830 "sqrt_f64" => Intrinsic
{
1831 inputs
: { static INPUTS: [&'static Type; 1] = [&::F64x1]; &INPUTS }
,
1833 definition
: Named("llvm.sqrt.v1f64")
1835 "sqrtq_f32" => Intrinsic
{
1836 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }
,
1838 definition
: Named("llvm.sqrt.v4f32")
1840 "sqrtq_f64" => Intrinsic
{
1841 inputs
: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }
,
1843 definition
: Named("llvm.sqrt.v2f64")
1845 "rsqrte_u32" => Intrinsic
{
1846 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }
,
1848 definition
: Named("llvm.aarch64.neon.ursqrte.v2i32")
1850 "rsqrte_f32" => Intrinsic
{
1851 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }
,
1853 definition
: Named("llvm.aarch64.neon.frsqrte.v2f32")
1855 "rsqrte_f64" => Intrinsic
{
1856 inputs
: { static INPUTS: [&'static Type; 1] = [&::F64x1]; &INPUTS }
,
1858 definition
: Named("llvm.aarch64.neon.frsqrte.v1f64")
1860 "rsqrteq_u32" => Intrinsic
{
1861 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }
,
1863 definition
: Named("llvm.aarch64.neon.ursqrte.v4i32")
1865 "rsqrteq_f32" => Intrinsic
{
1866 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }
,
1868 definition
: Named("llvm.aarch64.neon.frsqrte.v4f32")
1870 "rsqrteq_f64" => Intrinsic
{
1871 inputs
: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }
,
1873 definition
: Named("llvm.aarch64.neon.frsqrte.v2f64")
1875 "rsqrts_f32" => Intrinsic
{
1876 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
1878 definition
: Named("llvm.aarch64.neon.frsqrts.v2f32")
1880 "rsqrts_f64" => Intrinsic
{
1881 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS }
,
1883 definition
: Named("llvm.aarch64.neon.frsqrts.v1f64")
1885 "rsqrtsq_f32" => Intrinsic
{
1886 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
1888 definition
: Named("llvm.aarch64.neon.frsqrts.v4f32")
1890 "rsqrtsq_f64" => Intrinsic
{
1891 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }
,
1893 definition
: Named("llvm.aarch64.neon.frsqrts.v2f64")
1895 "rbit_s8" => Intrinsic
{
1896 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }
,
1898 definition
: Named("llvm.aarch64.neon.rbit.v8i8")
1900 "rbit_u8" => Intrinsic
{
1901 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }
,
1903 definition
: Named("llvm.aarch64.neon.rbit.v8i8")
1905 "rbitq_s8" => Intrinsic
{
1906 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }
,
1908 definition
: Named("llvm.aarch64.neon.rbit.v16i8")
1910 "rbitq_u8" => Intrinsic
{
1911 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }
,
1913 definition
: Named("llvm.aarch64.neon.rbit.v16i8")
1915 "ld2_s8" => Intrinsic
{
1916 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x8), true); &PTR }
]; &INPUTS
},
1917 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &PARTS }
); &AGG
},
1918 definition
: Named("llvm.aarch64.neon.ld2.v8i8.p0v8i8")
1920 "ld2_u8" => Intrinsic
{
1921 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x8), true); &PTR }
]; &INPUTS
},
1922 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &PARTS }
); &AGG
},
1923 definition
: Named("llvm.aarch64.neon.ld2.v8i8.p0v8i8")
1925 "ld2_s16" => Intrinsic
{
1926 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x4), true); &PTR }
]; &INPUTS
},
1927 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &PARTS }
); &AGG
},
1928 definition
: Named("llvm.aarch64.neon.ld2.v4i16.p0v4i16")
1930 "ld2_u16" => Intrinsic
{
1931 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x4), true); &PTR }
]; &INPUTS
},
1932 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &PARTS }
); &AGG
},
1933 definition
: Named("llvm.aarch64.neon.ld2.v4i16.p0v4i16")
1935 "ld2_s32" => Intrinsic
{
1936 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x2), true); &PTR }
]; &INPUTS
},
1937 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &PARTS }
); &AGG
},
1938 definition
: Named("llvm.aarch64.neon.ld2.v2i32.p0v2i32")
1940 "ld2_u32" => Intrinsic
{
1941 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x2), true); &PTR }
]; &INPUTS
},
1942 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &PARTS }
); &AGG
},
1943 definition
: Named("llvm.aarch64.neon.ld2.v2i32.p0v2i32")
1945 "ld2_s64" => Intrinsic
{
1946 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x1), true); &PTR }
]; &INPUTS
},
1947 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &PARTS }
); &AGG
},
1948 definition
: Named("llvm.aarch64.neon.ld2.v1i64.p0v1i64")
1950 "ld2_u64" => Intrinsic
{
1951 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x1), true); &PTR }
]; &INPUTS
},
1952 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &PARTS }
); &AGG
},
1953 definition
: Named("llvm.aarch64.neon.ld2.v1i64.p0v1i64")
1955 "ld2_f32" => Intrinsic
{
1956 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x2), true); &PTR }
]; &INPUTS
},
1957 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &PARTS }
); &AGG
},
1958 definition
: Named("llvm.aarch64.neon.ld2.v2f32.p0v2f32")
1960 "ld2_f64" => Intrinsic
{
1961 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x1), true); &PTR }
]; &INPUTS
},
1962 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &PARTS }
); &AGG
},
1963 definition
: Named("llvm.aarch64.neon.ld2.v1f64.p0v1f64")
1965 "ld2q_s8" => Intrinsic
{
1966 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x16), true); &PTR }
]; &INPUTS
},
1967 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }
); &AGG
},
1968 definition
: Named("llvm.aarch64.neon.ld2.v16i8.p0v16i8")
1970 "ld2q_u8" => Intrinsic
{
1971 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x16), true); &PTR }
]; &INPUTS
},
1972 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }
); &AGG
},
1973 definition
: Named("llvm.aarch64.neon.ld2.v16i8.p0v16i8")
1975 "ld2q_s16" => Intrinsic
{
1976 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x8), true); &PTR }
]; &INPUTS
},
1977 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &PARTS }
); &AGG
},
1978 definition
: Named("llvm.aarch64.neon.ld2.v8i16.p0v8i16")
1980 "ld2q_u16" => Intrinsic
{
1981 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x8), true); &PTR }
]; &INPUTS
},
1982 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &PARTS }
); &AGG
},
1983 definition
: Named("llvm.aarch64.neon.ld2.v8i16.p0v8i16")
1985 "ld2q_s32" => Intrinsic
{
1986 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x4), true); &PTR }
]; &INPUTS
},
1987 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &PARTS }
); &AGG
},
1988 definition
: Named("llvm.aarch64.neon.ld2.v4i32.p0v4i32")
1990 "ld2q_u32" => Intrinsic
{
1991 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x4), true); &PTR }
]; &INPUTS
},
1992 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &PARTS }
); &AGG
},
1993 definition
: Named("llvm.aarch64.neon.ld2.v4i32.p0v4i32")
1995 "ld2q_s64" => Intrinsic
{
1996 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x2), true); &PTR }
]; &INPUTS
},
1997 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &PARTS }
); &AGG
},
1998 definition
: Named("llvm.aarch64.neon.ld2.v2i64.p0v2i64")
2000 "ld2q_u64" => Intrinsic
{
2001 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x2), true); &PTR }
]; &INPUTS
},
2002 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &PARTS }
); &AGG
},
2003 definition
: Named("llvm.aarch64.neon.ld2.v2i64.p0v2i64")
2005 "ld2q_f32" => Intrinsic
{
2006 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x4), true); &PTR }
]; &INPUTS
},
2007 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &PARTS }
); &AGG
},
2008 definition
: Named("llvm.aarch64.neon.ld2.v4f32.p0v4f32")
2010 "ld2q_f64" => Intrinsic
{
2011 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x2), true); &PTR }
]; &INPUTS
},
2012 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &PARTS }
); &AGG
},
2013 definition
: Named("llvm.aarch64.neon.ld2.v2f64.p0v2f64")
2015 "ld3_s8" => Intrinsic
{
2016 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x8), true); &PTR }
]; &INPUTS
},
2017 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::I8x8]; &PARTS }
); &AGG
},
2018 definition
: Named("llvm.aarch64.neon.ld3.v8i8.p0v8i8")
2020 "ld3_u8" => Intrinsic
{
2021 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x8), true); &PTR }
]; &INPUTS
},
2022 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &PARTS }
); &AGG
},
2023 definition
: Named("llvm.aarch64.neon.ld3.v8i8.p0v8i8")
2025 "ld3_s16" => Intrinsic
{
2026 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x4), true); &PTR }
]; &INPUTS
},
2027 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I16x4, &::I16x4, &::I16x4]; &PARTS }
); &AGG
},
2028 definition
: Named("llvm.aarch64.neon.ld3.v4i16.p0v4i16")
2030 "ld3_u16" => Intrinsic
{
2031 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x4), true); &PTR }
]; &INPUTS
},
2032 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U16x4, &::U16x4, &::U16x4]; &PARTS }
); &AGG
},
2033 definition
: Named("llvm.aarch64.neon.ld3.v4i16.p0v4i16")
2035 "ld3_s32" => Intrinsic
{
2036 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x2), true); &PTR }
]; &INPUTS
},
2037 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I32x2, &::I32x2, &::I32x2]; &PARTS }
); &AGG
},
2038 definition
: Named("llvm.aarch64.neon.ld3.v2i32.p0v2i32")
2040 "ld3_u32" => Intrinsic
{
2041 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x2), true); &PTR }
]; &INPUTS
},
2042 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U32x2, &::U32x2, &::U32x2]; &PARTS }
); &AGG
},
2043 definition
: Named("llvm.aarch64.neon.ld3.v2i32.p0v2i32")
2045 "ld3_s64" => Intrinsic
{
2046 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x1), true); &PTR }
]; &INPUTS
},
2047 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I64x1, &::I64x1, &::I64x1]; &PARTS }
); &AGG
},
2048 definition
: Named("llvm.aarch64.neon.ld3.v1i64.p0v1i64")
2050 "ld3_u64" => Intrinsic
{
2051 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x1), true); &PTR }
]; &INPUTS
},
2052 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U64x1, &::U64x1, &::U64x1]; &PARTS }
); &AGG
},
2053 definition
: Named("llvm.aarch64.neon.ld3.v1i64.p0v1i64")
2055 "ld3_f32" => Intrinsic
{
2056 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x2), true); &PTR }
]; &INPUTS
},
2057 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F32x2, &::F32x2, &::F32x2]; &PARTS }
); &AGG
},
2058 definition
: Named("llvm.aarch64.neon.ld3.v2f32.p0v2f32")
2060 "ld3_f64" => Intrinsic
{
2061 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x1), true); &PTR }
]; &INPUTS
},
2062 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F64x1, &::F64x1, &::F64x1]; &PARTS }
); &AGG
},
2063 definition
: Named("llvm.aarch64.neon.ld3.v1f64.p0v1f64")
2065 "ld3q_s8" => Intrinsic
{
2066 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x16), true); &PTR }
]; &INPUTS
},
2067 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }
); &AGG
},
2068 definition
: Named("llvm.aarch64.neon.ld3.v16i8.p0v16i8")
2070 "ld3q_u8" => Intrinsic
{
2071 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x16), true); &PTR }
]; &INPUTS
},
2072 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }
); &AGG
},
2073 definition
: Named("llvm.aarch64.neon.ld3.v16i8.p0v16i8")
2075 "ld3q_s16" => Intrinsic
{
2076 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x8), true); &PTR }
]; &INPUTS
},
2077 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I16x8, &::I16x8, &::I16x8]; &PARTS }
); &AGG
},
2078 definition
: Named("llvm.aarch64.neon.ld3.v8i16.p0v8i16")
2080 "ld3q_u16" => Intrinsic
{
2081 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x8), true); &PTR }
]; &INPUTS
},
2082 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U16x8, &::U16x8, &::U16x8]; &PARTS }
); &AGG
},
2083 definition
: Named("llvm.aarch64.neon.ld3.v8i16.p0v8i16")
2085 "ld3q_s32" => Intrinsic
{
2086 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x4), true); &PTR }
]; &INPUTS
},
2087 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I32x4, &::I32x4, &::I32x4]; &PARTS }
); &AGG
},
2088 definition
: Named("llvm.aarch64.neon.ld3.v4i32.p0v4i32")
2090 "ld3q_u32" => Intrinsic
{
2091 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x4), true); &PTR }
]; &INPUTS
},
2092 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U32x4, &::U32x4, &::U32x4]; &PARTS }
); &AGG
},
2093 definition
: Named("llvm.aarch64.neon.ld3.v4i32.p0v4i32")
2095 "ld3q_s64" => Intrinsic
{
2096 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x2), true); &PTR }
]; &INPUTS
},
2097 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I64x2, &::I64x2, &::I64x2]; &PARTS }
); &AGG
},
2098 definition
: Named("llvm.aarch64.neon.ld3.v2i64.p0v2i64")
2100 "ld3q_u64" => Intrinsic
{
2101 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x2), true); &PTR }
]; &INPUTS
},
2102 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U64x2, &::U64x2, &::U64x2]; &PARTS }
); &AGG
},
2103 definition
: Named("llvm.aarch64.neon.ld3.v2i64.p0v2i64")
2105 "ld3q_f32" => Intrinsic
{
2106 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x4), true); &PTR }
]; &INPUTS
},
2107 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &PARTS }
); &AGG
},
2108 definition
: Named("llvm.aarch64.neon.ld3.v4f32.p0v4f32")
2110 "ld3q_f64" => Intrinsic
{
2111 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x2), true); &PTR }
]; &INPUTS
},
2112 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F64x2, &::F64x2, &::F64x2]; &PARTS }
); &AGG
},
2113 definition
: Named("llvm.aarch64.neon.ld3.v2f64.p0v2f64")
2115 "ld4_s8" => Intrinsic
{
2116 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x8), true); &PTR }
]; &INPUTS
},
2117 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I8x8, &::I8x8, &::I8x8, &::I8x8]; &PARTS }
); &AGG
},
2118 definition
: Named("llvm.aarch64.neon.ld4.v8i8.p0v8i8")
2120 "ld4_u8" => Intrinsic
{
2121 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x8), true); &PTR }
]; &INPUTS
},
2122 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U8x8, &::U8x8, &::U8x8, &::U8x8]; &PARTS }
); &AGG
},
2123 definition
: Named("llvm.aarch64.neon.ld4.v8i8.p0v8i8")
2125 "ld4_s16" => Intrinsic
{
2126 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x4), true); &PTR }
]; &INPUTS
},
2127 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I16x4, &::I16x4, &::I16x4, &::I16x4]; &PARTS }
); &AGG
},
2128 definition
: Named("llvm.aarch64.neon.ld4.v4i16.p0v4i16")
2130 "ld4_u16" => Intrinsic
{
2131 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x4), true); &PTR }
]; &INPUTS
},
2132 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U16x4, &::U16x4, &::U16x4, &::U16x4]; &PARTS }
); &AGG
},
2133 definition
: Named("llvm.aarch64.neon.ld4.v4i16.p0v4i16")
2135 "ld4_s32" => Intrinsic
{
2136 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x2), true); &PTR }
]; &INPUTS
},
2137 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I32x2, &::I32x2, &::I32x2, &::I32x2]; &PARTS }
); &AGG
},
2138 definition
: Named("llvm.aarch64.neon.ld4.v2i32.p0v2i32")
2140 "ld4_u32" => Intrinsic
{
2141 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x2), true); &PTR }
]; &INPUTS
},
2142 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U32x2, &::U32x2, &::U32x2, &::U32x2]; &PARTS }
); &AGG
},
2143 definition
: Named("llvm.aarch64.neon.ld4.v2i32.p0v2i32")
2145 "ld4_s64" => Intrinsic
{
2146 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x1), true); &PTR }
]; &INPUTS
},
2147 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I64x1, &::I64x1, &::I64x1, &::I64x1]; &PARTS }
); &AGG
},
2148 definition
: Named("llvm.aarch64.neon.ld4.v1i64.p0v1i64")
2150 "ld4_u64" => Intrinsic
{
2151 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x1), true); &PTR }
]; &INPUTS
},
2152 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U64x1, &::U64x1, &::U64x1, &::U64x1]; &PARTS }
); &AGG
},
2153 definition
: Named("llvm.aarch64.neon.ld4.v1i64.p0v1i64")
2155 "ld4_f32" => Intrinsic
{
2156 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x2), true); &PTR }
]; &INPUTS
},
2157 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F32x2, &::F32x2, &::F32x2, &::F32x2]; &PARTS }
); &AGG
},
2158 definition
: Named("llvm.aarch64.neon.ld4.v2f32.p0v2f32")
2160 "ld4_f64" => Intrinsic
{
2161 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x1), true); &PTR }
]; &INPUTS
},
2162 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F64x1, &::F64x1, &::F64x1, &::F64x1]; &PARTS }
); &AGG
},
2163 definition
: Named("llvm.aarch64.neon.ld4.v1f64.p0v1f64")
2165 "ld4q_s8" => Intrinsic
{
2166 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x16), true); &PTR }
]; &INPUTS
},
2167 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }
); &AGG
},
2168 definition
: Named("llvm.aarch64.neon.ld4.v16i8.p0v16i8")
2170 "ld4q_u8" => Intrinsic
{
2171 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x16), true); &PTR }
]; &INPUTS
},
2172 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }
); &AGG
},
2173 definition
: Named("llvm.aarch64.neon.ld4.v16i8.p0v16i8")
2175 "ld4q_s16" => Intrinsic
{
2176 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x8), true); &PTR }
]; &INPUTS
},
2177 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I16x8, &::I16x8, &::I16x8, &::I16x8]; &PARTS }
); &AGG
},
2178 definition
: Named("llvm.aarch64.neon.ld4.v8i16.p0v8i16")
2180 "ld4q_u16" => Intrinsic
{
2181 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x8), true); &PTR }
]; &INPUTS
},
2182 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U16x8, &::U16x8, &::U16x8, &::U16x8]; &PARTS }
); &AGG
},
2183 definition
: Named("llvm.aarch64.neon.ld4.v8i16.p0v8i16")
2185 "ld4q_s32" => Intrinsic
{
2186 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x4), true); &PTR }
]; &INPUTS
},
2187 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I32x4, &::I32x4, &::I32x4, &::I32x4]; &PARTS }
); &AGG
},
2188 definition
: Named("llvm.aarch64.neon.ld4.v4i32.p0v4i32")
2190 "ld4q_u32" => Intrinsic
{
2191 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x4), true); &PTR }
]; &INPUTS
},
2192 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U32x4, &::U32x4, &::U32x4, &::U32x4]; &PARTS }
); &AGG
},
2193 definition
: Named("llvm.aarch64.neon.ld4.v4i32.p0v4i32")
2195 "ld4q_s64" => Intrinsic
{
2196 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x2), true); &PTR }
]; &INPUTS
},
2197 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I64x2, &::I64x2, &::I64x2, &::I64x2]; &PARTS }
); &AGG
},
2198 definition
: Named("llvm.aarch64.neon.ld4.v2i64.p0v2i64")
2200 "ld4q_u64" => Intrinsic
{
2201 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x2), true); &PTR }
]; &INPUTS
},
2202 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U64x2, &::U64x2, &::U64x2, &::U64x2]; &PARTS }
); &AGG
},
2203 definition
: Named("llvm.aarch64.neon.ld4.v2i64.p0v2i64")
2205 "ld4q_f32" => Intrinsic
{
2206 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x4), true); &PTR }
]; &INPUTS
},
2207 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F32x4, &::F32x4, &::F32x4, &::F32x4]; &PARTS }
); &AGG
},
2208 definition
: Named("llvm.aarch64.neon.ld4.v4f32.p0v4f32")
2210 "ld4q_f64" => Intrinsic
{
2211 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x2), true); &PTR }
]; &INPUTS
},
2212 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F64x2, &::F64x2, &::F64x2, &::F64x2]; &PARTS }
); &AGG
},
2213 definition
: Named("llvm.aarch64.neon.ld4.v2f64.p0v2f64")
2215 "ld2_dup_s8" => Intrinsic
{
2216 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }
]; &INPUTS
},
2217 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &PARTS }
); &AGG
},
2218 definition
: Named("llvm.aarch64.neon.ld2.v8i8.p0i8")
2220 "ld2_dup_u8" => Intrinsic
{
2221 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }
]; &INPUTS
},
2222 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &PARTS }
); &AGG
},
2223 definition
: Named("llvm.aarch64.neon.ld2.v8i8.p0i8")
2225 "ld2_dup_s16" => Intrinsic
{
2226 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }
]; &INPUTS
},
2227 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &PARTS }
); &AGG
},
2228 definition
: Named("llvm.aarch64.neon.ld2.v4i16.p0i16")
2230 "ld2_dup_u16" => Intrinsic
{
2231 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }
]; &INPUTS
},
2232 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &PARTS }
); &AGG
},
2233 definition
: Named("llvm.aarch64.neon.ld2.v4i16.p0i16")
2235 "ld2_dup_s32" => Intrinsic
{
2236 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }
]; &INPUTS
},
2237 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &PARTS }
); &AGG
},
2238 definition
: Named("llvm.aarch64.neon.ld2.v2i32.p0i32")
2240 "ld2_dup_u32" => Intrinsic
{
2241 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }
]; &INPUTS
},
2242 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &PARTS }
); &AGG
},
2243 definition
: Named("llvm.aarch64.neon.ld2.v2i32.p0i32")
2245 "ld2_dup_s64" => Intrinsic
{
2246 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }
]; &INPUTS
},
2247 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &PARTS }
); &AGG
},
2248 definition
: Named("llvm.aarch64.neon.ld2.v1i64.p0i64")
2250 "ld2_dup_u64" => Intrinsic
{
2251 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }
]; &INPUTS
},
2252 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &PARTS }
); &AGG
},
2253 definition
: Named("llvm.aarch64.neon.ld2.v1i64.p0i64")
2255 "ld2_dup_f32" => Intrinsic
{
2256 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }
]; &INPUTS
},
2257 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &PARTS }
); &AGG
},
2258 definition
: Named("llvm.aarch64.neon.ld2.v2f32.p0f32")
2260 "ld2_dup_f64" => Intrinsic
{
2261 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }
]; &INPUTS
},
2262 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &PARTS }
); &AGG
},
2263 definition
: Named("llvm.aarch64.neon.ld2.v1f64.p0f64")
2265 "ld2q_dup_s8" => Intrinsic
{
2266 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }
]; &INPUTS
},
2267 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }
); &AGG
},
2268 definition
: Named("llvm.aarch64.neon.ld2.v16i8.p0i8")
2270 "ld2q_dup_u8" => Intrinsic
{
2271 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }
]; &INPUTS
},
2272 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }
); &AGG
},
2273 definition
: Named("llvm.aarch64.neon.ld2.v16i8.p0i8")
2275 "ld2q_dup_s16" => Intrinsic
{
2276 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }
]; &INPUTS
},
2277 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &PARTS }
); &AGG
},
2278 definition
: Named("llvm.aarch64.neon.ld2.v8i16.p0i16")
2280 "ld2q_dup_u16" => Intrinsic
{
2281 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }
]; &INPUTS
},
2282 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &PARTS }
); &AGG
},
2283 definition
: Named("llvm.aarch64.neon.ld2.v8i16.p0i16")
2285 "ld2q_dup_s32" => Intrinsic
{
2286 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }
]; &INPUTS
},
2287 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &PARTS }
); &AGG
},
2288 definition
: Named("llvm.aarch64.neon.ld2.v4i32.p0i32")
2290 "ld2q_dup_u32" => Intrinsic
{
2291 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }
]; &INPUTS
},
2292 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &PARTS }
); &AGG
},
2293 definition
: Named("llvm.aarch64.neon.ld2.v4i32.p0i32")
2295 "ld2q_dup_s64" => Intrinsic
{
2296 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }
]; &INPUTS
},
2297 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &PARTS }
); &AGG
},
2298 definition
: Named("llvm.aarch64.neon.ld2.v2i64.p0i64")
2300 "ld2q_dup_u64" => Intrinsic
{
2301 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }
]; &INPUTS
},
2302 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &PARTS }
); &AGG
},
2303 definition
: Named("llvm.aarch64.neon.ld2.v2i64.p0i64")
2305 "ld2q_dup_f32" => Intrinsic
{
2306 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }
]; &INPUTS
},
2307 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &PARTS }
); &AGG
},
2308 definition
: Named("llvm.aarch64.neon.ld2.v4f32.p0f32")
2310 "ld2q_dup_f64" => Intrinsic
{
2311 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }
]; &INPUTS
},
2312 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &PARTS }
); &AGG
},
2313 definition
: Named("llvm.aarch64.neon.ld2.v2f64.p0f64")
2315 "ld3_dup_s8" => Intrinsic
{
2316 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }
]; &INPUTS
},
2317 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::I8x8]; &PARTS }
); &AGG
},
2318 definition
: Named("llvm.aarch64.neon.ld3.v8i8.p0i8")
2320 "ld3_dup_u8" => Intrinsic
{
2321 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }
]; &INPUTS
},
2322 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &PARTS }
); &AGG
},
2323 definition
: Named("llvm.aarch64.neon.ld3.v8i8.p0i8")
2325 "ld3_dup_s16" => Intrinsic
{
2326 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }
]; &INPUTS
},
2327 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I16x4, &::I16x4, &::I16x4]; &PARTS }
); &AGG
},
2328 definition
: Named("llvm.aarch64.neon.ld3.v4i16.p0i16")
2330 "ld3_dup_u16" => Intrinsic
{
2331 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }
]; &INPUTS
},
2332 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U16x4, &::U16x4, &::U16x4]; &PARTS }
); &AGG
},
2333 definition
: Named("llvm.aarch64.neon.ld3.v4i16.p0i16")
2335 "ld3_dup_s32" => Intrinsic
{
2336 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }
]; &INPUTS
},
2337 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I32x2, &::I32x2, &::I32x2]; &PARTS }
); &AGG
},
2338 definition
: Named("llvm.aarch64.neon.ld3.v2i32.p0i32")
2340 "ld3_dup_u32" => Intrinsic
{
2341 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }
]; &INPUTS
},
2342 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U32x2, &::U32x2, &::U32x2]; &PARTS }
); &AGG
},
2343 definition
: Named("llvm.aarch64.neon.ld3.v2i32.p0i32")
2345 "ld3_dup_s64" => Intrinsic
{
2346 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }
]; &INPUTS
},
2347 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I64x1, &::I64x1, &::I64x1]; &PARTS }
); &AGG
},
2348 definition
: Named("llvm.aarch64.neon.ld3.v1i64.p0i64")
2350 "ld3_dup_u64" => Intrinsic
{
2351 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }
]; &INPUTS
},
2352 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U64x1, &::U64x1, &::U64x1]; &PARTS }
); &AGG
},
2353 definition
: Named("llvm.aarch64.neon.ld3.v1i64.p0i64")
2355 "ld3_dup_f32" => Intrinsic
{
2356 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }
]; &INPUTS
},
2357 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F32x2, &::F32x2, &::F32x2]; &PARTS }
); &AGG
},
2358 definition
: Named("llvm.aarch64.neon.ld3.v2f32.p0f32")
2360 "ld3_dup_f64" => Intrinsic
{
2361 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }
]; &INPUTS
},
2362 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F64x1, &::F64x1, &::F64x1]; &PARTS }
); &AGG
},
2363 definition
: Named("llvm.aarch64.neon.ld3.v1f64.p0f64")
2365 "ld3q_dup_s8" => Intrinsic
{
2366 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }
]; &INPUTS
},
2367 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }
); &AGG
},
2368 definition
: Named("llvm.aarch64.neon.ld3.v16i8.p0i8")
2370 "ld3q_dup_u8" => Intrinsic
{
2371 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }
]; &INPUTS
},
2372 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }
); &AGG
},
2373 definition
: Named("llvm.aarch64.neon.ld3.v16i8.p0i8")
2375 "ld3q_dup_s16" => Intrinsic
{
2376 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }
]; &INPUTS
},
2377 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I16x8, &::I16x8, &::I16x8]; &PARTS }
); &AGG
},
2378 definition
: Named("llvm.aarch64.neon.ld3.v8i16.p0i16")
2380 "ld3q_dup_u16" => Intrinsic
{
2381 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }
]; &INPUTS
},
2382 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U16x8, &::U16x8, &::U16x8]; &PARTS }
); &AGG
},
2383 definition
: Named("llvm.aarch64.neon.ld3.v8i16.p0i16")
2385 "ld3q_dup_s32" => Intrinsic
{
2386 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }
]; &INPUTS
},
2387 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I32x4, &::I32x4, &::I32x4]; &PARTS }
); &AGG
},
2388 definition
: Named("llvm.aarch64.neon.ld3.v4i32.p0i32")
2390 "ld3q_dup_u32" => Intrinsic
{
2391 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }
]; &INPUTS
},
2392 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U32x4, &::U32x4, &::U32x4]; &PARTS }
); &AGG
},
2393 definition
: Named("llvm.aarch64.neon.ld3.v4i32.p0i32")
2395 "ld3q_dup_s64" => Intrinsic
{
2396 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }
]; &INPUTS
},
2397 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I64x2, &::I64x2, &::I64x2]; &PARTS }
); &AGG
},
2398 definition
: Named("llvm.aarch64.neon.ld3.v2i64.p0i64")
2400 "ld3q_dup_u64" => Intrinsic
{
2401 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }
]; &INPUTS
},
2402 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U64x2, &::U64x2, &::U64x2]; &PARTS }
); &AGG
},
2403 definition
: Named("llvm.aarch64.neon.ld3.v2i64.p0i64")
2405 "ld3q_dup_f32" => Intrinsic
{
2406 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }
]; &INPUTS
},
2407 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &PARTS }
); &AGG
},
2408 definition
: Named("llvm.aarch64.neon.ld3.v4f32.p0f32")
2410 "ld3q_dup_f64" => Intrinsic
{
2411 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }
]; &INPUTS
},
2412 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F64x2, &::F64x2, &::F64x2]; &PARTS }
); &AGG
},
2413 definition
: Named("llvm.aarch64.neon.ld3.v2f64.p0f64")
2415 "ld4_dup_s8" => Intrinsic
{
2416 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }
]; &INPUTS
},
2417 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I8x8, &::I8x8, &::I8x8, &::I8x8]; &PARTS }
); &AGG
},
2418 definition
: Named("llvm.aarch64.neon.ld4.v8i8.p0i8")
2420 "ld4_dup_u8" => Intrinsic
{
2421 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }
]; &INPUTS
},
2422 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U8x8, &::U8x8, &::U8x8, &::U8x8]; &PARTS }
); &AGG
},
2423 definition
: Named("llvm.aarch64.neon.ld4.v8i8.p0i8")
2425 "ld4_dup_s16" => Intrinsic
{
2426 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }
]; &INPUTS
},
2427 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I16x4, &::I16x4, &::I16x4, &::I16x4]; &PARTS }
); &AGG
},
2428 definition
: Named("llvm.aarch64.neon.ld4.v4i16.p0i16")
2430 "ld4_dup_u16" => Intrinsic
{
2431 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }
]; &INPUTS
},
2432 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U16x4, &::U16x4, &::U16x4, &::U16x4]; &PARTS }
); &AGG
},
2433 definition
: Named("llvm.aarch64.neon.ld4.v4i16.p0i16")
2435 "ld4_dup_s32" => Intrinsic
{
2436 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }
]; &INPUTS
},
2437 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I32x2, &::I32x2, &::I32x2, &::I32x2]; &PARTS }
); &AGG
},
2438 definition
: Named("llvm.aarch64.neon.ld4.v2i32.p0i32")
2440 "ld4_dup_u32" => Intrinsic
{
2441 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }
]; &INPUTS
},
2442 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U32x2, &::U32x2, &::U32x2, &::U32x2]; &PARTS }
); &AGG
},
2443 definition
: Named("llvm.aarch64.neon.ld4.v2i32.p0i32")
2445 "ld4_dup_s64" => Intrinsic
{
2446 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }
]; &INPUTS
},
2447 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I64x1, &::I64x1, &::I64x1, &::I64x1]; &PARTS }
); &AGG
},
2448 definition
: Named("llvm.aarch64.neon.ld4.v1i64.p0i64")
2450 "ld4_dup_u64" => Intrinsic
{
2451 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }
]; &INPUTS
},
2452 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U64x1, &::U64x1, &::U64x1, &::U64x1]; &PARTS }
); &AGG
},
2453 definition
: Named("llvm.aarch64.neon.ld4.v1i64.p0i64")
2455 "ld4_dup_f32" => Intrinsic
{
2456 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }
]; &INPUTS
},
2457 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F32x2, &::F32x2, &::F32x2, &::F32x2]; &PARTS }
); &AGG
},
2458 definition
: Named("llvm.aarch64.neon.ld4.v2f32.p0f32")
2460 "ld4_dup_f64" => Intrinsic
{
2461 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }
]; &INPUTS
},
2462 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F64x1, &::F64x1, &::F64x1, &::F64x1]; &PARTS }
); &AGG
},
2463 definition
: Named("llvm.aarch64.neon.ld4.v1f64.p0f64")
2465 "ld4q_dup_s8" => Intrinsic
{
2466 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }
]; &INPUTS
},
2467 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }
); &AGG
},
2468 definition
: Named("llvm.aarch64.neon.ld4.v16i8.p0i8")
2470 "ld4q_dup_u8" => Intrinsic
{
2471 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }
]; &INPUTS
},
2472 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }
); &AGG
},
2473 definition
: Named("llvm.aarch64.neon.ld4.v16i8.p0i8")
2475 "ld4q_dup_s16" => Intrinsic
{
2476 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }
]; &INPUTS
},
2477 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I16x8, &::I16x8, &::I16x8, &::I16x8]; &PARTS }
); &AGG
},
2478 definition
: Named("llvm.aarch64.neon.ld4.v8i16.p0i16")
2480 "ld4q_dup_u16" => Intrinsic
{
2481 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }
]; &INPUTS
},
2482 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U16x8, &::U16x8, &::U16x8, &::U16x8]; &PARTS }
); &AGG
},
2483 definition
: Named("llvm.aarch64.neon.ld4.v8i16.p0i16")
2485 "ld4q_dup_s32" => Intrinsic
{
2486 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }
]; &INPUTS
},
2487 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I32x4, &::I32x4, &::I32x4, &::I32x4]; &PARTS }
); &AGG
},
2488 definition
: Named("llvm.aarch64.neon.ld4.v4i32.p0i32")
2490 "ld4q_dup_u32" => Intrinsic
{
2491 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }
]; &INPUTS
},
2492 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U32x4, &::U32x4, &::U32x4, &::U32x4]; &PARTS }
); &AGG
},
2493 definition
: Named("llvm.aarch64.neon.ld4.v4i32.p0i32")
2495 "ld4q_dup_s64" => Intrinsic
{
2496 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }
]; &INPUTS
},
2497 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I64x2, &::I64x2, &::I64x2, &::I64x2]; &PARTS }
); &AGG
},
2498 definition
: Named("llvm.aarch64.neon.ld4.v2i64.p0i64")
2500 "ld4q_dup_u64" => Intrinsic
{
2501 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }
]; &INPUTS
},
2502 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U64x2, &::U64x2, &::U64x2, &::U64x2]; &PARTS }
); &AGG
},
2503 definition
: Named("llvm.aarch64.neon.ld4.v2i64.p0i64")
2505 "ld4q_dup_f32" => Intrinsic
{
2506 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }
]; &INPUTS
},
2507 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F32x4, &::F32x4, &::F32x4, &::F32x4]; &PARTS }
); &AGG
},
2508 definition
: Named("llvm.aarch64.neon.ld4.v4f32.p0f32")
2510 "ld4q_dup_f64" => Intrinsic
{
2511 inputs
: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }
]; &INPUTS
},
2512 output
: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F64x2, &::F64x2, &::F64x2, &::F64x2]; &PARTS }
); &AGG
},
2513 definition
: Named("llvm.aarch64.neon.ld4.v2f64.p0f64")
2515 "padd_s8" => Intrinsic
{
2516 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
2518 definition
: Named("llvm.aarch64.neon.addp.v8i8")
2520 "padd_u8" => Intrinsic
{
2521 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
2523 definition
: Named("llvm.aarch64.neon.addp.v8i8")
2525 "padd_s16" => Intrinsic
{
2526 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
2528 definition
: Named("llvm.aarch64.neon.addp.v4i16")
2530 "padd_u16" => Intrinsic
{
2531 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
2533 definition
: Named("llvm.aarch64.neon.addp.v4i16")
2535 "padd_s32" => Intrinsic
{
2536 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
2538 definition
: Named("llvm.aarch64.neon.addp.v2i32")
2540 "padd_u32" => Intrinsic
{
2541 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
2543 definition
: Named("llvm.aarch64.neon.addp.v2i32")
2545 "padd_f32" => Intrinsic
{
2546 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
2548 definition
: Named("llvm.aarch64.neon.addp.v2f32")
2550 "paddq_s8" => Intrinsic
{
2551 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
2553 definition
: Named("llvm.aarch64.neon.addp.v16i8")
2555 "paddq_u8" => Intrinsic
{
2556 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
2558 definition
: Named("llvm.aarch64.neon.addp.v16i8")
2560 "paddq_s16" => Intrinsic
{
2561 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
2563 definition
: Named("llvm.aarch64.neon.addp.v8i16")
2565 "paddq_u16" => Intrinsic
{
2566 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
2568 definition
: Named("llvm.aarch64.neon.addp.v8i16")
2570 "paddq_s32" => Intrinsic
{
2571 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
2573 definition
: Named("llvm.aarch64.neon.addp.v4i32")
2575 "paddq_u32" => Intrinsic
{
2576 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
2578 definition
: Named("llvm.aarch64.neon.addp.v4i32")
2580 "paddq_f32" => Intrinsic
{
2581 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
2583 definition
: Named("llvm.aarch64.neon.addp.v4f32")
2585 "paddq_s64" => Intrinsic
{
2586 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
2588 definition
: Named("llvm.aarch64.neon.addp.v2i64")
2590 "paddq_u64" => Intrinsic
{
2591 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }
,
2593 definition
: Named("llvm.aarch64.neon.addp.v2i64")
2595 "paddq_f64" => Intrinsic
{
2596 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }
,
2598 definition
: Named("llvm.aarch64.neon.addp.v2f64")
2600 "paddl_s16" => Intrinsic
{
2601 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }
,
2603 definition
: Named("llvm.aarch64.neon.saddlp.v4i16.v8i8")
2605 "paddl_u16" => Intrinsic
{
2606 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }
,
2608 definition
: Named("llvm.aarch64.neon.uaddlp.v4i16.v8i8")
2610 "paddl_s32" => Intrinsic
{
2611 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }
,
2613 definition
: Named("llvm.aarch64.neon.saddlp.v2i32.v4i16")
2615 "paddl_u32" => Intrinsic
{
2616 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }
,
2618 definition
: Named("llvm.aarch64.neon.uaddlp.v2i32.v4i16")
2620 "paddl_s64" => Intrinsic
{
2621 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }
,
2623 definition
: Named("llvm.aarch64.neon.saddlp.v1i64.v2i32")
2625 "paddl_u64" => Intrinsic
{
2626 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }
,
2628 definition
: Named("llvm.aarch64.neon.uaddlp.v1i64.v2i32")
2630 "paddlq_s16" => Intrinsic
{
2631 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }
,
2633 definition
: Named("llvm.aarch64.neon.saddlp.v8i16.v16i8")
2635 "paddlq_u16" => Intrinsic
{
2636 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }
,
2638 definition
: Named("llvm.aarch64.neon.uaddlp.v8i16.v16i8")
2640 "paddlq_s32" => Intrinsic
{
2641 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }
,
2643 definition
: Named("llvm.aarch64.neon.saddlp.v4i32.v8i16")
2645 "paddlq_u32" => Intrinsic
{
2646 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }
,
2648 definition
: Named("llvm.aarch64.neon.uaddlp.v4i32.v8i16")
2650 "paddlq_s64" => Intrinsic
{
2651 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }
,
2653 definition
: Named("llvm.aarch64.neon.saddlp.v2i64.v4i32")
2655 "paddlq_u64" => Intrinsic
{
2656 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }
,
2658 definition
: Named("llvm.aarch64.neon.uaddlp.v2i64.v4i32")
2660 "pmax_s8" => Intrinsic
{
2661 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
2663 definition
: Named("llvm.aarch64.neon.smaxp.v8i8")
2665 "pmax_u8" => Intrinsic
{
2666 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
2668 definition
: Named("llvm.aarch64.neon.umaxp.v8i8")
2670 "pmax_s16" => Intrinsic
{
2671 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
2673 definition
: Named("llvm.aarch64.neon.smaxp.v4i16")
2675 "pmax_u16" => Intrinsic
{
2676 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
2678 definition
: Named("llvm.aarch64.neon.umaxp.v4i16")
2680 "pmax_s32" => Intrinsic
{
2681 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
2683 definition
: Named("llvm.aarch64.neon.smaxp.v2i32")
2685 "pmax_u32" => Intrinsic
{
2686 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
2688 definition
: Named("llvm.aarch64.neon.umaxp.v2i32")
2690 "pmax_f32" => Intrinsic
{
2691 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
2693 definition
: Named("llvm.aarch64.neon.fmaxp.v2f32")
2695 "pmaxq_s8" => Intrinsic
{
2696 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
2698 definition
: Named("llvm.aarch64.neon.smaxp.v16i8")
2700 "pmaxq_u8" => Intrinsic
{
2701 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
2703 definition
: Named("llvm.aarch64.neon.umaxp.v16i8")
2705 "pmaxq_s16" => Intrinsic
{
2706 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
2708 definition
: Named("llvm.aarch64.neon.smaxp.v8i16")
2710 "pmaxq_u16" => Intrinsic
{
2711 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
2713 definition
: Named("llvm.aarch64.neon.umaxp.v8i16")
2715 "pmaxq_s32" => Intrinsic
{
2716 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
2718 definition
: Named("llvm.aarch64.neon.smaxp.v4i32")
2720 "pmaxq_u32" => Intrinsic
{
2721 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
2723 definition
: Named("llvm.aarch64.neon.umaxp.v4i32")
2725 "pmaxq_f32" => Intrinsic
{
2726 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
2728 definition
: Named("llvm.aarch64.neon.fmaxp.v4f32")
2730 "pmaxq_s64" => Intrinsic
{
2731 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
2733 definition
: Named("llvm.aarch64.neon.smaxp.v2i64")
2735 "pmaxq_u64" => Intrinsic
{
2736 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }
,
2738 definition
: Named("llvm.aarch64.neon.umaxp.v2i64")
2740 "pmaxq_f64" => Intrinsic
{
2741 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }
,
2743 definition
: Named("llvm.aarch64.neon.fmaxp.v2f64")
2745 "pmin_s8" => Intrinsic
{
2746 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
2748 definition
: Named("llvm.aarch64.neon.sminp.v8i8")
2750 "pmin_u8" => Intrinsic
{
2751 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
2753 definition
: Named("llvm.aarch64.neon.uminp.v8i8")
2755 "pmin_s16" => Intrinsic
{
2756 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
2758 definition
: Named("llvm.aarch64.neon.sminp.v4i16")
2760 "pmin_u16" => Intrinsic
{
2761 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
2763 definition
: Named("llvm.aarch64.neon.uminp.v4i16")
2765 "pmin_s32" => Intrinsic
{
2766 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
2768 definition
: Named("llvm.aarch64.neon.sminp.v2i32")
2770 "pmin_u32" => Intrinsic
{
2771 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
2773 definition
: Named("llvm.aarch64.neon.uminp.v2i32")
2775 "pmin_f32" => Intrinsic
{
2776 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
2778 definition
: Named("llvm.aarch64.neon.fminp.v2f32")
2780 "pminq_s8" => Intrinsic
{
2781 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
2783 definition
: Named("llvm.aarch64.neon.sminp.v16i8")
2785 "pminq_u8" => Intrinsic
{
2786 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
2788 definition
: Named("llvm.aarch64.neon.uminp.v16i8")
2790 "pminq_s16" => Intrinsic
{
2791 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
2793 definition
: Named("llvm.aarch64.neon.sminp.v8i16")
2795 "pminq_u16" => Intrinsic
{
2796 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
2798 definition
: Named("llvm.aarch64.neon.uminp.v8i16")
2800 "pminq_s32" => Intrinsic
{
2801 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
2803 definition
: Named("llvm.aarch64.neon.sminp.v4i32")
2805 "pminq_u32" => Intrinsic
{
2806 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
2808 definition
: Named("llvm.aarch64.neon.uminp.v4i32")
2810 "pminq_f32" => Intrinsic
{
2811 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
2813 definition
: Named("llvm.aarch64.neon.fminp.v4f32")
2815 "pminq_s64" => Intrinsic
{
2816 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
2818 definition
: Named("llvm.aarch64.neon.sminp.v2i64")
2820 "pminq_u64" => Intrinsic
{
2821 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }
,
2823 definition
: Named("llvm.aarch64.neon.uminp.v2i64")
2825 "pminq_f64" => Intrinsic
{
2826 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }
,
2828 definition
: Named("llvm.aarch64.neon.fminp.v2f64")
2830 "pmaxnm_s8" => Intrinsic
{
2831 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
2833 definition
: Named("llvm.aarch64.neon.smaxnmp.v8i8")
2835 "pmaxnm_u8" => Intrinsic
{
2836 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
2838 definition
: Named("llvm.aarch64.neon.umaxnmp.v8i8")
2840 "pmaxnm_s16" => Intrinsic
{
2841 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
2843 definition
: Named("llvm.aarch64.neon.smaxnmp.v4i16")
2845 "pmaxnm_u16" => Intrinsic
{
2846 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
2848 definition
: Named("llvm.aarch64.neon.umaxnmp.v4i16")
2850 "pmaxnm_s32" => Intrinsic
{
2851 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
2853 definition
: Named("llvm.aarch64.neon.smaxnmp.v2i32")
2855 "pmaxnm_u32" => Intrinsic
{
2856 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
2858 definition
: Named("llvm.aarch64.neon.umaxnmp.v2i32")
2860 "pmaxnm_f32" => Intrinsic
{
2861 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
2863 definition
: Named("llvm.aarch64.neon.fmaxnmp.v2f32")
2865 "pmaxnmq_s8" => Intrinsic
{
2866 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
2868 definition
: Named("llvm.aarch64.neon.smaxnmp.v16i8")
2870 "pmaxnmq_u8" => Intrinsic
{
2871 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
2873 definition
: Named("llvm.aarch64.neon.umaxnmp.v16i8")
2875 "pmaxnmq_s16" => Intrinsic
{
2876 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
2878 definition
: Named("llvm.aarch64.neon.smaxnmp.v8i16")
2880 "pmaxnmq_u16" => Intrinsic
{
2881 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
2883 definition
: Named("llvm.aarch64.neon.umaxnmp.v8i16")
2885 "pmaxnmq_s32" => Intrinsic
{
2886 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
2888 definition
: Named("llvm.aarch64.neon.smaxnmp.v4i32")
2890 "pmaxnmq_u32" => Intrinsic
{
2891 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
2893 definition
: Named("llvm.aarch64.neon.umaxnmp.v4i32")
2895 "pmaxnmq_f32" => Intrinsic
{
2896 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
2898 definition
: Named("llvm.aarch64.neon.fmaxnmp.v4f32")
2900 "pmaxnmq_s64" => Intrinsic
{
2901 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
2903 definition
: Named("llvm.aarch64.neon.smaxnmp.v2i64")
2905 "pmaxnmq_u64" => Intrinsic
{
2906 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }
,
2908 definition
: Named("llvm.aarch64.neon.umaxnmp.v2i64")
2910 "pmaxnmq_f64" => Intrinsic
{
2911 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }
,
2913 definition
: Named("llvm.aarch64.neon.fmaxnmp.v2f64")
2915 "pminnm_f32" => Intrinsic
{
2916 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
2918 definition
: Named("llvm.aarch64.neon.fminnmp.v2f32")
2920 "pminnmq_f32" => Intrinsic
{
2921 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
2923 definition
: Named("llvm.aarch64.neon.fminnmp.v4f32")
2925 "pminnmq_f64" => Intrinsic
{
2926 inputs
: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }
,
2928 definition
: Named("llvm.aarch64.neon.fminnmp.v2f64")
2930 "addv_s8" => Intrinsic
{
2931 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }
,
2933 definition
: Named("llvm.aarch64.neon.saddv.i8.v8i8")
2935 "addv_u8" => Intrinsic
{
2936 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }
,
2938 definition
: Named("llvm.aarch64.neon.uaddv.i8.v8i8")
2940 "addv_s16" => Intrinsic
{
2941 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }
,
2943 definition
: Named("llvm.aarch64.neon.saddv.i16.v4i16")
2945 "addv_u16" => Intrinsic
{
2946 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }
,
2948 definition
: Named("llvm.aarch64.neon.uaddv.i16.v4i16")
2950 "addv_s32" => Intrinsic
{
2951 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }
,
2953 definition
: Named("llvm.aarch64.neon.saddv.i32.v2i32")
2955 "addv_u32" => Intrinsic
{
2956 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }
,
2958 definition
: Named("llvm.aarch64.neon.uaddv.i32.v2i32")
2960 "addv_f32" => Intrinsic
{
2961 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }
,
2963 definition
: Named("llvm.aarch64.neon.faddv.f32.v2f32")
2965 "addvq_s8" => Intrinsic
{
2966 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }
,
2968 definition
: Named("llvm.aarch64.neon.saddv.i8.v16i8")
2970 "addvq_u8" => Intrinsic
{
2971 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }
,
2973 definition
: Named("llvm.aarch64.neon.uaddv.i8.v16i8")
2975 "addvq_s16" => Intrinsic
{
2976 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }
,
2978 definition
: Named("llvm.aarch64.neon.saddv.i16.v8i16")
2980 "addvq_u16" => Intrinsic
{
2981 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }
,
2983 definition
: Named("llvm.aarch64.neon.uaddv.i16.v8i16")
2985 "addvq_s32" => Intrinsic
{
2986 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }
,
2988 definition
: Named("llvm.aarch64.neon.saddv.i32.v4i32")
2990 "addvq_u32" => Intrinsic
{
2991 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }
,
2993 definition
: Named("llvm.aarch64.neon.uaddv.i32.v4i32")
2995 "addvq_f32" => Intrinsic
{
2996 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }
,
2998 definition
: Named("llvm.aarch64.neon.faddv.f32.v4f32")
3000 "addvq_s64" => Intrinsic
{
3001 inputs
: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS }
,
3003 definition
: Named("llvm.aarch64.neon.saddv.i64.v2i64")
3005 "addvq_u64" => Intrinsic
{
3006 inputs
: { static INPUTS: [&'static Type; 1] = [&::U64x2]; &INPUTS }
,
3008 definition
: Named("llvm.aarch64.neon.uaddv.i64.v2i64")
3010 "addvq_f64" => Intrinsic
{
3011 inputs
: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }
,
3013 definition
: Named("llvm.aarch64.neon.faddv.f64.v2f64")
3015 "addlv_s8" => Intrinsic
{
3016 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }
,
3018 definition
: Named("llvm.aarch64.neon.saddlv.i16.v8i8")
3020 "addlv_u8" => Intrinsic
{
3021 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }
,
3023 definition
: Named("llvm.aarch64.neon.uaddlv.i16.v8i8")
3025 "addlv_s16" => Intrinsic
{
3026 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }
,
3028 definition
: Named("llvm.aarch64.neon.saddlv.i32.v4i16")
3030 "addlv_u16" => Intrinsic
{
3031 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }
,
3033 definition
: Named("llvm.aarch64.neon.uaddlv.i32.v4i16")
3035 "addlv_s32" => Intrinsic
{
3036 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }
,
3038 definition
: Named("llvm.aarch64.neon.saddlv.i64.v2i32")
3040 "addlv_u32" => Intrinsic
{
3041 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }
,
3043 definition
: Named("llvm.aarch64.neon.uaddlv.i64.v2i32")
3045 "addlvq_s8" => Intrinsic
{
3046 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }
,
3048 definition
: Named("llvm.aarch64.neon.saddlv.i16.v16i8")
3050 "addlvq_u8" => Intrinsic
{
3051 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }
,
3053 definition
: Named("llvm.aarch64.neon.uaddlv.i16.v16i8")
3055 "addlvq_s16" => Intrinsic
{
3056 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }
,
3058 definition
: Named("llvm.aarch64.neon.saddlv.i32.v8i16")
3060 "addlvq_u16" => Intrinsic
{
3061 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }
,
3063 definition
: Named("llvm.aarch64.neon.uaddlv.i32.v8i16")
3065 "addlvq_s32" => Intrinsic
{
3066 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }
,
3068 definition
: Named("llvm.aarch64.neon.saddlv.i64.v4i32")
3070 "addlvq_u32" => Intrinsic
{
3071 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }
,
3073 definition
: Named("llvm.aarch64.neon.uaddlv.i64.v4i32")
3075 "maxv_s8" => Intrinsic
{
3076 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }
,
3078 definition
: Named("llvm.aarch64.neon.smaxv.i8.v8i8")
3080 "maxv_u8" => Intrinsic
{
3081 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }
,
3083 definition
: Named("llvm.aarch64.neon.umaxv.i8.v8i8")
3085 "maxv_s16" => Intrinsic
{
3086 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }
,
3088 definition
: Named("llvm.aarch64.neon.smaxv.i16.v4i16")
3090 "maxv_u16" => Intrinsic
{
3091 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }
,
3093 definition
: Named("llvm.aarch64.neon.umaxv.i16.v4i16")
3095 "maxv_s32" => Intrinsic
{
3096 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }
,
3098 definition
: Named("llvm.aarch64.neon.smaxv.i32.v2i32")
3100 "maxv_u32" => Intrinsic
{
3101 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }
,
3103 definition
: Named("llvm.aarch64.neon.umaxv.i32.v2i32")
3105 "maxv_f32" => Intrinsic
{
3106 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }
,
3108 definition
: Named("llvm.aarch64.neon.fmaxv.f32.v2f32")
3110 "maxvq_s8" => Intrinsic
{
3111 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }
,
3113 definition
: Named("llvm.aarch64.neon.smaxv.i8.v16i8")
3115 "maxvq_u8" => Intrinsic
{
3116 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }
,
3118 definition
: Named("llvm.aarch64.neon.umaxv.i8.v16i8")
3120 "maxvq_s16" => Intrinsic
{
3121 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }
,
3123 definition
: Named("llvm.aarch64.neon.smaxv.i16.v8i16")
3125 "maxvq_u16" => Intrinsic
{
3126 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }
,
3128 definition
: Named("llvm.aarch64.neon.umaxv.i16.v8i16")
3130 "maxvq_s32" => Intrinsic
{
3131 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }
,
3133 definition
: Named("llvm.aarch64.neon.smaxv.i32.v4i32")
3135 "maxvq_u32" => Intrinsic
{
3136 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }
,
3138 definition
: Named("llvm.aarch64.neon.umaxv.i32.v4i32")
3140 "maxvq_f32" => Intrinsic
{
3141 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }
,
3143 definition
: Named("llvm.aarch64.neon.fmaxv.f32.v4f32")
3145 "maxvq_f64" => Intrinsic
{
3146 inputs
: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }
,
3148 definition
: Named("llvm.aarch64.neon.fmaxv.f64.v2f64")
3150 "minv_s8" => Intrinsic
{
3151 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }
,
3153 definition
: Named("llvm.aarch64.neon.sminv.i8.v8i8")
3155 "minv_u8" => Intrinsic
{
3156 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }
,
3158 definition
: Named("llvm.aarch64.neon.uminv.i8.v8i8")
3160 "minv_s16" => Intrinsic
{
3161 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }
,
3163 definition
: Named("llvm.aarch64.neon.sminv.i16.v4i16")
3165 "minv_u16" => Intrinsic
{
3166 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }
,
3168 definition
: Named("llvm.aarch64.neon.uminv.i16.v4i16")
3170 "minv_s32" => Intrinsic
{
3171 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }
,
3173 definition
: Named("llvm.aarch64.neon.sminv.i32.v2i32")
3175 "minv_u32" => Intrinsic
{
3176 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }
,
3178 definition
: Named("llvm.aarch64.neon.uminv.i32.v2i32")
3180 "minv_f32" => Intrinsic
{
3181 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }
,
3183 definition
: Named("llvm.aarch64.neon.fminv.f32.v2f32")
3185 "minvq_s8" => Intrinsic
{
3186 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }
,
3188 definition
: Named("llvm.aarch64.neon.sminv.i8.v16i8")
3190 "minvq_u8" => Intrinsic
{
3191 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }
,
3193 definition
: Named("llvm.aarch64.neon.uminv.i8.v16i8")
3195 "minvq_s16" => Intrinsic
{
3196 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }
,
3198 definition
: Named("llvm.aarch64.neon.sminv.i16.v8i16")
3200 "minvq_u16" => Intrinsic
{
3201 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }
,
3203 definition
: Named("llvm.aarch64.neon.uminv.i16.v8i16")
3205 "minvq_s32" => Intrinsic
{
3206 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }
,
3208 definition
: Named("llvm.aarch64.neon.sminv.i32.v4i32")
3210 "minvq_u32" => Intrinsic
{
3211 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }
,
3213 definition
: Named("llvm.aarch64.neon.uminv.i32.v4i32")
3215 "minvq_f32" => Intrinsic
{
3216 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }
,
3218 definition
: Named("llvm.aarch64.neon.fminv.f32.v4f32")
3220 "minvq_f64" => Intrinsic
{
3221 inputs
: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }
,
3223 definition
: Named("llvm.aarch64.neon.fminv.f64.v2f64")
3225 "maxnmv_f32" => Intrinsic
{
3226 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }
,
3228 definition
: Named("llvm.aarch64.neon.fmaxnmv.f32.v2f32")
3230 "maxnmvq_f32" => Intrinsic
{
3231 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }
,
3233 definition
: Named("llvm.aarch64.neon.fmaxnmv.f32.v4f32")
3235 "maxnmvq_f64" => Intrinsic
{
3236 inputs
: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }
,
3238 definition
: Named("llvm.aarch64.neon.fmaxnmv.f64.v2f64")
3240 "minnmv_f32" => Intrinsic
{
3241 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }
,
3243 definition
: Named("llvm.aarch64.neon.fminnmv.f32.v2f32")
3245 "minnmvq_f32" => Intrinsic
{
3246 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }
,
3248 definition
: Named("llvm.aarch64.neon.fminnmv.f32.v4f32")
3250 "minnmvq_f64" => Intrinsic
{
3251 inputs
: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }
,
3253 definition
: Named("llvm.aarch64.neon.fminnmv.f64.v2f64")
3255 "qtbl1_s8" => Intrinsic
{
3256 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::U8x8]; &INPUTS }
,
3258 definition
: Named("llvm.aarch64.neon.tbl1.v8i8")
3260 "qtbl1_u8" => Intrinsic
{
3261 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x8]; &INPUTS }
,
3263 definition
: Named("llvm.aarch64.neon.tbl1.v8i8")
3265 "qtbl1q_s8" => Intrinsic
{
3266 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::U8x16]; &INPUTS }
,
3268 definition
: Named("llvm.aarch64.neon.tbl1.v16i8")
3270 "qtbl1q_u8" => Intrinsic
{
3271 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
3273 definition
: Named("llvm.aarch64.neon.tbl1.v16i8")
3275 "qtbx1_s8" => Intrinsic
{
3276 inputs
: { static INPUTS: [&'static Type; 3] = [&::I8x8, &::I8x16, &::U8x8]; &INPUTS }
,
3278 definition
: Named("llvm.aarch64.neon.tbx1.v8i8")
3280 "qtbx1_u8" => Intrinsic
{
3281 inputs
: { static INPUTS: [&'static Type; 3] = [&::U8x8, &::U8x16, &::U8x8]; &INPUTS }
,
3283 definition
: Named("llvm.aarch64.neon.tbx1.v8i8")
3285 "qtbx1q_s8" => Intrinsic
{
3286 inputs
: { static INPUTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::U8x16]; &INPUTS }
,
3288 definition
: Named("llvm.aarch64.neon.tbx1.v16i8")
3290 "qtbx1q_u8" => Intrinsic
{
3291 inputs
: { static INPUTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &INPUTS }
,
3293 definition
: Named("llvm.aarch64.neon.tbx1.v16i8")
3295 "qtbl2_s8" => Intrinsic
{
3296 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
3298 definition
: Named("llvm.aarch64.neon.tbl2.v8i8")
3300 "qtbl2_u8" => Intrinsic
{
3301 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
3303 definition
: Named("llvm.aarch64.neon.tbl2.v8i8")
3305 "qtbl2q_s8" => Intrinsic
{
3306 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }
); &AGG
}, &::U8x16
]; &INPUTS
},
3308 definition
: Named("llvm.aarch64.neon.tbl2.v16i8")
3310 "qtbl2q_u8" => Intrinsic
{
3311 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }
); &AGG
}, &::U8x16
]; &INPUTS
},
3313 definition
: Named("llvm.aarch64.neon.tbl2.v16i8")
3315 "qtbx2_s8" => Intrinsic
{
3316 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
3318 definition
: Named("llvm.aarch64.neon.tbx2.v8i8")
3320 "qtbx2_u8" => Intrinsic
{
3321 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
3323 definition
: Named("llvm.aarch64.neon.tbx2.v8i8")
3325 "qtbx2q_s8" => Intrinsic
{
3326 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }
); &AGG
}, &::U8x16
]; &INPUTS
},
3328 definition
: Named("llvm.aarch64.neon.tbx2.v16i8")
3330 "qtbx2q_u8" => Intrinsic
{
3331 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }
); &AGG
}, &::U8x16
]; &INPUTS
},
3333 definition
: Named("llvm.aarch64.neon.tbx2.v16i8")
3335 "qtbl3_s8" => Intrinsic
{
3336 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
3338 definition
: Named("llvm.aarch64.neon.tbl3.v8i8")
3340 "qtbl3_u8" => Intrinsic
{
3341 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
3343 definition
: Named("llvm.aarch64.neon.tbl3.v8i8")
3345 "qtbl3q_s8" => Intrinsic
{
3346 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }
); &AGG
}, &::U8x16
]; &INPUTS
},
3348 definition
: Named("llvm.aarch64.neon.tbl3.v16i8")
3350 "qtbl3q_u8" => Intrinsic
{
3351 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }
); &AGG
}, &::U8x16
]; &INPUTS
},
3353 definition
: Named("llvm.aarch64.neon.tbl3.v16i8")
3355 "qtbx3_s8" => Intrinsic
{
3356 inputs
: { static INPUTS: [&'static Type; 3] = [&::I8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
3358 definition
: Named("llvm.aarch64.neon.tbx3.v8i8")
3360 "qtbx3_u8" => Intrinsic
{
3361 inputs
: { static INPUTS: [&'static Type; 3] = [&::U8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
3363 definition
: Named("llvm.aarch64.neon.tbx3.v8i8")
3365 "qtbx3q_s8" => Intrinsic
{
3366 inputs
: { static INPUTS: [&'static Type; 3] = [&::I8x16, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }
); &AGG
}, &::U8x16
]; &INPUTS
},
3368 definition
: Named("llvm.aarch64.neon.tbx3.v16i8")
3370 "qtbx3q_u8" => Intrinsic
{
3371 inputs
: { static INPUTS: [&'static Type; 3] = [&::U8x16, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }
); &AGG
}, &::U8x16
]; &INPUTS
},
3373 definition
: Named("llvm.aarch64.neon.tbx3.v16i8")
3375 "qtbl4_s8" => Intrinsic
{
3376 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
3378 definition
: Named("llvm.aarch64.neon.tbl4.v8i8")
3380 "qtbl4_u8" => Intrinsic
{
3381 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
3383 definition
: Named("llvm.aarch64.neon.tbl4.v8i8")
3385 "qtbl4q_s8" => Intrinsic
{
3386 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }
); &AGG
}, &::U8x16
]; &INPUTS
},
3388 definition
: Named("llvm.aarch64.neon.tbl4.v16i8")
3390 "qtbl4q_u8" => Intrinsic
{
3391 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }
); &AGG
}, &::U8x16
]; &INPUTS
},
3393 definition
: Named("llvm.aarch64.neon.tbl4.v16i8")
3395 "qtbx4_s8" => Intrinsic
{
3396 inputs
: { static INPUTS: [&'static Type; 3] = [&::I8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
3398 definition
: Named("llvm.aarch64.neon.tbx4.v8i8")
3400 "qtbx4_u8" => Intrinsic
{
3401 inputs
: { static INPUTS: [&'static Type; 3] = [&::U8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
3403 definition
: Named("llvm.aarch64.neon.tbx4.v8i8")
3405 "qtbx4q_s8" => Intrinsic
{
3406 inputs
: { static INPUTS: [&'static Type; 3] = [&::I8x16, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }
); &AGG
}, &::U8x16
]; &INPUTS
},
3408 definition
: Named("llvm.aarch64.neon.tbx4.v16i8")
3410 "qtbx4q_u8" => Intrinsic
{
3411 inputs
: { static INPUTS: [&'static Type; 3] = [&::U8x16, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }
); &AGG
}, &::U8x16
]; &INPUTS
},
3413 definition
: Named("llvm.aarch64.neon.tbx4.v16i8")