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Imported Upstream version 1.9.0+dfsg1
[rustc.git] / src / librustc_platform_intrinsics / arm.rs
1 // Copyright 2015 The Rust Project Developers. See the COPYRIGHT
2 // file at the top-level directory of this distribution and at
3 // http://rust-lang.org/COPYRIGHT.
4 //
5 // Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
6 // http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
7 // <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
8 // option. This file may not be copied, modified, or distributed
9 // except according to those terms.
10
11 // DO NOT EDIT: autogenerated by etc/platform-intrinsics/generator.py
12 // ignore-tidy-linelength
13
14 #![allow(unused_imports)]
15
16 use {Intrinsic, Type};
17 use IntrinsicDef::Named;
18
19 // The default inlining settings trigger a pathological behaviour in
20 // LLVM, which causes makes compilation very slow. See #28273.
21 #[inline(never)]
22 pub fn find(name: &str) -> Option<Intrinsic> {
23 if !name.starts_with("arm_v") { return None }
24 Some(match &name["arm_v".len()..] {
25 "hadd_s8" => Intrinsic {
26 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
27 output: &::I8x8,
28 definition: Named("llvm.neon.vhadds.v8i8")
29 },
30 "hadd_u8" => Intrinsic {
31 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
32 output: &::U8x8,
33 definition: Named("llvm.neon.vhaddu.v8i8")
34 },
35 "hadd_s16" => Intrinsic {
36 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
37 output: &::I16x4,
38 definition: Named("llvm.neon.vhadds.v4i16")
39 },
40 "hadd_u16" => Intrinsic {
41 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
42 output: &::U16x4,
43 definition: Named("llvm.neon.vhaddu.v4i16")
44 },
45 "hadd_s32" => Intrinsic {
46 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
47 output: &::I32x2,
48 definition: Named("llvm.neon.vhadds.v2i32")
49 },
50 "hadd_u32" => Intrinsic {
51 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
52 output: &::U32x2,
53 definition: Named("llvm.neon.vhaddu.v2i32")
54 },
55 "haddq_s8" => Intrinsic {
56 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
57 output: &::I8x16,
58 definition: Named("llvm.neon.vhadds.v16i8")
59 },
60 "haddq_u8" => Intrinsic {
61 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
62 output: &::U8x16,
63 definition: Named("llvm.neon.vhaddu.v16i8")
64 },
65 "haddq_s16" => Intrinsic {
66 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
67 output: &::I16x8,
68 definition: Named("llvm.neon.vhadds.v8i16")
69 },
70 "haddq_u16" => Intrinsic {
71 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
72 output: &::U16x8,
73 definition: Named("llvm.neon.vhaddu.v8i16")
74 },
75 "haddq_s32" => Intrinsic {
76 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
77 output: &::I32x4,
78 definition: Named("llvm.neon.vhadds.v4i32")
79 },
80 "haddq_u32" => Intrinsic {
81 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
82 output: &::U32x4,
83 definition: Named("llvm.neon.vhaddu.v4i32")
84 },
85 "rhadd_s8" => Intrinsic {
86 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
87 output: &::I8x8,
88 definition: Named("llvm.neon.vrhadds.v8i8")
89 },
90 "rhadd_u8" => Intrinsic {
91 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
92 output: &::U8x8,
93 definition: Named("llvm.neon.vrhaddu.v8i8")
94 },
95 "rhadd_s16" => Intrinsic {
96 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
97 output: &::I16x4,
98 definition: Named("llvm.neon.vrhadds.v4i16")
99 },
100 "rhadd_u16" => Intrinsic {
101 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
102 output: &::U16x4,
103 definition: Named("llvm.neon.vrhaddu.v4i16")
104 },
105 "rhadd_s32" => Intrinsic {
106 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
107 output: &::I32x2,
108 definition: Named("llvm.neon.vrhadds.v2i32")
109 },
110 "rhadd_u32" => Intrinsic {
111 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
112 output: &::U32x2,
113 definition: Named("llvm.neon.vrhaddu.v2i32")
114 },
115 "rhaddq_s8" => Intrinsic {
116 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
117 output: &::I8x16,
118 definition: Named("llvm.neon.vrhadds.v16i8")
119 },
120 "rhaddq_u8" => Intrinsic {
121 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
122 output: &::U8x16,
123 definition: Named("llvm.neon.vrhaddu.v16i8")
124 },
125 "rhaddq_s16" => Intrinsic {
126 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
127 output: &::I16x8,
128 definition: Named("llvm.neon.vrhadds.v8i16")
129 },
130 "rhaddq_u16" => Intrinsic {
131 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
132 output: &::U16x8,
133 definition: Named("llvm.neon.vrhaddu.v8i16")
134 },
135 "rhaddq_s32" => Intrinsic {
136 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
137 output: &::I32x4,
138 definition: Named("llvm.neon.vrhadds.v4i32")
139 },
140 "rhaddq_u32" => Intrinsic {
141 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
142 output: &::U32x4,
143 definition: Named("llvm.neon.vrhaddu.v4i32")
144 },
145 "qadd_s8" => Intrinsic {
146 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
147 output: &::I8x8,
148 definition: Named("llvm.neon.vqadds.v8i8")
149 },
150 "qadd_u8" => Intrinsic {
151 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
152 output: &::U8x8,
153 definition: Named("llvm.neon.vqaddu.v8i8")
154 },
155 "qadd_s16" => Intrinsic {
156 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
157 output: &::I16x4,
158 definition: Named("llvm.neon.vqadds.v4i16")
159 },
160 "qadd_u16" => Intrinsic {
161 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
162 output: &::U16x4,
163 definition: Named("llvm.neon.vqaddu.v4i16")
164 },
165 "qadd_s32" => Intrinsic {
166 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
167 output: &::I32x2,
168 definition: Named("llvm.neon.vqadds.v2i32")
169 },
170 "qadd_u32" => Intrinsic {
171 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
172 output: &::U32x2,
173 definition: Named("llvm.neon.vqaddu.v2i32")
174 },
175 "qadd_s64" => Intrinsic {
176 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
177 output: &::I64x1,
178 definition: Named("llvm.neon.vqadds.v1i64")
179 },
180 "qadd_u64" => Intrinsic {
181 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
182 output: &::U64x1,
183 definition: Named("llvm.neon.vqaddu.v1i64")
184 },
185 "qaddq_s8" => Intrinsic {
186 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
187 output: &::I8x16,
188 definition: Named("llvm.neon.vqadds.v16i8")
189 },
190 "qaddq_u8" => Intrinsic {
191 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
192 output: &::U8x16,
193 definition: Named("llvm.neon.vqaddu.v16i8")
194 },
195 "qaddq_s16" => Intrinsic {
196 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
197 output: &::I16x8,
198 definition: Named("llvm.neon.vqadds.v8i16")
199 },
200 "qaddq_u16" => Intrinsic {
201 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
202 output: &::U16x8,
203 definition: Named("llvm.neon.vqaddu.v8i16")
204 },
205 "qaddq_s32" => Intrinsic {
206 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
207 output: &::I32x4,
208 definition: Named("llvm.neon.vqadds.v4i32")
209 },
210 "qaddq_u32" => Intrinsic {
211 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
212 output: &::U32x4,
213 definition: Named("llvm.neon.vqaddu.v4i32")
214 },
215 "qaddq_s64" => Intrinsic {
216 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
217 output: &::I64x2,
218 definition: Named("llvm.neon.vqadds.v2i64")
219 },
220 "qaddq_u64" => Intrinsic {
221 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
222 output: &::U64x2,
223 definition: Named("llvm.neon.vqaddu.v2i64")
224 },
225 "raddhn_s16" => Intrinsic {
226 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
227 output: &::I8x8,
228 definition: Named("llvm.neon.vraddhn.v8i8")
229 },
230 "raddhn_u16" => Intrinsic {
231 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
232 output: &::U8x8,
233 definition: Named("llvm.neon.vraddhn.v8i8")
234 },
235 "raddhn_s32" => Intrinsic {
236 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
237 output: &::I16x4,
238 definition: Named("llvm.neon.vraddhn.v4i16")
239 },
240 "raddhn_u32" => Intrinsic {
241 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
242 output: &::U16x4,
243 definition: Named("llvm.neon.vraddhn.v4i16")
244 },
245 "raddhn_s64" => Intrinsic {
246 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
247 output: &::I32x2,
248 definition: Named("llvm.neon.vraddhn.v2i32")
249 },
250 "raddhn_u64" => Intrinsic {
251 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
252 output: &::U32x2,
253 definition: Named("llvm.neon.vraddhn.v2i32")
254 },
255 "fma_f32" => Intrinsic {
256 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
257 output: &::F32x2,
258 definition: Named("llvm.fma.v2f32")
259 },
260 "fmaq_f32" => Intrinsic {
261 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
262 output: &::F32x4,
263 definition: Named("llvm.fma.v4f32")
264 },
265 "qdmulh_s16" => Intrinsic {
266 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
267 output: &::I16x4,
268 definition: Named("llvm.neon.vsqdmulh.v4i16")
269 },
270 "qdmulh_s32" => Intrinsic {
271 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
272 output: &::I32x2,
273 definition: Named("llvm.neon.vsqdmulh.v2i32")
274 },
275 "qdmulhq_s16" => Intrinsic {
276 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
277 output: &::I16x8,
278 definition: Named("llvm.neon.vsqdmulh.v8i16")
279 },
280 "qdmulhq_s32" => Intrinsic {
281 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
282 output: &::I32x4,
283 definition: Named("llvm.neon.vsqdmulh.v4i32")
284 },
285 "qrdmulh_s16" => Intrinsic {
286 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
287 output: &::I16x4,
288 definition: Named("llvm.neon.vsqrdmulh.v4i16")
289 },
290 "qrdmulh_s32" => Intrinsic {
291 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
292 output: &::I32x2,
293 definition: Named("llvm.neon.vsqrdmulh.v2i32")
294 },
295 "qrdmulhq_s16" => Intrinsic {
296 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
297 output: &::I16x8,
298 definition: Named("llvm.neon.vsqrdmulh.v8i16")
299 },
300 "qrdmulhq_s32" => Intrinsic {
301 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
302 output: &::I32x4,
303 definition: Named("llvm.neon.vsqrdmulh.v4i32")
304 },
305 "mull_s8" => Intrinsic {
306 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
307 output: &::I16x8,
308 definition: Named("llvm.neon.vmulls.v8i16")
309 },
310 "mull_u8" => Intrinsic {
311 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
312 output: &::U16x8,
313 definition: Named("llvm.neon.vmullu.v8i16")
314 },
315 "mull_s16" => Intrinsic {
316 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
317 output: &::I32x4,
318 definition: Named("llvm.neon.vmulls.v4i32")
319 },
320 "mull_u16" => Intrinsic {
321 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
322 output: &::U32x4,
323 definition: Named("llvm.neon.vmullu.v4i32")
324 },
325 "mull_s32" => Intrinsic {
326 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
327 output: &::I64x2,
328 definition: Named("llvm.neon.vmulls.v2i64")
329 },
330 "mull_u32" => Intrinsic {
331 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
332 output: &::U64x2,
333 definition: Named("llvm.neon.vmullu.v2i64")
334 },
335 "qdmullq_s8" => Intrinsic {
336 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
337 output: &::I16x8,
338 definition: Named("llvm.neon.vsqdmull.v8i16")
339 },
340 "qdmullq_s16" => Intrinsic {
341 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
342 output: &::I32x4,
343 definition: Named("llvm.neon.vsqdmull.v4i32")
344 },
345 "hsub_s8" => Intrinsic {
346 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
347 output: &::I8x8,
348 definition: Named("llvm.neon.vhsubs.v8i8")
349 },
350 "hsub_u8" => Intrinsic {
351 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
352 output: &::U8x8,
353 definition: Named("llvm.neon.vhsubu.v8i8")
354 },
355 "hsub_s16" => Intrinsic {
356 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
357 output: &::I16x4,
358 definition: Named("llvm.neon.vhsubs.v4i16")
359 },
360 "hsub_u16" => Intrinsic {
361 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
362 output: &::U16x4,
363 definition: Named("llvm.neon.vhsubu.v4i16")
364 },
365 "hsub_s32" => Intrinsic {
366 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
367 output: &::I32x2,
368 definition: Named("llvm.neon.vhsubs.v2i32")
369 },
370 "hsub_u32" => Intrinsic {
371 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
372 output: &::U32x2,
373 definition: Named("llvm.neon.vhsubu.v2i32")
374 },
375 "hsubq_s8" => Intrinsic {
376 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
377 output: &::I8x16,
378 definition: Named("llvm.neon.vhsubs.v16i8")
379 },
380 "hsubq_u8" => Intrinsic {
381 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
382 output: &::U8x16,
383 definition: Named("llvm.neon.vhsubu.v16i8")
384 },
385 "hsubq_s16" => Intrinsic {
386 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
387 output: &::I16x8,
388 definition: Named("llvm.neon.vhsubs.v8i16")
389 },
390 "hsubq_u16" => Intrinsic {
391 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
392 output: &::U16x8,
393 definition: Named("llvm.neon.vhsubu.v8i16")
394 },
395 "hsubq_s32" => Intrinsic {
396 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
397 output: &::I32x4,
398 definition: Named("llvm.neon.vhsubs.v4i32")
399 },
400 "hsubq_u32" => Intrinsic {
401 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
402 output: &::U32x4,
403 definition: Named("llvm.neon.vhsubu.v4i32")
404 },
405 "qsub_s8" => Intrinsic {
406 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
407 output: &::I8x8,
408 definition: Named("llvm.neon.vqsubs.v8i8")
409 },
410 "qsub_u8" => Intrinsic {
411 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
412 output: &::U8x8,
413 definition: Named("llvm.neon.vqsubu.v8i8")
414 },
415 "qsub_s16" => Intrinsic {
416 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
417 output: &::I16x4,
418 definition: Named("llvm.neon.vqsubs.v4i16")
419 },
420 "qsub_u16" => Intrinsic {
421 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
422 output: &::U16x4,
423 definition: Named("llvm.neon.vqsubu.v4i16")
424 },
425 "qsub_s32" => Intrinsic {
426 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
427 output: &::I32x2,
428 definition: Named("llvm.neon.vqsubs.v2i32")
429 },
430 "qsub_u32" => Intrinsic {
431 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
432 output: &::U32x2,
433 definition: Named("llvm.neon.vqsubu.v2i32")
434 },
435 "qsub_s64" => Intrinsic {
436 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
437 output: &::I64x1,
438 definition: Named("llvm.neon.vqsubs.v1i64")
439 },
440 "qsub_u64" => Intrinsic {
441 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
442 output: &::U64x1,
443 definition: Named("llvm.neon.vqsubu.v1i64")
444 },
445 "qsubq_s8" => Intrinsic {
446 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
447 output: &::I8x16,
448 definition: Named("llvm.neon.vqsubs.v16i8")
449 },
450 "qsubq_u8" => Intrinsic {
451 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
452 output: &::U8x16,
453 definition: Named("llvm.neon.vqsubu.v16i8")
454 },
455 "qsubq_s16" => Intrinsic {
456 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
457 output: &::I16x8,
458 definition: Named("llvm.neon.vqsubs.v8i16")
459 },
460 "qsubq_u16" => Intrinsic {
461 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
462 output: &::U16x8,
463 definition: Named("llvm.neon.vqsubu.v8i16")
464 },
465 "qsubq_s32" => Intrinsic {
466 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
467 output: &::I32x4,
468 definition: Named("llvm.neon.vqsubs.v4i32")
469 },
470 "qsubq_u32" => Intrinsic {
471 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
472 output: &::U32x4,
473 definition: Named("llvm.neon.vqsubu.v4i32")
474 },
475 "qsubq_s64" => Intrinsic {
476 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
477 output: &::I64x2,
478 definition: Named("llvm.neon.vqsubs.v2i64")
479 },
480 "qsubq_u64" => Intrinsic {
481 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
482 output: &::U64x2,
483 definition: Named("llvm.neon.vqsubu.v2i64")
484 },
485 "rsubhn_s16" => Intrinsic {
486 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
487 output: &::I8x8,
488 definition: Named("llvm.neon.vrsubhn.v8i8")
489 },
490 "rsubhn_u16" => Intrinsic {
491 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
492 output: &::U8x8,
493 definition: Named("llvm.neon.vrsubhn.v8i8")
494 },
495 "rsubhn_s32" => Intrinsic {
496 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
497 output: &::I16x4,
498 definition: Named("llvm.neon.vrsubhn.v4i16")
499 },
500 "rsubhn_u32" => Intrinsic {
501 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
502 output: &::U16x4,
503 definition: Named("llvm.neon.vrsubhn.v4i16")
504 },
505 "rsubhn_s64" => Intrinsic {
506 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
507 output: &::I32x2,
508 definition: Named("llvm.neon.vrsubhn.v2i32")
509 },
510 "rsubhn_u64" => Intrinsic {
511 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
512 output: &::U32x2,
513 definition: Named("llvm.neon.vrsubhn.v2i32")
514 },
515 "abd_s8" => Intrinsic {
516 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
517 output: &::I8x8,
518 definition: Named("llvm.neon.vabds.v8i8")
519 },
520 "abd_u8" => Intrinsic {
521 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
522 output: &::U8x8,
523 definition: Named("llvm.neon.vabdu.v8i8")
524 },
525 "abd_s16" => Intrinsic {
526 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
527 output: &::I16x4,
528 definition: Named("llvm.neon.vabds.v4i16")
529 },
530 "abd_u16" => Intrinsic {
531 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
532 output: &::U16x4,
533 definition: Named("llvm.neon.vabdu.v4i16")
534 },
535 "abd_s32" => Intrinsic {
536 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
537 output: &::I32x2,
538 definition: Named("llvm.neon.vabds.v2i32")
539 },
540 "abd_u32" => Intrinsic {
541 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
542 output: &::U32x2,
543 definition: Named("llvm.neon.vabdu.v2i32")
544 },
545 "abd_f32" => Intrinsic {
546 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
547 output: &::F32x2,
548 definition: Named("llvm.neon.vabdf.v2f32")
549 },
550 "abdq_s8" => Intrinsic {
551 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
552 output: &::I8x16,
553 definition: Named("llvm.neon.vabds.v16i8")
554 },
555 "abdq_u8" => Intrinsic {
556 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
557 output: &::U8x16,
558 definition: Named("llvm.neon.vabdu.v16i8")
559 },
560 "abdq_s16" => Intrinsic {
561 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
562 output: &::I16x8,
563 definition: Named("llvm.neon.vabds.v8i16")
564 },
565 "abdq_u16" => Intrinsic {
566 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
567 output: &::U16x8,
568 definition: Named("llvm.neon.vabdu.v8i16")
569 },
570 "abdq_s32" => Intrinsic {
571 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
572 output: &::I32x4,
573 definition: Named("llvm.neon.vabds.v4i32")
574 },
575 "abdq_u32" => Intrinsic {
576 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
577 output: &::U32x4,
578 definition: Named("llvm.neon.vabdu.v4i32")
579 },
580 "abdq_f32" => Intrinsic {
581 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
582 output: &::F32x4,
583 definition: Named("llvm.neon.vabdf.v4f32")
584 },
585 "max_s8" => Intrinsic {
586 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
587 output: &::I8x8,
588 definition: Named("llvm.neon.vmaxs.v8i8")
589 },
590 "max_u8" => Intrinsic {
591 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
592 output: &::U8x8,
593 definition: Named("llvm.neon.vmaxu.v8i8")
594 },
595 "max_s16" => Intrinsic {
596 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
597 output: &::I16x4,
598 definition: Named("llvm.neon.vmaxs.v4i16")
599 },
600 "max_u16" => Intrinsic {
601 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
602 output: &::U16x4,
603 definition: Named("llvm.neon.vmaxu.v4i16")
604 },
605 "max_s32" => Intrinsic {
606 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
607 output: &::I32x2,
608 definition: Named("llvm.neon.vmaxs.v2i32")
609 },
610 "max_u32" => Intrinsic {
611 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
612 output: &::U32x2,
613 definition: Named("llvm.neon.vmaxu.v2i32")
614 },
615 "max_f32" => Intrinsic {
616 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
617 output: &::F32x2,
618 definition: Named("llvm.neon.vmaxf.v2f32")
619 },
620 "maxq_s8" => Intrinsic {
621 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
622 output: &::I8x16,
623 definition: Named("llvm.neon.vmaxs.v16i8")
624 },
625 "maxq_u8" => Intrinsic {
626 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
627 output: &::U8x16,
628 definition: Named("llvm.neon.vmaxu.v16i8")
629 },
630 "maxq_s16" => Intrinsic {
631 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
632 output: &::I16x8,
633 definition: Named("llvm.neon.vmaxs.v8i16")
634 },
635 "maxq_u16" => Intrinsic {
636 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
637 output: &::U16x8,
638 definition: Named("llvm.neon.vmaxu.v8i16")
639 },
640 "maxq_s32" => Intrinsic {
641 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
642 output: &::I32x4,
643 definition: Named("llvm.neon.vmaxs.v4i32")
644 },
645 "maxq_u32" => Intrinsic {
646 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
647 output: &::U32x4,
648 definition: Named("llvm.neon.vmaxu.v4i32")
649 },
650 "maxq_f32" => Intrinsic {
651 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
652 output: &::F32x4,
653 definition: Named("llvm.neon.vmaxf.v4f32")
654 },
655 "min_s8" => Intrinsic {
656 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
657 output: &::I8x8,
658 definition: Named("llvm.neon.vmins.v8i8")
659 },
660 "min_u8" => Intrinsic {
661 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
662 output: &::U8x8,
663 definition: Named("llvm.neon.vminu.v8i8")
664 },
665 "min_s16" => Intrinsic {
666 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
667 output: &::I16x4,
668 definition: Named("llvm.neon.vmins.v4i16")
669 },
670 "min_u16" => Intrinsic {
671 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
672 output: &::U16x4,
673 definition: Named("llvm.neon.vminu.v4i16")
674 },
675 "min_s32" => Intrinsic {
676 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
677 output: &::I32x2,
678 definition: Named("llvm.neon.vmins.v2i32")
679 },
680 "min_u32" => Intrinsic {
681 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
682 output: &::U32x2,
683 definition: Named("llvm.neon.vminu.v2i32")
684 },
685 "min_f32" => Intrinsic {
686 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
687 output: &::F32x2,
688 definition: Named("llvm.neon.vminf.v2f32")
689 },
690 "minq_s8" => Intrinsic {
691 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
692 output: &::I8x16,
693 definition: Named("llvm.neon.vmins.v16i8")
694 },
695 "minq_u8" => Intrinsic {
696 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
697 output: &::U8x16,
698 definition: Named("llvm.neon.vminu.v16i8")
699 },
700 "minq_s16" => Intrinsic {
701 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
702 output: &::I16x8,
703 definition: Named("llvm.neon.vmins.v8i16")
704 },
705 "minq_u16" => Intrinsic {
706 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
707 output: &::U16x8,
708 definition: Named("llvm.neon.vminu.v8i16")
709 },
710 "minq_s32" => Intrinsic {
711 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
712 output: &::I32x4,
713 definition: Named("llvm.neon.vmins.v4i32")
714 },
715 "minq_u32" => Intrinsic {
716 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
717 output: &::U32x4,
718 definition: Named("llvm.neon.vminu.v4i32")
719 },
720 "minq_f32" => Intrinsic {
721 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
722 output: &::F32x4,
723 definition: Named("llvm.neon.vminf.v4f32")
724 },
725 "shl_s8" => Intrinsic {
726 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
727 output: &::I8x8,
728 definition: Named("llvm.neon.vshls.v8i8")
729 },
730 "shl_u8" => Intrinsic {
731 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
732 output: &::U8x8,
733 definition: Named("llvm.neon.vshlu.v8i8")
734 },
735 "shl_s16" => Intrinsic {
736 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
737 output: &::I16x4,
738 definition: Named("llvm.neon.vshls.v4i16")
739 },
740 "shl_u16" => Intrinsic {
741 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
742 output: &::U16x4,
743 definition: Named("llvm.neon.vshlu.v4i16")
744 },
745 "shl_s32" => Intrinsic {
746 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
747 output: &::I32x2,
748 definition: Named("llvm.neon.vshls.v2i32")
749 },
750 "shl_u32" => Intrinsic {
751 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
752 output: &::U32x2,
753 definition: Named("llvm.neon.vshlu.v2i32")
754 },
755 "shl_s64" => Intrinsic {
756 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
757 output: &::I64x1,
758 definition: Named("llvm.neon.vshls.v1i64")
759 },
760 "shl_u64" => Intrinsic {
761 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
762 output: &::U64x1,
763 definition: Named("llvm.neon.vshlu.v1i64")
764 },
765 "shlq_s8" => Intrinsic {
766 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
767 output: &::I8x16,
768 definition: Named("llvm.neon.vshls.v16i8")
769 },
770 "shlq_u8" => Intrinsic {
771 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
772 output: &::U8x16,
773 definition: Named("llvm.neon.vshlu.v16i8")
774 },
775 "shlq_s16" => Intrinsic {
776 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
777 output: &::I16x8,
778 definition: Named("llvm.neon.vshls.v8i16")
779 },
780 "shlq_u16" => Intrinsic {
781 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
782 output: &::U16x8,
783 definition: Named("llvm.neon.vshlu.v8i16")
784 },
785 "shlq_s32" => Intrinsic {
786 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
787 output: &::I32x4,
788 definition: Named("llvm.neon.vshls.v4i32")
789 },
790 "shlq_u32" => Intrinsic {
791 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
792 output: &::U32x4,
793 definition: Named("llvm.neon.vshlu.v4i32")
794 },
795 "shlq_s64" => Intrinsic {
796 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
797 output: &::I64x2,
798 definition: Named("llvm.neon.vshls.v2i64")
799 },
800 "shlq_u64" => Intrinsic {
801 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
802 output: &::U64x2,
803 definition: Named("llvm.neon.vshlu.v2i64")
804 },
805 "qshl_s8" => Intrinsic {
806 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
807 output: &::I8x8,
808 definition: Named("llvm.neon.vqshls.v8i8")
809 },
810 "qshl_u8" => Intrinsic {
811 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
812 output: &::U8x8,
813 definition: Named("llvm.neon.vqshlu.v8i8")
814 },
815 "qshl_s16" => Intrinsic {
816 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
817 output: &::I16x4,
818 definition: Named("llvm.neon.vqshls.v4i16")
819 },
820 "qshl_u16" => Intrinsic {
821 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
822 output: &::U16x4,
823 definition: Named("llvm.neon.vqshlu.v4i16")
824 },
825 "qshl_s32" => Intrinsic {
826 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
827 output: &::I32x2,
828 definition: Named("llvm.neon.vqshls.v2i32")
829 },
830 "qshl_u32" => Intrinsic {
831 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
832 output: &::U32x2,
833 definition: Named("llvm.neon.vqshlu.v2i32")
834 },
835 "qshl_s64" => Intrinsic {
836 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
837 output: &::I64x1,
838 definition: Named("llvm.neon.vqshls.v1i64")
839 },
840 "qshl_u64" => Intrinsic {
841 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
842 output: &::U64x1,
843 definition: Named("llvm.neon.vqshlu.v1i64")
844 },
845 "qshlq_s8" => Intrinsic {
846 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
847 output: &::I8x16,
848 definition: Named("llvm.neon.vqshls.v16i8")
849 },
850 "qshlq_u8" => Intrinsic {
851 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
852 output: &::U8x16,
853 definition: Named("llvm.neon.vqshlu.v16i8")
854 },
855 "qshlq_s16" => Intrinsic {
856 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
857 output: &::I16x8,
858 definition: Named("llvm.neon.vqshls.v8i16")
859 },
860 "qshlq_u16" => Intrinsic {
861 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
862 output: &::U16x8,
863 definition: Named("llvm.neon.vqshlu.v8i16")
864 },
865 "qshlq_s32" => Intrinsic {
866 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
867 output: &::I32x4,
868 definition: Named("llvm.neon.vqshls.v4i32")
869 },
870 "qshlq_u32" => Intrinsic {
871 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
872 output: &::U32x4,
873 definition: Named("llvm.neon.vqshlu.v4i32")
874 },
875 "qshlq_s64" => Intrinsic {
876 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
877 output: &::I64x2,
878 definition: Named("llvm.neon.vqshls.v2i64")
879 },
880 "qshlq_u64" => Intrinsic {
881 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
882 output: &::U64x2,
883 definition: Named("llvm.neon.vqshlu.v2i64")
884 },
885 "rshl_s8" => Intrinsic {
886 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
887 output: &::I8x8,
888 definition: Named("llvm.neon.vrshls.v8i8")
889 },
890 "rshl_u8" => Intrinsic {
891 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
892 output: &::U8x8,
893 definition: Named("llvm.neon.vrshlu.v8i8")
894 },
895 "rshl_s16" => Intrinsic {
896 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
897 output: &::I16x4,
898 definition: Named("llvm.neon.vrshls.v4i16")
899 },
900 "rshl_u16" => Intrinsic {
901 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
902 output: &::U16x4,
903 definition: Named("llvm.neon.vrshlu.v4i16")
904 },
905 "rshl_s32" => Intrinsic {
906 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
907 output: &::I32x2,
908 definition: Named("llvm.neon.vrshls.v2i32")
909 },
910 "rshl_u32" => Intrinsic {
911 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
912 output: &::U32x2,
913 definition: Named("llvm.neon.vrshlu.v2i32")
914 },
915 "rshl_s64" => Intrinsic {
916 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
917 output: &::I64x1,
918 definition: Named("llvm.neon.vrshls.v1i64")
919 },
920 "rshl_u64" => Intrinsic {
921 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
922 output: &::U64x1,
923 definition: Named("llvm.neon.vrshlu.v1i64")
924 },
925 "rshlq_s8" => Intrinsic {
926 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
927 output: &::I8x16,
928 definition: Named("llvm.neon.vrshls.v16i8")
929 },
930 "rshlq_u8" => Intrinsic {
931 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
932 output: &::U8x16,
933 definition: Named("llvm.neon.vrshlu.v16i8")
934 },
935 "rshlq_s16" => Intrinsic {
936 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
937 output: &::I16x8,
938 definition: Named("llvm.neon.vrshls.v8i16")
939 },
940 "rshlq_u16" => Intrinsic {
941 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
942 output: &::U16x8,
943 definition: Named("llvm.neon.vrshlu.v8i16")
944 },
945 "rshlq_s32" => Intrinsic {
946 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
947 output: &::I32x4,
948 definition: Named("llvm.neon.vrshls.v4i32")
949 },
950 "rshlq_u32" => Intrinsic {
951 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
952 output: &::U32x4,
953 definition: Named("llvm.neon.vrshlu.v4i32")
954 },
955 "rshlq_s64" => Intrinsic {
956 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
957 output: &::I64x2,
958 definition: Named("llvm.neon.vrshls.v2i64")
959 },
960 "rshlq_u64" => Intrinsic {
961 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
962 output: &::U64x2,
963 definition: Named("llvm.neon.vrshlu.v2i64")
964 },
965 "qrshl_s8" => Intrinsic {
966 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
967 output: &::I8x8,
968 definition: Named("llvm.neon.vqrshls.v8i8")
969 },
970 "qrshl_u8" => Intrinsic {
971 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
972 output: &::U8x8,
973 definition: Named("llvm.neon.vqrshlu.v8i8")
974 },
975 "qrshl_s16" => Intrinsic {
976 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
977 output: &::I16x4,
978 definition: Named("llvm.neon.vqrshls.v4i16")
979 },
980 "qrshl_u16" => Intrinsic {
981 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
982 output: &::U16x4,
983 definition: Named("llvm.neon.vqrshlu.v4i16")
984 },
985 "qrshl_s32" => Intrinsic {
986 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
987 output: &::I32x2,
988 definition: Named("llvm.neon.vqrshls.v2i32")
989 },
990 "qrshl_u32" => Intrinsic {
991 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
992 output: &::U32x2,
993 definition: Named("llvm.neon.vqrshlu.v2i32")
994 },
995 "qrshl_s64" => Intrinsic {
996 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
997 output: &::I64x1,
998 definition: Named("llvm.neon.vqrshls.v1i64")
999 },
1000 "qrshl_u64" => Intrinsic {
1001 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
1002 output: &::U64x1,
1003 definition: Named("llvm.neon.vqrshlu.v1i64")
1004 },
1005 "qrshlq_s8" => Intrinsic {
1006 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1007 output: &::I8x16,
1008 definition: Named("llvm.neon.vqrshls.v16i8")
1009 },
1010 "qrshlq_u8" => Intrinsic {
1011 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
1012 output: &::U8x16,
1013 definition: Named("llvm.neon.vqrshlu.v16i8")
1014 },
1015 "qrshlq_s16" => Intrinsic {
1016 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1017 output: &::I16x8,
1018 definition: Named("llvm.neon.vqrshls.v8i16")
1019 },
1020 "qrshlq_u16" => Intrinsic {
1021 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
1022 output: &::U16x8,
1023 definition: Named("llvm.neon.vqrshlu.v8i16")
1024 },
1025 "qrshlq_s32" => Intrinsic {
1026 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1027 output: &::I32x4,
1028 definition: Named("llvm.neon.vqrshls.v4i32")
1029 },
1030 "qrshlq_u32" => Intrinsic {
1031 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
1032 output: &::U32x4,
1033 definition: Named("llvm.neon.vqrshlu.v4i32")
1034 },
1035 "qrshlq_s64" => Intrinsic {
1036 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
1037 output: &::I64x2,
1038 definition: Named("llvm.neon.vqrshls.v2i64")
1039 },
1040 "qrshlq_u64" => Intrinsic {
1041 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
1042 output: &::U64x2,
1043 definition: Named("llvm.neon.vqrshlu.v2i64")
1044 },
1045 "qshrun_n_s16" => Intrinsic {
1046 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1047 output: &::I8x8,
1048 definition: Named("llvm.neon.vsqshrun.v8i8")
1049 },
1050 "qshrun_n_s32" => Intrinsic {
1051 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1052 output: &::I16x4,
1053 definition: Named("llvm.neon.vsqshrun.v4i16")
1054 },
1055 "qshrun_n_s64" => Intrinsic {
1056 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1057 output: &::I32x2,
1058 definition: Named("llvm.neon.vsqshrun.v2i32")
1059 },
1060 "qrshrun_n_s16" => Intrinsic {
1061 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1062 output: &::I8x8,
1063 definition: Named("llvm.neon.vsqrshrun.v8i8")
1064 },
1065 "qrshrun_n_s32" => Intrinsic {
1066 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1067 output: &::I16x4,
1068 definition: Named("llvm.neon.vsqrshrun.v4i16")
1069 },
1070 "qrshrun_n_s64" => Intrinsic {
1071 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1072 output: &::I32x2,
1073 definition: Named("llvm.neon.vsqrshrun.v2i32")
1074 },
1075 "qshrn_n_s16" => Intrinsic {
1076 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1077 output: &::I8x8,
1078 definition: Named("llvm.neon.vqshrns.v8i8")
1079 },
1080 "qshrn_n_u16" => Intrinsic {
1081 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS },
1082 output: &::U8x8,
1083 definition: Named("llvm.neon.vqshrnu.v8i8")
1084 },
1085 "qshrn_n_s32" => Intrinsic {
1086 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1087 output: &::I16x4,
1088 definition: Named("llvm.neon.vqshrns.v4i16")
1089 },
1090 "qshrn_n_u32" => Intrinsic {
1091 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS },
1092 output: &::U16x4,
1093 definition: Named("llvm.neon.vqshrnu.v4i16")
1094 },
1095 "qshrn_n_s64" => Intrinsic {
1096 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1097 output: &::I32x2,
1098 definition: Named("llvm.neon.vqshrns.v2i32")
1099 },
1100 "qshrn_n_u64" => Intrinsic {
1101 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS },
1102 output: &::U32x2,
1103 definition: Named("llvm.neon.vqshrnu.v2i32")
1104 },
1105 "rshrn_n_s16" => Intrinsic {
1106 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1107 output: &::I8x8,
1108 definition: Named("llvm.neon.vrshrn.v8i8")
1109 },
1110 "rshrn_n_u16" => Intrinsic {
1111 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS },
1112 output: &::U8x8,
1113 definition: Named("llvm.neon.vrshrn.v8i8")
1114 },
1115 "rshrn_n_s32" => Intrinsic {
1116 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1117 output: &::I16x4,
1118 definition: Named("llvm.neon.vrshrn.v4i16")
1119 },
1120 "rshrn_n_u32" => Intrinsic {
1121 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS },
1122 output: &::U16x4,
1123 definition: Named("llvm.neon.vrshrn.v4i16")
1124 },
1125 "rshrn_n_s64" => Intrinsic {
1126 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1127 output: &::I32x2,
1128 definition: Named("llvm.neon.vrshrn.v2i32")
1129 },
1130 "rshrn_n_u64" => Intrinsic {
1131 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS },
1132 output: &::U32x2,
1133 definition: Named("llvm.neon.vrshrn.v2i32")
1134 },
1135 "qrshrn_n_s16" => Intrinsic {
1136 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS },
1137 output: &::I8x8,
1138 definition: Named("llvm.neon.vqrshrns.v8i8")
1139 },
1140 "qrshrn_n_u16" => Intrinsic {
1141 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS },
1142 output: &::U8x8,
1143 definition: Named("llvm.neon.vqrshrnu.v8i8")
1144 },
1145 "qrshrn_n_s32" => Intrinsic {
1146 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS },
1147 output: &::I16x4,
1148 definition: Named("llvm.neon.vqrshrns.v4i16")
1149 },
1150 "qrshrn_n_u32" => Intrinsic {
1151 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS },
1152 output: &::U16x4,
1153 definition: Named("llvm.neon.vqrshrnu.v4i16")
1154 },
1155 "qrshrn_n_s64" => Intrinsic {
1156 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS },
1157 output: &::I32x2,
1158 definition: Named("llvm.neon.vqrshrns.v2i32")
1159 },
1160 "qrshrn_n_u64" => Intrinsic {
1161 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS },
1162 output: &::U32x2,
1163 definition: Named("llvm.neon.vqrshrnu.v2i32")
1164 },
1165 "sri_s8" => Intrinsic {
1166 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1167 output: &::I8x8,
1168 definition: Named("llvm.neon.vvsri.v8i8")
1169 },
1170 "sri_u8" => Intrinsic {
1171 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1172 output: &::U8x8,
1173 definition: Named("llvm.neon.vvsri.v8i8")
1174 },
1175 "sri_s16" => Intrinsic {
1176 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1177 output: &::I16x4,
1178 definition: Named("llvm.neon.vvsri.v4i16")
1179 },
1180 "sri_u16" => Intrinsic {
1181 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1182 output: &::U16x4,
1183 definition: Named("llvm.neon.vvsri.v4i16")
1184 },
1185 "sri_s32" => Intrinsic {
1186 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1187 output: &::I32x2,
1188 definition: Named("llvm.neon.vvsri.v2i32")
1189 },
1190 "sri_u32" => Intrinsic {
1191 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1192 output: &::U32x2,
1193 definition: Named("llvm.neon.vvsri.v2i32")
1194 },
1195 "sri_s64" => Intrinsic {
1196 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
1197 output: &::I64x1,
1198 definition: Named("llvm.neon.vvsri.v1i64")
1199 },
1200 "sri_u64" => Intrinsic {
1201 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
1202 output: &::U64x1,
1203 definition: Named("llvm.neon.vvsri.v1i64")
1204 },
1205 "sriq_s8" => Intrinsic {
1206 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1207 output: &::I8x16,
1208 definition: Named("llvm.neon.vvsri.v16i8")
1209 },
1210 "sriq_u8" => Intrinsic {
1211 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
1212 output: &::U8x16,
1213 definition: Named("llvm.neon.vvsri.v16i8")
1214 },
1215 "sriq_s16" => Intrinsic {
1216 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1217 output: &::I16x8,
1218 definition: Named("llvm.neon.vvsri.v8i16")
1219 },
1220 "sriq_u16" => Intrinsic {
1221 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
1222 output: &::U16x8,
1223 definition: Named("llvm.neon.vvsri.v8i16")
1224 },
1225 "sriq_s32" => Intrinsic {
1226 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1227 output: &::I32x4,
1228 definition: Named("llvm.neon.vvsri.v4i32")
1229 },
1230 "sriq_u32" => Intrinsic {
1231 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
1232 output: &::U32x4,
1233 definition: Named("llvm.neon.vvsri.v4i32")
1234 },
1235 "sriq_s64" => Intrinsic {
1236 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
1237 output: &::I64x2,
1238 definition: Named("llvm.neon.vvsri.v2i64")
1239 },
1240 "sriq_u64" => Intrinsic {
1241 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
1242 output: &::U64x2,
1243 definition: Named("llvm.neon.vvsri.v2i64")
1244 },
1245 "sli_s8" => Intrinsic {
1246 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1247 output: &::I8x8,
1248 definition: Named("llvm.neon.vvsli.v8i8")
1249 },
1250 "sli_u8" => Intrinsic {
1251 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1252 output: &::U8x8,
1253 definition: Named("llvm.neon.vvsli.v8i8")
1254 },
1255 "sli_s16" => Intrinsic {
1256 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1257 output: &::I16x4,
1258 definition: Named("llvm.neon.vvsli.v4i16")
1259 },
1260 "sli_u16" => Intrinsic {
1261 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1262 output: &::U16x4,
1263 definition: Named("llvm.neon.vvsli.v4i16")
1264 },
1265 "sli_s32" => Intrinsic {
1266 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1267 output: &::I32x2,
1268 definition: Named("llvm.neon.vvsli.v2i32")
1269 },
1270 "sli_u32" => Intrinsic {
1271 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1272 output: &::U32x2,
1273 definition: Named("llvm.neon.vvsli.v2i32")
1274 },
1275 "sli_s64" => Intrinsic {
1276 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS },
1277 output: &::I64x1,
1278 definition: Named("llvm.neon.vvsli.v1i64")
1279 },
1280 "sli_u64" => Intrinsic {
1281 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
1282 output: &::U64x1,
1283 definition: Named("llvm.neon.vvsli.v1i64")
1284 },
1285 "sliq_s8" => Intrinsic {
1286 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1287 output: &::I8x16,
1288 definition: Named("llvm.neon.vvsli.v16i8")
1289 },
1290 "sliq_u8" => Intrinsic {
1291 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
1292 output: &::U8x16,
1293 definition: Named("llvm.neon.vvsli.v16i8")
1294 },
1295 "sliq_s16" => Intrinsic {
1296 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1297 output: &::I16x8,
1298 definition: Named("llvm.neon.vvsli.v8i16")
1299 },
1300 "sliq_u16" => Intrinsic {
1301 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
1302 output: &::U16x8,
1303 definition: Named("llvm.neon.vvsli.v8i16")
1304 },
1305 "sliq_s32" => Intrinsic {
1306 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1307 output: &::I32x4,
1308 definition: Named("llvm.neon.vvsli.v4i32")
1309 },
1310 "sliq_u32" => Intrinsic {
1311 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
1312 output: &::U32x4,
1313 definition: Named("llvm.neon.vvsli.v4i32")
1314 },
1315 "sliq_s64" => Intrinsic {
1316 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS },
1317 output: &::I64x2,
1318 definition: Named("llvm.neon.vvsli.v2i64")
1319 },
1320 "sliq_u64" => Intrinsic {
1321 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
1322 output: &::U64x2,
1323 definition: Named("llvm.neon.vvsli.v2i64")
1324 },
1325 "vqmovn_s16" => Intrinsic {
1326 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1327 output: &::I8x8,
1328 definition: Named("llvm.neon.vqxtns.v8i8")
1329 },
1330 "vqmovn_u16" => Intrinsic {
1331 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
1332 output: &::U8x8,
1333 definition: Named("llvm.neon.vqxtnu.v8i8")
1334 },
1335 "vqmovn_s32" => Intrinsic {
1336 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1337 output: &::I16x4,
1338 definition: Named("llvm.neon.vqxtns.v4i16")
1339 },
1340 "vqmovn_u32" => Intrinsic {
1341 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1342 output: &::U16x4,
1343 definition: Named("llvm.neon.vqxtnu.v4i16")
1344 },
1345 "vqmovn_s64" => Intrinsic {
1346 inputs: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS },
1347 output: &::I32x2,
1348 definition: Named("llvm.neon.vqxtns.v2i32")
1349 },
1350 "vqmovn_u64" => Intrinsic {
1351 inputs: { static INPUTS: [&'static Type; 1] = [&::U64x2]; &INPUTS },
1352 output: &::U32x2,
1353 definition: Named("llvm.neon.vqxtnu.v2i32")
1354 },
1355 "abs_s8" => Intrinsic {
1356 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1357 output: &::I8x8,
1358 definition: Named("llvm.neon.vabs.v8i8")
1359 },
1360 "abs_s16" => Intrinsic {
1361 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1362 output: &::I16x4,
1363 definition: Named("llvm.neon.vabs.v4i16")
1364 },
1365 "abs_s32" => Intrinsic {
1366 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1367 output: &::I32x2,
1368 definition: Named("llvm.neon.vabs.v2i32")
1369 },
1370 "absq_s8" => Intrinsic {
1371 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1372 output: &::I8x16,
1373 definition: Named("llvm.neon.vabs.v16i8")
1374 },
1375 "absq_s16" => Intrinsic {
1376 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1377 output: &::I16x8,
1378 definition: Named("llvm.neon.vabs.v8i16")
1379 },
1380 "absq_s32" => Intrinsic {
1381 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1382 output: &::I32x4,
1383 definition: Named("llvm.neon.vabs.v4i32")
1384 },
1385 "abs_f32" => Intrinsic {
1386 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1387 output: &::F32x2,
1388 definition: Named("llvm.fabs.v2f32")
1389 },
1390 "absq_f32" => Intrinsic {
1391 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1392 output: &::F32x4,
1393 definition: Named("llvm.fabs.v4f32")
1394 },
1395 "qabs_s8" => Intrinsic {
1396 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1397 output: &::I8x8,
1398 definition: Named("llvm.neon.vsqabs.v8i8")
1399 },
1400 "qabs_s16" => Intrinsic {
1401 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1402 output: &::I16x4,
1403 definition: Named("llvm.neon.vsqabs.v4i16")
1404 },
1405 "qabs_s32" => Intrinsic {
1406 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1407 output: &::I32x2,
1408 definition: Named("llvm.neon.vsqabs.v2i32")
1409 },
1410 "qabsq_s8" => Intrinsic {
1411 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1412 output: &::I8x16,
1413 definition: Named("llvm.neon.vsqabs.v16i8")
1414 },
1415 "qabsq_s16" => Intrinsic {
1416 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1417 output: &::I16x8,
1418 definition: Named("llvm.neon.vsqabs.v8i16")
1419 },
1420 "qabsq_s32" => Intrinsic {
1421 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1422 output: &::I32x4,
1423 definition: Named("llvm.neon.vsqabs.v4i32")
1424 },
1425 "qneg_s8" => Intrinsic {
1426 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1427 output: &::I8x8,
1428 definition: Named("llvm.neon.vsqneg.v8i8")
1429 },
1430 "qneg_s16" => Intrinsic {
1431 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1432 output: &::I16x4,
1433 definition: Named("llvm.neon.vsqneg.v4i16")
1434 },
1435 "qneg_s32" => Intrinsic {
1436 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1437 output: &::I32x2,
1438 definition: Named("llvm.neon.vsqneg.v2i32")
1439 },
1440 "qnegq_s8" => Intrinsic {
1441 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1442 output: &::I8x16,
1443 definition: Named("llvm.neon.vsqneg.v16i8")
1444 },
1445 "qnegq_s16" => Intrinsic {
1446 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1447 output: &::I16x8,
1448 definition: Named("llvm.neon.vsqneg.v8i16")
1449 },
1450 "qnegq_s32" => Intrinsic {
1451 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1452 output: &::I32x4,
1453 definition: Named("llvm.neon.vsqneg.v4i32")
1454 },
1455 "clz_s8" => Intrinsic {
1456 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1457 output: &::I8x8,
1458 definition: Named("llvm.ctlz.v8i8")
1459 },
1460 "clz_u8" => Intrinsic {
1461 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1462 output: &::U8x8,
1463 definition: Named("llvm.ctlz.v8i8")
1464 },
1465 "clz_s16" => Intrinsic {
1466 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1467 output: &::I16x4,
1468 definition: Named("llvm.ctlz.v4i16")
1469 },
1470 "clz_u16" => Intrinsic {
1471 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
1472 output: &::U16x4,
1473 definition: Named("llvm.ctlz.v4i16")
1474 },
1475 "clz_s32" => Intrinsic {
1476 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1477 output: &::I32x2,
1478 definition: Named("llvm.ctlz.v2i32")
1479 },
1480 "clz_u32" => Intrinsic {
1481 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1482 output: &::U32x2,
1483 definition: Named("llvm.ctlz.v2i32")
1484 },
1485 "clzq_s8" => Intrinsic {
1486 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1487 output: &::I8x16,
1488 definition: Named("llvm.ctlz.v16i8")
1489 },
1490 "clzq_u8" => Intrinsic {
1491 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1492 output: &::U8x16,
1493 definition: Named("llvm.ctlz.v16i8")
1494 },
1495 "clzq_s16" => Intrinsic {
1496 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1497 output: &::I16x8,
1498 definition: Named("llvm.ctlz.v8i16")
1499 },
1500 "clzq_u16" => Intrinsic {
1501 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
1502 output: &::U16x8,
1503 definition: Named("llvm.ctlz.v8i16")
1504 },
1505 "clzq_s32" => Intrinsic {
1506 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1507 output: &::I32x4,
1508 definition: Named("llvm.ctlz.v4i32")
1509 },
1510 "clzq_u32" => Intrinsic {
1511 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1512 output: &::U32x4,
1513 definition: Named("llvm.ctlz.v4i32")
1514 },
1515 "cls_s8" => Intrinsic {
1516 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1517 output: &::I8x8,
1518 definition: Named("llvm.neon.vcls.v8i8")
1519 },
1520 "cls_u8" => Intrinsic {
1521 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1522 output: &::U8x8,
1523 definition: Named("llvm.neon.vcls.v8i8")
1524 },
1525 "cls_s16" => Intrinsic {
1526 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1527 output: &::I16x4,
1528 definition: Named("llvm.neon.vcls.v4i16")
1529 },
1530 "cls_u16" => Intrinsic {
1531 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
1532 output: &::U16x4,
1533 definition: Named("llvm.neon.vcls.v4i16")
1534 },
1535 "cls_s32" => Intrinsic {
1536 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1537 output: &::I32x2,
1538 definition: Named("llvm.neon.vcls.v2i32")
1539 },
1540 "cls_u32" => Intrinsic {
1541 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1542 output: &::U32x2,
1543 definition: Named("llvm.neon.vcls.v2i32")
1544 },
1545 "clsq_s8" => Intrinsic {
1546 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1547 output: &::I8x16,
1548 definition: Named("llvm.neon.vcls.v16i8")
1549 },
1550 "clsq_u8" => Intrinsic {
1551 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1552 output: &::U8x16,
1553 definition: Named("llvm.neon.vcls.v16i8")
1554 },
1555 "clsq_s16" => Intrinsic {
1556 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1557 output: &::I16x8,
1558 definition: Named("llvm.neon.vcls.v8i16")
1559 },
1560 "clsq_u16" => Intrinsic {
1561 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
1562 output: &::U16x8,
1563 definition: Named("llvm.neon.vcls.v8i16")
1564 },
1565 "clsq_s32" => Intrinsic {
1566 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1567 output: &::I32x4,
1568 definition: Named("llvm.neon.vcls.v4i32")
1569 },
1570 "clsq_u32" => Intrinsic {
1571 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1572 output: &::U32x4,
1573 definition: Named("llvm.neon.vcls.v4i32")
1574 },
1575 "cnt_s8" => Intrinsic {
1576 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1577 output: &::I8x8,
1578 definition: Named("llvm.ctpop.v8i8")
1579 },
1580 "cnt_u8" => Intrinsic {
1581 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1582 output: &::U8x8,
1583 definition: Named("llvm.ctpop.v8i8")
1584 },
1585 "cntq_s8" => Intrinsic {
1586 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1587 output: &::I8x16,
1588 definition: Named("llvm.ctpop.v16i8")
1589 },
1590 "cntq_u8" => Intrinsic {
1591 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1592 output: &::U8x16,
1593 definition: Named("llvm.ctpop.v16i8")
1594 },
1595 "recpe_u32" => Intrinsic {
1596 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1597 output: &::U32x2,
1598 definition: Named("llvm.neon.vrecpe.v2i32")
1599 },
1600 "recpe_f32" => Intrinsic {
1601 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1602 output: &::F32x2,
1603 definition: Named("llvm.neon.vrecpe.v2f32")
1604 },
1605 "recpeq_u32" => Intrinsic {
1606 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1607 output: &::U32x4,
1608 definition: Named("llvm.neon.vrecpe.v4i32")
1609 },
1610 "recpeq_f32" => Intrinsic {
1611 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1612 output: &::F32x4,
1613 definition: Named("llvm.neon.vrecpe.v4f32")
1614 },
1615 "recps_f32" => Intrinsic {
1616 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
1617 output: &::F32x2,
1618 definition: Named("llvm.neon.vfrecps.v2f32")
1619 },
1620 "recpsq_f32" => Intrinsic {
1621 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
1622 output: &::F32x4,
1623 definition: Named("llvm.neon.vfrecps.v4f32")
1624 },
1625 "sqrt_f32" => Intrinsic {
1626 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1627 output: &::F32x2,
1628 definition: Named("llvm.sqrt.v2f32")
1629 },
1630 "sqrtq_f32" => Intrinsic {
1631 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1632 output: &::F32x4,
1633 definition: Named("llvm.sqrt.v4f32")
1634 },
1635 "rsqrte_u32" => Intrinsic {
1636 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1637 output: &::U32x2,
1638 definition: Named("llvm.neon.vrsqrte.v2i32")
1639 },
1640 "rsqrte_f32" => Intrinsic {
1641 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS },
1642 output: &::F32x2,
1643 definition: Named("llvm.neon.vrsqrte.v2f32")
1644 },
1645 "rsqrteq_u32" => Intrinsic {
1646 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1647 output: &::U32x4,
1648 definition: Named("llvm.neon.vrsqrte.v4i32")
1649 },
1650 "rsqrteq_f32" => Intrinsic {
1651 inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
1652 output: &::F32x4,
1653 definition: Named("llvm.neon.vrsqrte.v4f32")
1654 },
1655 "rsqrts_f32" => Intrinsic {
1656 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
1657 output: &::F32x2,
1658 definition: Named("llvm.neon.vrsqrts.v2f32")
1659 },
1660 "rsqrtsq_f32" => Intrinsic {
1661 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
1662 output: &::F32x4,
1663 definition: Named("llvm.neon.vrsqrts.v4f32")
1664 },
1665 "bsl_s8" => Intrinsic {
1666 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS },
1667 output: &::I8x8,
1668 definition: Named("llvm.neon.vbsl.v8i8")
1669 },
1670 "bsl_u8" => Intrinsic {
1671 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1672 output: &::U8x8,
1673 definition: Named("llvm.neon.vbsl.v8i8")
1674 },
1675 "bsl_s16" => Intrinsic {
1676 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS },
1677 output: &::I16x4,
1678 definition: Named("llvm.neon.vbsl.v4i16")
1679 },
1680 "bsl_u16" => Intrinsic {
1681 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1682 output: &::U16x4,
1683 definition: Named("llvm.neon.vbsl.v4i16")
1684 },
1685 "bsl_s32" => Intrinsic {
1686 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS },
1687 output: &::I32x2,
1688 definition: Named("llvm.neon.vbsl.v2i32")
1689 },
1690 "bsl_u32" => Intrinsic {
1691 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1692 output: &::U32x2,
1693 definition: Named("llvm.neon.vbsl.v2i32")
1694 },
1695 "bsl_s64" => Intrinsic {
1696 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS },
1697 output: &::I64x1,
1698 definition: Named("llvm.neon.vbsl.v1i64")
1699 },
1700 "bsl_u64" => Intrinsic {
1701 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS },
1702 output: &::U64x1,
1703 definition: Named("llvm.neon.vbsl.v1i64")
1704 },
1705 "bslq_s8" => Intrinsic {
1706 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS },
1707 output: &::I8x16,
1708 definition: Named("llvm.neon.vbsl.v16i8")
1709 },
1710 "bslq_u8" => Intrinsic {
1711 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
1712 output: &::U8x16,
1713 definition: Named("llvm.neon.vbsl.v16i8")
1714 },
1715 "bslq_s16" => Intrinsic {
1716 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS },
1717 output: &::I16x8,
1718 definition: Named("llvm.neon.vbsl.v8i16")
1719 },
1720 "bslq_u16" => Intrinsic {
1721 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
1722 output: &::U16x8,
1723 definition: Named("llvm.neon.vbsl.v8i16")
1724 },
1725 "bslq_s32" => Intrinsic {
1726 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS },
1727 output: &::I32x4,
1728 definition: Named("llvm.neon.vbsl.v4i32")
1729 },
1730 "bslq_u32" => Intrinsic {
1731 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
1732 output: &::U32x4,
1733 definition: Named("llvm.neon.vbsl.v4i32")
1734 },
1735 "bslq_s64" => Intrinsic {
1736 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS },
1737 output: &::I64x2,
1738 definition: Named("llvm.neon.vbsl.v2i64")
1739 },
1740 "bslq_u64" => Intrinsic {
1741 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS },
1742 output: &::U64x2,
1743 definition: Named("llvm.neon.vbsl.v2i64")
1744 },
1745 "padd_s8" => Intrinsic {
1746 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1747 output: &::I8x8,
1748 definition: Named("llvm.neon.vpadd.v8i8")
1749 },
1750 "padd_u8" => Intrinsic {
1751 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1752 output: &::U8x8,
1753 definition: Named("llvm.neon.vpadd.v8i8")
1754 },
1755 "padd_s16" => Intrinsic {
1756 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1757 output: &::I16x4,
1758 definition: Named("llvm.neon.vpadd.v4i16")
1759 },
1760 "padd_u16" => Intrinsic {
1761 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1762 output: &::U16x4,
1763 definition: Named("llvm.neon.vpadd.v4i16")
1764 },
1765 "padd_s32" => Intrinsic {
1766 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1767 output: &::I32x2,
1768 definition: Named("llvm.neon.vpadd.v2i32")
1769 },
1770 "padd_u32" => Intrinsic {
1771 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1772 output: &::U32x2,
1773 definition: Named("llvm.neon.vpadd.v2i32")
1774 },
1775 "padd_f32" => Intrinsic {
1776 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
1777 output: &::F32x2,
1778 definition: Named("llvm.neon.vpadd.v2f32")
1779 },
1780 "paddl_s16" => Intrinsic {
1781 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS },
1782 output: &::I16x4,
1783 definition: Named("llvm.neon.vpaddls.v4i16.v8i8")
1784 },
1785 "paddl_u16" => Intrinsic {
1786 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS },
1787 output: &::U16x4,
1788 definition: Named("llvm.neon.vpaddlu.v4i16.v8i8")
1789 },
1790 "paddl_s32" => Intrinsic {
1791 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS },
1792 output: &::I32x2,
1793 definition: Named("llvm.neon.vpaddls.v2i32.v4i16")
1794 },
1795 "paddl_u32" => Intrinsic {
1796 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS },
1797 output: &::U32x2,
1798 definition: Named("llvm.neon.vpaddlu.v2i32.v4i16")
1799 },
1800 "paddl_s64" => Intrinsic {
1801 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS },
1802 output: &::I64x1,
1803 definition: Named("llvm.neon.vpaddls.v1i64.v2i32")
1804 },
1805 "paddl_u64" => Intrinsic {
1806 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS },
1807 output: &::U64x1,
1808 definition: Named("llvm.neon.vpaddlu.v1i64.v2i32")
1809 },
1810 "paddlq_s16" => Intrinsic {
1811 inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS },
1812 output: &::I16x8,
1813 definition: Named("llvm.neon.vpaddls.v8i16.v16i8")
1814 },
1815 "paddlq_u16" => Intrinsic {
1816 inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS },
1817 output: &::U16x8,
1818 definition: Named("llvm.neon.vpaddlu.v8i16.v16i8")
1819 },
1820 "paddlq_s32" => Intrinsic {
1821 inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS },
1822 output: &::I32x4,
1823 definition: Named("llvm.neon.vpaddls.v4i32.v8i16")
1824 },
1825 "paddlq_u32" => Intrinsic {
1826 inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS },
1827 output: &::U32x4,
1828 definition: Named("llvm.neon.vpaddlu.v4i32.v8i16")
1829 },
1830 "paddlq_s64" => Intrinsic {
1831 inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS },
1832 output: &::I64x2,
1833 definition: Named("llvm.neon.vpaddls.v2i64.v4i32")
1834 },
1835 "paddlq_u64" => Intrinsic {
1836 inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS },
1837 output: &::U64x2,
1838 definition: Named("llvm.neon.vpaddlu.v2i64.v4i32")
1839 },
1840 "padal_s16" => Intrinsic {
1841 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I8x8]; &INPUTS },
1842 output: &::I16x4,
1843 definition: Named("llvm.neon.vpadals.v4i16.v4i16")
1844 },
1845 "padal_u16" => Intrinsic {
1846 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U8x8]; &INPUTS },
1847 output: &::U16x4,
1848 definition: Named("llvm.neon.vpadalu.v4i16.v4i16")
1849 },
1850 "padal_s32" => Intrinsic {
1851 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I16x4]; &INPUTS },
1852 output: &::I32x2,
1853 definition: Named("llvm.neon.vpadals.v2i32.v2i32")
1854 },
1855 "padal_u32" => Intrinsic {
1856 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U16x4]; &INPUTS },
1857 output: &::U32x2,
1858 definition: Named("llvm.neon.vpadalu.v2i32.v2i32")
1859 },
1860 "padal_s64" => Intrinsic {
1861 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I32x2]; &INPUTS },
1862 output: &::I64x1,
1863 definition: Named("llvm.neon.vpadals.v1i64.v1i64")
1864 },
1865 "padal_u64" => Intrinsic {
1866 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U32x2]; &INPUTS },
1867 output: &::U64x1,
1868 definition: Named("llvm.neon.vpadalu.v1i64.v1i64")
1869 },
1870 "padalq_s16" => Intrinsic {
1871 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I8x16]; &INPUTS },
1872 output: &::I16x8,
1873 definition: Named("llvm.neon.vpadals.v8i16.v8i16")
1874 },
1875 "padalq_u16" => Intrinsic {
1876 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U8x16]; &INPUTS },
1877 output: &::U16x8,
1878 definition: Named("llvm.neon.vpadalu.v8i16.v8i16")
1879 },
1880 "padalq_s32" => Intrinsic {
1881 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I16x8]; &INPUTS },
1882 output: &::I32x4,
1883 definition: Named("llvm.neon.vpadals.v4i32.v4i32")
1884 },
1885 "padalq_u32" => Intrinsic {
1886 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U16x8]; &INPUTS },
1887 output: &::U32x4,
1888 definition: Named("llvm.neon.vpadalu.v4i32.v4i32")
1889 },
1890 "padalq_s64" => Intrinsic {
1891 inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I32x4]; &INPUTS },
1892 output: &::I64x2,
1893 definition: Named("llvm.neon.vpadals.v2i64.v2i64")
1894 },
1895 "padalq_u64" => Intrinsic {
1896 inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32x4]; &INPUTS },
1897 output: &::U64x2,
1898 definition: Named("llvm.neon.vpadalu.v2i64.v2i64")
1899 },
1900 "pmax_s8" => Intrinsic {
1901 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1902 output: &::I8x8,
1903 definition: Named("llvm.neon.vpmaxs.v8i8")
1904 },
1905 "pmax_u8" => Intrinsic {
1906 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1907 output: &::U8x8,
1908 definition: Named("llvm.neon.vpmaxu.v8i8")
1909 },
1910 "pmax_s16" => Intrinsic {
1911 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1912 output: &::I16x4,
1913 definition: Named("llvm.neon.vpmaxs.v4i16")
1914 },
1915 "pmax_u16" => Intrinsic {
1916 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1917 output: &::U16x4,
1918 definition: Named("llvm.neon.vpmaxu.v4i16")
1919 },
1920 "pmax_s32" => Intrinsic {
1921 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1922 output: &::I32x2,
1923 definition: Named("llvm.neon.vpmaxs.v2i32")
1924 },
1925 "pmax_u32" => Intrinsic {
1926 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1927 output: &::U32x2,
1928 definition: Named("llvm.neon.vpmaxu.v2i32")
1929 },
1930 "pmax_f32" => Intrinsic {
1931 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
1932 output: &::F32x2,
1933 definition: Named("llvm.neon.vpmaxf.v2f32")
1934 },
1935 "pmin_s8" => Intrinsic {
1936 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS },
1937 output: &::I8x8,
1938 definition: Named("llvm.neon.vpmins.v8i8")
1939 },
1940 "pmin_u8" => Intrinsic {
1941 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
1942 output: &::U8x8,
1943 definition: Named("llvm.neon.vpminu.v8i8")
1944 },
1945 "pmin_s16" => Intrinsic {
1946 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS },
1947 output: &::I16x4,
1948 definition: Named("llvm.neon.vpmins.v4i16")
1949 },
1950 "pmin_u16" => Intrinsic {
1951 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS },
1952 output: &::U16x4,
1953 definition: Named("llvm.neon.vpminu.v4i16")
1954 },
1955 "pmin_s32" => Intrinsic {
1956 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS },
1957 output: &::I32x2,
1958 definition: Named("llvm.neon.vpmins.v2i32")
1959 },
1960 "pmin_u32" => Intrinsic {
1961 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS },
1962 output: &::U32x2,
1963 definition: Named("llvm.neon.vpminu.v2i32")
1964 },
1965 "pmin_f32" => Intrinsic {
1966 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS },
1967 output: &::F32x2,
1968 definition: Named("llvm.neon.vpminf.v2f32")
1969 },
1970 "pminq_s8" => Intrinsic {
1971 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
1972 output: &::I8x16,
1973 definition: Named("llvm.neon.vpmins.v16i8")
1974 },
1975 "pminq_u8" => Intrinsic {
1976 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
1977 output: &::U8x16,
1978 definition: Named("llvm.neon.vpminu.v16i8")
1979 },
1980 "pminq_s16" => Intrinsic {
1981 inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
1982 output: &::I16x8,
1983 definition: Named("llvm.neon.vpmins.v8i16")
1984 },
1985 "pminq_u16" => Intrinsic {
1986 inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
1987 output: &::U16x8,
1988 definition: Named("llvm.neon.vpminu.v8i16")
1989 },
1990 "pminq_s32" => Intrinsic {
1991 inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
1992 output: &::I32x4,
1993 definition: Named("llvm.neon.vpmins.v4i32")
1994 },
1995 "pminq_u32" => Intrinsic {
1996 inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
1997 output: &::U32x4,
1998 definition: Named("llvm.neon.vpminu.v4i32")
1999 },
2000 "pminq_f32" => Intrinsic {
2001 inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
2002 output: &::F32x4,
2003 definition: Named("llvm.neon.vpminf.v4f32")
2004 },
2005 "tbl1_s8" => Intrinsic {
2006 inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::U8x8]; &INPUTS },
2007 output: &::I8x8,
2008 definition: Named("llvm.neon.vtbl1")
2009 },
2010 "tbl1_u8" => Intrinsic {
2011 inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS },
2012 output: &::U8x8,
2013 definition: Named("llvm.neon.vtbl1")
2014 },
2015 "tbx1_s8" => Intrinsic {
2016 inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::U8x8]; &INPUTS },
2017 output: &::I8x8,
2018 definition: Named("llvm.neon.vtbx1")
2019 },
2020 "tbx1_u8" => Intrinsic {
2021 inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &INPUTS },
2022 output: &::U8x8,
2023 definition: Named("llvm.neon.vtbx1")
2024 },
2025 "tbl2_s8" => Intrinsic {
2026 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2027 output: &::I8x8,
2028 definition: Named("llvm.neon.vtbl2")
2029 },
2030 "tbl2_u8" => Intrinsic {
2031 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2032 output: &::U8x8,
2033 definition: Named("llvm.neon.vtbl2")
2034 },
2035 "tbx2_s8" => Intrinsic {
2036 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2037 output: &::I8x8,
2038 definition: Named("llvm.neon.vtbx2")
2039 },
2040 "tbx2_u8" => Intrinsic {
2041 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2042 output: &::U8x8,
2043 definition: Named("llvm.neon.vtbx2")
2044 },
2045 "tbl3_s8" => Intrinsic {
2046 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2047 output: &::I8x8,
2048 definition: Named("llvm.neon.vtbl3")
2049 },
2050 "tbl3_u8" => Intrinsic {
2051 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2052 output: &::U8x8,
2053 definition: Named("llvm.neon.vtbl3")
2054 },
2055 "tbx3_s8" => Intrinsic {
2056 inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2057 output: &::I8x8,
2058 definition: Named("llvm.neon.vtbx3")
2059 },
2060 "tbx3_u8" => Intrinsic {
2061 inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2062 output: &::U8x8,
2063 definition: Named("llvm.neon.vtbx3")
2064 },
2065 "tbl4_s8" => Intrinsic {
2066 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x8, &::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2067 output: &::I8x8,
2068 definition: Named("llvm.neon.vtbl4")
2069 },
2070 "tbl4_u8" => Intrinsic {
2071 inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x8, &::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2072 output: &::U8x8,
2073 definition: Named("llvm.neon.vtbl4")
2074 },
2075 "tbx4_s8" => Intrinsic {
2076 inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x8, &::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2077 output: &::I8x8,
2078 definition: Named("llvm.neon.vtbx4")
2079 },
2080 "tbx4_u8" => Intrinsic {
2081 inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x8, &::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS },
2082 output: &::U8x8,
2083 definition: Named("llvm.neon.vtbx4")
2084 },
2085 _ => return None,
2086 })
2087 }
backport for Debian buster