1 // Copyright 2015 The Rust Project Developers. See the COPYRIGHT
2 // file at the top-level directory of this distribution and at
3 // http://rust-lang.org/COPYRIGHT.
5 // Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
6 // http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
7 // <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
8 // option. This file may not be copied, modified, or distributed
9 // except according to those terms.
11 // DO NOT EDIT: autogenerated by etc/platform-intrinsics/generator.py
12 // ignore-tidy-linelength
14 #![allow(unused_imports)]
16 use {Intrinsic, Type}
;
17 use IntrinsicDef
::Named
;
19 // The default inlining settings trigger a pathological behaviour in
20 // LLVM, which causes makes compilation very slow. See #28273.
22 pub fn find(name
: &str) -> Option
<Intrinsic
> {
23 if !name
.starts_with("arm_v") { return None }
24 Some(match &name
["arm_v".len()..] {
25 "hadd_s8" => Intrinsic
{
26 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
28 definition
: Named("llvm.neon.vhadds.v8i8")
30 "hadd_u8" => Intrinsic
{
31 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
33 definition
: Named("llvm.neon.vhaddu.v8i8")
35 "hadd_s16" => Intrinsic
{
36 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
38 definition
: Named("llvm.neon.vhadds.v4i16")
40 "hadd_u16" => Intrinsic
{
41 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
43 definition
: Named("llvm.neon.vhaddu.v4i16")
45 "hadd_s32" => Intrinsic
{
46 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
48 definition
: Named("llvm.neon.vhadds.v2i32")
50 "hadd_u32" => Intrinsic
{
51 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
53 definition
: Named("llvm.neon.vhaddu.v2i32")
55 "haddq_s8" => Intrinsic
{
56 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
58 definition
: Named("llvm.neon.vhadds.v16i8")
60 "haddq_u8" => Intrinsic
{
61 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
63 definition
: Named("llvm.neon.vhaddu.v16i8")
65 "haddq_s16" => Intrinsic
{
66 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
68 definition
: Named("llvm.neon.vhadds.v8i16")
70 "haddq_u16" => Intrinsic
{
71 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
73 definition
: Named("llvm.neon.vhaddu.v8i16")
75 "haddq_s32" => Intrinsic
{
76 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
78 definition
: Named("llvm.neon.vhadds.v4i32")
80 "haddq_u32" => Intrinsic
{
81 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
83 definition
: Named("llvm.neon.vhaddu.v4i32")
85 "rhadd_s8" => Intrinsic
{
86 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
88 definition
: Named("llvm.neon.vrhadds.v8i8")
90 "rhadd_u8" => Intrinsic
{
91 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
93 definition
: Named("llvm.neon.vrhaddu.v8i8")
95 "rhadd_s16" => Intrinsic
{
96 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
98 definition
: Named("llvm.neon.vrhadds.v4i16")
100 "rhadd_u16" => Intrinsic
{
101 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
103 definition
: Named("llvm.neon.vrhaddu.v4i16")
105 "rhadd_s32" => Intrinsic
{
106 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
108 definition
: Named("llvm.neon.vrhadds.v2i32")
110 "rhadd_u32" => Intrinsic
{
111 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
113 definition
: Named("llvm.neon.vrhaddu.v2i32")
115 "rhaddq_s8" => Intrinsic
{
116 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
118 definition
: Named("llvm.neon.vrhadds.v16i8")
120 "rhaddq_u8" => Intrinsic
{
121 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
123 definition
: Named("llvm.neon.vrhaddu.v16i8")
125 "rhaddq_s16" => Intrinsic
{
126 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
128 definition
: Named("llvm.neon.vrhadds.v8i16")
130 "rhaddq_u16" => Intrinsic
{
131 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
133 definition
: Named("llvm.neon.vrhaddu.v8i16")
135 "rhaddq_s32" => Intrinsic
{
136 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
138 definition
: Named("llvm.neon.vrhadds.v4i32")
140 "rhaddq_u32" => Intrinsic
{
141 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
143 definition
: Named("llvm.neon.vrhaddu.v4i32")
145 "qadd_s8" => Intrinsic
{
146 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
148 definition
: Named("llvm.neon.vqadds.v8i8")
150 "qadd_u8" => Intrinsic
{
151 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
153 definition
: Named("llvm.neon.vqaddu.v8i8")
155 "qadd_s16" => Intrinsic
{
156 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
158 definition
: Named("llvm.neon.vqadds.v4i16")
160 "qadd_u16" => Intrinsic
{
161 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
163 definition
: Named("llvm.neon.vqaddu.v4i16")
165 "qadd_s32" => Intrinsic
{
166 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
168 definition
: Named("llvm.neon.vqadds.v2i32")
170 "qadd_u32" => Intrinsic
{
171 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
173 definition
: Named("llvm.neon.vqaddu.v2i32")
175 "qadd_s64" => Intrinsic
{
176 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }
,
178 definition
: Named("llvm.neon.vqadds.v1i64")
180 "qadd_u64" => Intrinsic
{
181 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS }
,
183 definition
: Named("llvm.neon.vqaddu.v1i64")
185 "qaddq_s8" => Intrinsic
{
186 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
188 definition
: Named("llvm.neon.vqadds.v16i8")
190 "qaddq_u8" => Intrinsic
{
191 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
193 definition
: Named("llvm.neon.vqaddu.v16i8")
195 "qaddq_s16" => Intrinsic
{
196 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
198 definition
: Named("llvm.neon.vqadds.v8i16")
200 "qaddq_u16" => Intrinsic
{
201 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
203 definition
: Named("llvm.neon.vqaddu.v8i16")
205 "qaddq_s32" => Intrinsic
{
206 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
208 definition
: Named("llvm.neon.vqadds.v4i32")
210 "qaddq_u32" => Intrinsic
{
211 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
213 definition
: Named("llvm.neon.vqaddu.v4i32")
215 "qaddq_s64" => Intrinsic
{
216 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
218 definition
: Named("llvm.neon.vqadds.v2i64")
220 "qaddq_u64" => Intrinsic
{
221 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }
,
223 definition
: Named("llvm.neon.vqaddu.v2i64")
225 "raddhn_s16" => Intrinsic
{
226 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
228 definition
: Named("llvm.neon.vraddhn.v8i8")
230 "raddhn_u16" => Intrinsic
{
231 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
233 definition
: Named("llvm.neon.vraddhn.v8i8")
235 "raddhn_s32" => Intrinsic
{
236 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
238 definition
: Named("llvm.neon.vraddhn.v4i16")
240 "raddhn_u32" => Intrinsic
{
241 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
243 definition
: Named("llvm.neon.vraddhn.v4i16")
245 "raddhn_s64" => Intrinsic
{
246 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
248 definition
: Named("llvm.neon.vraddhn.v2i32")
250 "raddhn_u64" => Intrinsic
{
251 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }
,
253 definition
: Named("llvm.neon.vraddhn.v2i32")
255 "fma_f32" => Intrinsic
{
256 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
258 definition
: Named("llvm.fma.v2f32")
260 "fmaq_f32" => Intrinsic
{
261 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
263 definition
: Named("llvm.fma.v4f32")
265 "qdmulh_s16" => Intrinsic
{
266 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
268 definition
: Named("llvm.neon.vsqdmulh.v4i16")
270 "qdmulh_s32" => Intrinsic
{
271 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
273 definition
: Named("llvm.neon.vsqdmulh.v2i32")
275 "qdmulhq_s16" => Intrinsic
{
276 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
278 definition
: Named("llvm.neon.vsqdmulh.v8i16")
280 "qdmulhq_s32" => Intrinsic
{
281 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
283 definition
: Named("llvm.neon.vsqdmulh.v4i32")
285 "qrdmulh_s16" => Intrinsic
{
286 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
288 definition
: Named("llvm.neon.vsqrdmulh.v4i16")
290 "qrdmulh_s32" => Intrinsic
{
291 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
293 definition
: Named("llvm.neon.vsqrdmulh.v2i32")
295 "qrdmulhq_s16" => Intrinsic
{
296 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
298 definition
: Named("llvm.neon.vsqrdmulh.v8i16")
300 "qrdmulhq_s32" => Intrinsic
{
301 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
303 definition
: Named("llvm.neon.vsqrdmulh.v4i32")
305 "mull_s8" => Intrinsic
{
306 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
308 definition
: Named("llvm.neon.vmulls.v8i16")
310 "mull_u8" => Intrinsic
{
311 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
313 definition
: Named("llvm.neon.vmullu.v8i16")
315 "mull_s16" => Intrinsic
{
316 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
318 definition
: Named("llvm.neon.vmulls.v4i32")
320 "mull_u16" => Intrinsic
{
321 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
323 definition
: Named("llvm.neon.vmullu.v4i32")
325 "mull_s32" => Intrinsic
{
326 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
328 definition
: Named("llvm.neon.vmulls.v2i64")
330 "mull_u32" => Intrinsic
{
331 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
333 definition
: Named("llvm.neon.vmullu.v2i64")
335 "qdmullq_s8" => Intrinsic
{
336 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
338 definition
: Named("llvm.neon.vsqdmull.v8i16")
340 "qdmullq_s16" => Intrinsic
{
341 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
343 definition
: Named("llvm.neon.vsqdmull.v4i32")
345 "hsub_s8" => Intrinsic
{
346 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
348 definition
: Named("llvm.neon.vhsubs.v8i8")
350 "hsub_u8" => Intrinsic
{
351 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
353 definition
: Named("llvm.neon.vhsubu.v8i8")
355 "hsub_s16" => Intrinsic
{
356 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
358 definition
: Named("llvm.neon.vhsubs.v4i16")
360 "hsub_u16" => Intrinsic
{
361 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
363 definition
: Named("llvm.neon.vhsubu.v4i16")
365 "hsub_s32" => Intrinsic
{
366 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
368 definition
: Named("llvm.neon.vhsubs.v2i32")
370 "hsub_u32" => Intrinsic
{
371 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
373 definition
: Named("llvm.neon.vhsubu.v2i32")
375 "hsubq_s8" => Intrinsic
{
376 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
378 definition
: Named("llvm.neon.vhsubs.v16i8")
380 "hsubq_u8" => Intrinsic
{
381 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
383 definition
: Named("llvm.neon.vhsubu.v16i8")
385 "hsubq_s16" => Intrinsic
{
386 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
388 definition
: Named("llvm.neon.vhsubs.v8i16")
390 "hsubq_u16" => Intrinsic
{
391 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
393 definition
: Named("llvm.neon.vhsubu.v8i16")
395 "hsubq_s32" => Intrinsic
{
396 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
398 definition
: Named("llvm.neon.vhsubs.v4i32")
400 "hsubq_u32" => Intrinsic
{
401 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
403 definition
: Named("llvm.neon.vhsubu.v4i32")
405 "qsub_s8" => Intrinsic
{
406 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
408 definition
: Named("llvm.neon.vqsubs.v8i8")
410 "qsub_u8" => Intrinsic
{
411 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
413 definition
: Named("llvm.neon.vqsubu.v8i8")
415 "qsub_s16" => Intrinsic
{
416 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
418 definition
: Named("llvm.neon.vqsubs.v4i16")
420 "qsub_u16" => Intrinsic
{
421 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
423 definition
: Named("llvm.neon.vqsubu.v4i16")
425 "qsub_s32" => Intrinsic
{
426 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
428 definition
: Named("llvm.neon.vqsubs.v2i32")
430 "qsub_u32" => Intrinsic
{
431 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
433 definition
: Named("llvm.neon.vqsubu.v2i32")
435 "qsub_s64" => Intrinsic
{
436 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }
,
438 definition
: Named("llvm.neon.vqsubs.v1i64")
440 "qsub_u64" => Intrinsic
{
441 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS }
,
443 definition
: Named("llvm.neon.vqsubu.v1i64")
445 "qsubq_s8" => Intrinsic
{
446 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
448 definition
: Named("llvm.neon.vqsubs.v16i8")
450 "qsubq_u8" => Intrinsic
{
451 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
453 definition
: Named("llvm.neon.vqsubu.v16i8")
455 "qsubq_s16" => Intrinsic
{
456 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
458 definition
: Named("llvm.neon.vqsubs.v8i16")
460 "qsubq_u16" => Intrinsic
{
461 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
463 definition
: Named("llvm.neon.vqsubu.v8i16")
465 "qsubq_s32" => Intrinsic
{
466 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
468 definition
: Named("llvm.neon.vqsubs.v4i32")
470 "qsubq_u32" => Intrinsic
{
471 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
473 definition
: Named("llvm.neon.vqsubu.v4i32")
475 "qsubq_s64" => Intrinsic
{
476 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
478 definition
: Named("llvm.neon.vqsubs.v2i64")
480 "qsubq_u64" => Intrinsic
{
481 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }
,
483 definition
: Named("llvm.neon.vqsubu.v2i64")
485 "rsubhn_s16" => Intrinsic
{
486 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
488 definition
: Named("llvm.neon.vrsubhn.v8i8")
490 "rsubhn_u16" => Intrinsic
{
491 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
493 definition
: Named("llvm.neon.vrsubhn.v8i8")
495 "rsubhn_s32" => Intrinsic
{
496 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
498 definition
: Named("llvm.neon.vrsubhn.v4i16")
500 "rsubhn_u32" => Intrinsic
{
501 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
503 definition
: Named("llvm.neon.vrsubhn.v4i16")
505 "rsubhn_s64" => Intrinsic
{
506 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
508 definition
: Named("llvm.neon.vrsubhn.v2i32")
510 "rsubhn_u64" => Intrinsic
{
511 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }
,
513 definition
: Named("llvm.neon.vrsubhn.v2i32")
515 "abd_s8" => Intrinsic
{
516 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
518 definition
: Named("llvm.neon.vabds.v8i8")
520 "abd_u8" => Intrinsic
{
521 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
523 definition
: Named("llvm.neon.vabdu.v8i8")
525 "abd_s16" => Intrinsic
{
526 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
528 definition
: Named("llvm.neon.vabds.v4i16")
530 "abd_u16" => Intrinsic
{
531 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
533 definition
: Named("llvm.neon.vabdu.v4i16")
535 "abd_s32" => Intrinsic
{
536 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
538 definition
: Named("llvm.neon.vabds.v2i32")
540 "abd_u32" => Intrinsic
{
541 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
543 definition
: Named("llvm.neon.vabdu.v2i32")
545 "abd_f32" => Intrinsic
{
546 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
548 definition
: Named("llvm.neon.vabdf.v2f32")
550 "abdq_s8" => Intrinsic
{
551 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
553 definition
: Named("llvm.neon.vabds.v16i8")
555 "abdq_u8" => Intrinsic
{
556 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
558 definition
: Named("llvm.neon.vabdu.v16i8")
560 "abdq_s16" => Intrinsic
{
561 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
563 definition
: Named("llvm.neon.vabds.v8i16")
565 "abdq_u16" => Intrinsic
{
566 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
568 definition
: Named("llvm.neon.vabdu.v8i16")
570 "abdq_s32" => Intrinsic
{
571 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
573 definition
: Named("llvm.neon.vabds.v4i32")
575 "abdq_u32" => Intrinsic
{
576 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
578 definition
: Named("llvm.neon.vabdu.v4i32")
580 "abdq_f32" => Intrinsic
{
581 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
583 definition
: Named("llvm.neon.vabdf.v4f32")
585 "max_s8" => Intrinsic
{
586 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
588 definition
: Named("llvm.neon.vmaxs.v8i8")
590 "max_u8" => Intrinsic
{
591 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
593 definition
: Named("llvm.neon.vmaxu.v8i8")
595 "max_s16" => Intrinsic
{
596 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
598 definition
: Named("llvm.neon.vmaxs.v4i16")
600 "max_u16" => Intrinsic
{
601 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
603 definition
: Named("llvm.neon.vmaxu.v4i16")
605 "max_s32" => Intrinsic
{
606 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
608 definition
: Named("llvm.neon.vmaxs.v2i32")
610 "max_u32" => Intrinsic
{
611 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
613 definition
: Named("llvm.neon.vmaxu.v2i32")
615 "max_f32" => Intrinsic
{
616 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
618 definition
: Named("llvm.neon.vmaxf.v2f32")
620 "maxq_s8" => Intrinsic
{
621 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
623 definition
: Named("llvm.neon.vmaxs.v16i8")
625 "maxq_u8" => Intrinsic
{
626 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
628 definition
: Named("llvm.neon.vmaxu.v16i8")
630 "maxq_s16" => Intrinsic
{
631 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
633 definition
: Named("llvm.neon.vmaxs.v8i16")
635 "maxq_u16" => Intrinsic
{
636 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
638 definition
: Named("llvm.neon.vmaxu.v8i16")
640 "maxq_s32" => Intrinsic
{
641 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
643 definition
: Named("llvm.neon.vmaxs.v4i32")
645 "maxq_u32" => Intrinsic
{
646 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
648 definition
: Named("llvm.neon.vmaxu.v4i32")
650 "maxq_f32" => Intrinsic
{
651 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
653 definition
: Named("llvm.neon.vmaxf.v4f32")
655 "min_s8" => Intrinsic
{
656 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
658 definition
: Named("llvm.neon.vmins.v8i8")
660 "min_u8" => Intrinsic
{
661 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
663 definition
: Named("llvm.neon.vminu.v8i8")
665 "min_s16" => Intrinsic
{
666 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
668 definition
: Named("llvm.neon.vmins.v4i16")
670 "min_u16" => Intrinsic
{
671 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
673 definition
: Named("llvm.neon.vminu.v4i16")
675 "min_s32" => Intrinsic
{
676 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
678 definition
: Named("llvm.neon.vmins.v2i32")
680 "min_u32" => Intrinsic
{
681 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
683 definition
: Named("llvm.neon.vminu.v2i32")
685 "min_f32" => Intrinsic
{
686 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
688 definition
: Named("llvm.neon.vminf.v2f32")
690 "minq_s8" => Intrinsic
{
691 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
693 definition
: Named("llvm.neon.vmins.v16i8")
695 "minq_u8" => Intrinsic
{
696 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
698 definition
: Named("llvm.neon.vminu.v16i8")
700 "minq_s16" => Intrinsic
{
701 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
703 definition
: Named("llvm.neon.vmins.v8i16")
705 "minq_u16" => Intrinsic
{
706 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
708 definition
: Named("llvm.neon.vminu.v8i16")
710 "minq_s32" => Intrinsic
{
711 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
713 definition
: Named("llvm.neon.vmins.v4i32")
715 "minq_u32" => Intrinsic
{
716 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
718 definition
: Named("llvm.neon.vminu.v4i32")
720 "minq_f32" => Intrinsic
{
721 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
723 definition
: Named("llvm.neon.vminf.v4f32")
725 "shl_s8" => Intrinsic
{
726 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
728 definition
: Named("llvm.neon.vshls.v8i8")
730 "shl_u8" => Intrinsic
{
731 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS }
,
733 definition
: Named("llvm.neon.vshlu.v8i8")
735 "shl_s16" => Intrinsic
{
736 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
738 definition
: Named("llvm.neon.vshls.v4i16")
740 "shl_u16" => Intrinsic
{
741 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS }
,
743 definition
: Named("llvm.neon.vshlu.v4i16")
745 "shl_s32" => Intrinsic
{
746 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
748 definition
: Named("llvm.neon.vshls.v2i32")
750 "shl_u32" => Intrinsic
{
751 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS }
,
753 definition
: Named("llvm.neon.vshlu.v2i32")
755 "shl_s64" => Intrinsic
{
756 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }
,
758 definition
: Named("llvm.neon.vshls.v1i64")
760 "shl_u64" => Intrinsic
{
761 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS }
,
763 definition
: Named("llvm.neon.vshlu.v1i64")
765 "shlq_s8" => Intrinsic
{
766 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
768 definition
: Named("llvm.neon.vshls.v16i8")
770 "shlq_u8" => Intrinsic
{
771 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }
,
773 definition
: Named("llvm.neon.vshlu.v16i8")
775 "shlq_s16" => Intrinsic
{
776 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
778 definition
: Named("llvm.neon.vshls.v8i16")
780 "shlq_u16" => Intrinsic
{
781 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }
,
783 definition
: Named("llvm.neon.vshlu.v8i16")
785 "shlq_s32" => Intrinsic
{
786 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
788 definition
: Named("llvm.neon.vshls.v4i32")
790 "shlq_u32" => Intrinsic
{
791 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }
,
793 definition
: Named("llvm.neon.vshlu.v4i32")
795 "shlq_s64" => Intrinsic
{
796 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
798 definition
: Named("llvm.neon.vshls.v2i64")
800 "shlq_u64" => Intrinsic
{
801 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }
,
803 definition
: Named("llvm.neon.vshlu.v2i64")
805 "qshl_s8" => Intrinsic
{
806 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
808 definition
: Named("llvm.neon.vqshls.v8i8")
810 "qshl_u8" => Intrinsic
{
811 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS }
,
813 definition
: Named("llvm.neon.vqshlu.v8i8")
815 "qshl_s16" => Intrinsic
{
816 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
818 definition
: Named("llvm.neon.vqshls.v4i16")
820 "qshl_u16" => Intrinsic
{
821 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS }
,
823 definition
: Named("llvm.neon.vqshlu.v4i16")
825 "qshl_s32" => Intrinsic
{
826 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
828 definition
: Named("llvm.neon.vqshls.v2i32")
830 "qshl_u32" => Intrinsic
{
831 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS }
,
833 definition
: Named("llvm.neon.vqshlu.v2i32")
835 "qshl_s64" => Intrinsic
{
836 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }
,
838 definition
: Named("llvm.neon.vqshls.v1i64")
840 "qshl_u64" => Intrinsic
{
841 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS }
,
843 definition
: Named("llvm.neon.vqshlu.v1i64")
845 "qshlq_s8" => Intrinsic
{
846 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
848 definition
: Named("llvm.neon.vqshls.v16i8")
850 "qshlq_u8" => Intrinsic
{
851 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }
,
853 definition
: Named("llvm.neon.vqshlu.v16i8")
855 "qshlq_s16" => Intrinsic
{
856 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
858 definition
: Named("llvm.neon.vqshls.v8i16")
860 "qshlq_u16" => Intrinsic
{
861 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }
,
863 definition
: Named("llvm.neon.vqshlu.v8i16")
865 "qshlq_s32" => Intrinsic
{
866 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
868 definition
: Named("llvm.neon.vqshls.v4i32")
870 "qshlq_u32" => Intrinsic
{
871 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }
,
873 definition
: Named("llvm.neon.vqshlu.v4i32")
875 "qshlq_s64" => Intrinsic
{
876 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
878 definition
: Named("llvm.neon.vqshls.v2i64")
880 "qshlq_u64" => Intrinsic
{
881 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }
,
883 definition
: Named("llvm.neon.vqshlu.v2i64")
885 "rshl_s8" => Intrinsic
{
886 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
888 definition
: Named("llvm.neon.vrshls.v8i8")
890 "rshl_u8" => Intrinsic
{
891 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS }
,
893 definition
: Named("llvm.neon.vrshlu.v8i8")
895 "rshl_s16" => Intrinsic
{
896 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
898 definition
: Named("llvm.neon.vrshls.v4i16")
900 "rshl_u16" => Intrinsic
{
901 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS }
,
903 definition
: Named("llvm.neon.vrshlu.v4i16")
905 "rshl_s32" => Intrinsic
{
906 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
908 definition
: Named("llvm.neon.vrshls.v2i32")
910 "rshl_u32" => Intrinsic
{
911 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS }
,
913 definition
: Named("llvm.neon.vrshlu.v2i32")
915 "rshl_s64" => Intrinsic
{
916 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }
,
918 definition
: Named("llvm.neon.vrshls.v1i64")
920 "rshl_u64" => Intrinsic
{
921 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS }
,
923 definition
: Named("llvm.neon.vrshlu.v1i64")
925 "rshlq_s8" => Intrinsic
{
926 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
928 definition
: Named("llvm.neon.vrshls.v16i8")
930 "rshlq_u8" => Intrinsic
{
931 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }
,
933 definition
: Named("llvm.neon.vrshlu.v16i8")
935 "rshlq_s16" => Intrinsic
{
936 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
938 definition
: Named("llvm.neon.vrshls.v8i16")
940 "rshlq_u16" => Intrinsic
{
941 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }
,
943 definition
: Named("llvm.neon.vrshlu.v8i16")
945 "rshlq_s32" => Intrinsic
{
946 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
948 definition
: Named("llvm.neon.vrshls.v4i32")
950 "rshlq_u32" => Intrinsic
{
951 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }
,
953 definition
: Named("llvm.neon.vrshlu.v4i32")
955 "rshlq_s64" => Intrinsic
{
956 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
958 definition
: Named("llvm.neon.vrshls.v2i64")
960 "rshlq_u64" => Intrinsic
{
961 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }
,
963 definition
: Named("llvm.neon.vrshlu.v2i64")
965 "qrshl_s8" => Intrinsic
{
966 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
968 definition
: Named("llvm.neon.vqrshls.v8i8")
970 "qrshl_u8" => Intrinsic
{
971 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS }
,
973 definition
: Named("llvm.neon.vqrshlu.v8i8")
975 "qrshl_s16" => Intrinsic
{
976 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
978 definition
: Named("llvm.neon.vqrshls.v4i16")
980 "qrshl_u16" => Intrinsic
{
981 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS }
,
983 definition
: Named("llvm.neon.vqrshlu.v4i16")
985 "qrshl_s32" => Intrinsic
{
986 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
988 definition
: Named("llvm.neon.vqrshls.v2i32")
990 "qrshl_u32" => Intrinsic
{
991 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS }
,
993 definition
: Named("llvm.neon.vqrshlu.v2i32")
995 "qrshl_s64" => Intrinsic
{
996 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }
,
998 definition
: Named("llvm.neon.vqrshls.v1i64")
1000 "qrshl_u64" => Intrinsic
{
1001 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS }
,
1003 definition
: Named("llvm.neon.vqrshlu.v1i64")
1005 "qrshlq_s8" => Intrinsic
{
1006 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
1008 definition
: Named("llvm.neon.vqrshls.v16i8")
1010 "qrshlq_u8" => Intrinsic
{
1011 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }
,
1013 definition
: Named("llvm.neon.vqrshlu.v16i8")
1015 "qrshlq_s16" => Intrinsic
{
1016 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
1018 definition
: Named("llvm.neon.vqrshls.v8i16")
1020 "qrshlq_u16" => Intrinsic
{
1021 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }
,
1023 definition
: Named("llvm.neon.vqrshlu.v8i16")
1025 "qrshlq_s32" => Intrinsic
{
1026 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
1028 definition
: Named("llvm.neon.vqrshls.v4i32")
1030 "qrshlq_u32" => Intrinsic
{
1031 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }
,
1033 definition
: Named("llvm.neon.vqrshlu.v4i32")
1035 "qrshlq_s64" => Intrinsic
{
1036 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
1038 definition
: Named("llvm.neon.vqrshls.v2i64")
1040 "qrshlq_u64" => Intrinsic
{
1041 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }
,
1043 definition
: Named("llvm.neon.vqrshlu.v2i64")
1045 "qshrun_n_s16" => Intrinsic
{
1046 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }
,
1048 definition
: Named("llvm.neon.vsqshrun.v8i8")
1050 "qshrun_n_s32" => Intrinsic
{
1051 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }
,
1053 definition
: Named("llvm.neon.vsqshrun.v4i16")
1055 "qshrun_n_s64" => Intrinsic
{
1056 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }
,
1058 definition
: Named("llvm.neon.vsqshrun.v2i32")
1060 "qrshrun_n_s16" => Intrinsic
{
1061 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }
,
1063 definition
: Named("llvm.neon.vsqrshrun.v8i8")
1065 "qrshrun_n_s32" => Intrinsic
{
1066 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }
,
1068 definition
: Named("llvm.neon.vsqrshrun.v4i16")
1070 "qrshrun_n_s64" => Intrinsic
{
1071 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }
,
1073 definition
: Named("llvm.neon.vsqrshrun.v2i32")
1075 "qshrn_n_s16" => Intrinsic
{
1076 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }
,
1078 definition
: Named("llvm.neon.vqshrns.v8i8")
1080 "qshrn_n_u16" => Intrinsic
{
1081 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS }
,
1083 definition
: Named("llvm.neon.vqshrnu.v8i8")
1085 "qshrn_n_s32" => Intrinsic
{
1086 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }
,
1088 definition
: Named("llvm.neon.vqshrns.v4i16")
1090 "qshrn_n_u32" => Intrinsic
{
1091 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS }
,
1093 definition
: Named("llvm.neon.vqshrnu.v4i16")
1095 "qshrn_n_s64" => Intrinsic
{
1096 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }
,
1098 definition
: Named("llvm.neon.vqshrns.v2i32")
1100 "qshrn_n_u64" => Intrinsic
{
1101 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS }
,
1103 definition
: Named("llvm.neon.vqshrnu.v2i32")
1105 "rshrn_n_s16" => Intrinsic
{
1106 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }
,
1108 definition
: Named("llvm.neon.vrshrn.v8i8")
1110 "rshrn_n_u16" => Intrinsic
{
1111 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS }
,
1113 definition
: Named("llvm.neon.vrshrn.v8i8")
1115 "rshrn_n_s32" => Intrinsic
{
1116 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }
,
1118 definition
: Named("llvm.neon.vrshrn.v4i16")
1120 "rshrn_n_u32" => Intrinsic
{
1121 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS }
,
1123 definition
: Named("llvm.neon.vrshrn.v4i16")
1125 "rshrn_n_s64" => Intrinsic
{
1126 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }
,
1128 definition
: Named("llvm.neon.vrshrn.v2i32")
1130 "rshrn_n_u64" => Intrinsic
{
1131 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS }
,
1133 definition
: Named("llvm.neon.vrshrn.v2i32")
1135 "qrshrn_n_s16" => Intrinsic
{
1136 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }
,
1138 definition
: Named("llvm.neon.vqrshrns.v8i8")
1140 "qrshrn_n_u16" => Intrinsic
{
1141 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS }
,
1143 definition
: Named("llvm.neon.vqrshrnu.v8i8")
1145 "qrshrn_n_s32" => Intrinsic
{
1146 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }
,
1148 definition
: Named("llvm.neon.vqrshrns.v4i16")
1150 "qrshrn_n_u32" => Intrinsic
{
1151 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS }
,
1153 definition
: Named("llvm.neon.vqrshrnu.v4i16")
1155 "qrshrn_n_s64" => Intrinsic
{
1156 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }
,
1158 definition
: Named("llvm.neon.vqrshrns.v2i32")
1160 "qrshrn_n_u64" => Intrinsic
{
1161 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS }
,
1163 definition
: Named("llvm.neon.vqrshrnu.v2i32")
1165 "sri_s8" => Intrinsic
{
1166 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
1168 definition
: Named("llvm.neon.vvsri.v8i8")
1170 "sri_u8" => Intrinsic
{
1171 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
1173 definition
: Named("llvm.neon.vvsri.v8i8")
1175 "sri_s16" => Intrinsic
{
1176 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
1178 definition
: Named("llvm.neon.vvsri.v4i16")
1180 "sri_u16" => Intrinsic
{
1181 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
1183 definition
: Named("llvm.neon.vvsri.v4i16")
1185 "sri_s32" => Intrinsic
{
1186 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
1188 definition
: Named("llvm.neon.vvsri.v2i32")
1190 "sri_u32" => Intrinsic
{
1191 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
1193 definition
: Named("llvm.neon.vvsri.v2i32")
1195 "sri_s64" => Intrinsic
{
1196 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }
,
1198 definition
: Named("llvm.neon.vvsri.v1i64")
1200 "sri_u64" => Intrinsic
{
1201 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS }
,
1203 definition
: Named("llvm.neon.vvsri.v1i64")
1205 "sriq_s8" => Intrinsic
{
1206 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
1208 definition
: Named("llvm.neon.vvsri.v16i8")
1210 "sriq_u8" => Intrinsic
{
1211 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
1213 definition
: Named("llvm.neon.vvsri.v16i8")
1215 "sriq_s16" => Intrinsic
{
1216 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
1218 definition
: Named("llvm.neon.vvsri.v8i16")
1220 "sriq_u16" => Intrinsic
{
1221 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
1223 definition
: Named("llvm.neon.vvsri.v8i16")
1225 "sriq_s32" => Intrinsic
{
1226 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
1228 definition
: Named("llvm.neon.vvsri.v4i32")
1230 "sriq_u32" => Intrinsic
{
1231 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
1233 definition
: Named("llvm.neon.vvsri.v4i32")
1235 "sriq_s64" => Intrinsic
{
1236 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
1238 definition
: Named("llvm.neon.vvsri.v2i64")
1240 "sriq_u64" => Intrinsic
{
1241 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }
,
1243 definition
: Named("llvm.neon.vvsri.v2i64")
1245 "sli_s8" => Intrinsic
{
1246 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
1248 definition
: Named("llvm.neon.vvsli.v8i8")
1250 "sli_u8" => Intrinsic
{
1251 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
1253 definition
: Named("llvm.neon.vvsli.v8i8")
1255 "sli_s16" => Intrinsic
{
1256 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
1258 definition
: Named("llvm.neon.vvsli.v4i16")
1260 "sli_u16" => Intrinsic
{
1261 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
1263 definition
: Named("llvm.neon.vvsli.v4i16")
1265 "sli_s32" => Intrinsic
{
1266 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
1268 definition
: Named("llvm.neon.vvsli.v2i32")
1270 "sli_u32" => Intrinsic
{
1271 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
1273 definition
: Named("llvm.neon.vvsli.v2i32")
1275 "sli_s64" => Intrinsic
{
1276 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }
,
1278 definition
: Named("llvm.neon.vvsli.v1i64")
1280 "sli_u64" => Intrinsic
{
1281 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS }
,
1283 definition
: Named("llvm.neon.vvsli.v1i64")
1285 "sliq_s8" => Intrinsic
{
1286 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
1288 definition
: Named("llvm.neon.vvsli.v16i8")
1290 "sliq_u8" => Intrinsic
{
1291 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
1293 definition
: Named("llvm.neon.vvsli.v16i8")
1295 "sliq_s16" => Intrinsic
{
1296 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
1298 definition
: Named("llvm.neon.vvsli.v8i16")
1300 "sliq_u16" => Intrinsic
{
1301 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
1303 definition
: Named("llvm.neon.vvsli.v8i16")
1305 "sliq_s32" => Intrinsic
{
1306 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
1308 definition
: Named("llvm.neon.vvsli.v4i32")
1310 "sliq_u32" => Intrinsic
{
1311 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
1313 definition
: Named("llvm.neon.vvsli.v4i32")
1315 "sliq_s64" => Intrinsic
{
1316 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }
,
1318 definition
: Named("llvm.neon.vvsli.v2i64")
1320 "sliq_u64" => Intrinsic
{
1321 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }
,
1323 definition
: Named("llvm.neon.vvsli.v2i64")
1325 "vqmovn_s16" => Intrinsic
{
1326 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }
,
1328 definition
: Named("llvm.neon.vqxtns.v8i8")
1330 "vqmovn_u16" => Intrinsic
{
1331 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }
,
1333 definition
: Named("llvm.neon.vqxtnu.v8i8")
1335 "vqmovn_s32" => Intrinsic
{
1336 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }
,
1338 definition
: Named("llvm.neon.vqxtns.v4i16")
1340 "vqmovn_u32" => Intrinsic
{
1341 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }
,
1343 definition
: Named("llvm.neon.vqxtnu.v4i16")
1345 "vqmovn_s64" => Intrinsic
{
1346 inputs
: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS }
,
1348 definition
: Named("llvm.neon.vqxtns.v2i32")
1350 "vqmovn_u64" => Intrinsic
{
1351 inputs
: { static INPUTS: [&'static Type; 1] = [&::U64x2]; &INPUTS }
,
1353 definition
: Named("llvm.neon.vqxtnu.v2i32")
1355 "abs_s8" => Intrinsic
{
1356 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }
,
1358 definition
: Named("llvm.neon.vabs.v8i8")
1360 "abs_s16" => Intrinsic
{
1361 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }
,
1363 definition
: Named("llvm.neon.vabs.v4i16")
1365 "abs_s32" => Intrinsic
{
1366 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }
,
1368 definition
: Named("llvm.neon.vabs.v2i32")
1370 "absq_s8" => Intrinsic
{
1371 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }
,
1373 definition
: Named("llvm.neon.vabs.v16i8")
1375 "absq_s16" => Intrinsic
{
1376 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }
,
1378 definition
: Named("llvm.neon.vabs.v8i16")
1380 "absq_s32" => Intrinsic
{
1381 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }
,
1383 definition
: Named("llvm.neon.vabs.v4i32")
1385 "abs_f32" => Intrinsic
{
1386 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }
,
1388 definition
: Named("llvm.fabs.v2f32")
1390 "absq_f32" => Intrinsic
{
1391 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }
,
1393 definition
: Named("llvm.fabs.v4f32")
1395 "qabs_s8" => Intrinsic
{
1396 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }
,
1398 definition
: Named("llvm.neon.vsqabs.v8i8")
1400 "qabs_s16" => Intrinsic
{
1401 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }
,
1403 definition
: Named("llvm.neon.vsqabs.v4i16")
1405 "qabs_s32" => Intrinsic
{
1406 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }
,
1408 definition
: Named("llvm.neon.vsqabs.v2i32")
1410 "qabsq_s8" => Intrinsic
{
1411 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }
,
1413 definition
: Named("llvm.neon.vsqabs.v16i8")
1415 "qabsq_s16" => Intrinsic
{
1416 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }
,
1418 definition
: Named("llvm.neon.vsqabs.v8i16")
1420 "qabsq_s32" => Intrinsic
{
1421 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }
,
1423 definition
: Named("llvm.neon.vsqabs.v4i32")
1425 "qneg_s8" => Intrinsic
{
1426 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }
,
1428 definition
: Named("llvm.neon.vsqneg.v8i8")
1430 "qneg_s16" => Intrinsic
{
1431 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }
,
1433 definition
: Named("llvm.neon.vsqneg.v4i16")
1435 "qneg_s32" => Intrinsic
{
1436 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }
,
1438 definition
: Named("llvm.neon.vsqneg.v2i32")
1440 "qnegq_s8" => Intrinsic
{
1441 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }
,
1443 definition
: Named("llvm.neon.vsqneg.v16i8")
1445 "qnegq_s16" => Intrinsic
{
1446 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }
,
1448 definition
: Named("llvm.neon.vsqneg.v8i16")
1450 "qnegq_s32" => Intrinsic
{
1451 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }
,
1453 definition
: Named("llvm.neon.vsqneg.v4i32")
1455 "clz_s8" => Intrinsic
{
1456 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }
,
1458 definition
: Named("llvm.ctlz.v8i8")
1460 "clz_u8" => Intrinsic
{
1461 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }
,
1463 definition
: Named("llvm.ctlz.v8i8")
1465 "clz_s16" => Intrinsic
{
1466 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }
,
1468 definition
: Named("llvm.ctlz.v4i16")
1470 "clz_u16" => Intrinsic
{
1471 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }
,
1473 definition
: Named("llvm.ctlz.v4i16")
1475 "clz_s32" => Intrinsic
{
1476 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }
,
1478 definition
: Named("llvm.ctlz.v2i32")
1480 "clz_u32" => Intrinsic
{
1481 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }
,
1483 definition
: Named("llvm.ctlz.v2i32")
1485 "clzq_s8" => Intrinsic
{
1486 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }
,
1488 definition
: Named("llvm.ctlz.v16i8")
1490 "clzq_u8" => Intrinsic
{
1491 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }
,
1493 definition
: Named("llvm.ctlz.v16i8")
1495 "clzq_s16" => Intrinsic
{
1496 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }
,
1498 definition
: Named("llvm.ctlz.v8i16")
1500 "clzq_u16" => Intrinsic
{
1501 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }
,
1503 definition
: Named("llvm.ctlz.v8i16")
1505 "clzq_s32" => Intrinsic
{
1506 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }
,
1508 definition
: Named("llvm.ctlz.v4i32")
1510 "clzq_u32" => Intrinsic
{
1511 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }
,
1513 definition
: Named("llvm.ctlz.v4i32")
1515 "cls_s8" => Intrinsic
{
1516 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }
,
1518 definition
: Named("llvm.neon.vcls.v8i8")
1520 "cls_u8" => Intrinsic
{
1521 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }
,
1523 definition
: Named("llvm.neon.vcls.v8i8")
1525 "cls_s16" => Intrinsic
{
1526 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }
,
1528 definition
: Named("llvm.neon.vcls.v4i16")
1530 "cls_u16" => Intrinsic
{
1531 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }
,
1533 definition
: Named("llvm.neon.vcls.v4i16")
1535 "cls_s32" => Intrinsic
{
1536 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }
,
1538 definition
: Named("llvm.neon.vcls.v2i32")
1540 "cls_u32" => Intrinsic
{
1541 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }
,
1543 definition
: Named("llvm.neon.vcls.v2i32")
1545 "clsq_s8" => Intrinsic
{
1546 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }
,
1548 definition
: Named("llvm.neon.vcls.v16i8")
1550 "clsq_u8" => Intrinsic
{
1551 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }
,
1553 definition
: Named("llvm.neon.vcls.v16i8")
1555 "clsq_s16" => Intrinsic
{
1556 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }
,
1558 definition
: Named("llvm.neon.vcls.v8i16")
1560 "clsq_u16" => Intrinsic
{
1561 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }
,
1563 definition
: Named("llvm.neon.vcls.v8i16")
1565 "clsq_s32" => Intrinsic
{
1566 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }
,
1568 definition
: Named("llvm.neon.vcls.v4i32")
1570 "clsq_u32" => Intrinsic
{
1571 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }
,
1573 definition
: Named("llvm.neon.vcls.v4i32")
1575 "cnt_s8" => Intrinsic
{
1576 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }
,
1578 definition
: Named("llvm.ctpop.v8i8")
1580 "cnt_u8" => Intrinsic
{
1581 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }
,
1583 definition
: Named("llvm.ctpop.v8i8")
1585 "cntq_s8" => Intrinsic
{
1586 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }
,
1588 definition
: Named("llvm.ctpop.v16i8")
1590 "cntq_u8" => Intrinsic
{
1591 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }
,
1593 definition
: Named("llvm.ctpop.v16i8")
1595 "recpe_u32" => Intrinsic
{
1596 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }
,
1598 definition
: Named("llvm.neon.vrecpe.v2i32")
1600 "recpe_f32" => Intrinsic
{
1601 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }
,
1603 definition
: Named("llvm.neon.vrecpe.v2f32")
1605 "recpeq_u32" => Intrinsic
{
1606 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }
,
1608 definition
: Named("llvm.neon.vrecpe.v4i32")
1610 "recpeq_f32" => Intrinsic
{
1611 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }
,
1613 definition
: Named("llvm.neon.vrecpe.v4f32")
1615 "recps_f32" => Intrinsic
{
1616 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
1618 definition
: Named("llvm.neon.vfrecps.v2f32")
1620 "recpsq_f32" => Intrinsic
{
1621 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
1623 definition
: Named("llvm.neon.vfrecps.v4f32")
1625 "sqrt_f32" => Intrinsic
{
1626 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }
,
1628 definition
: Named("llvm.sqrt.v2f32")
1630 "sqrtq_f32" => Intrinsic
{
1631 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }
,
1633 definition
: Named("llvm.sqrt.v4f32")
1635 "rsqrte_u32" => Intrinsic
{
1636 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }
,
1638 definition
: Named("llvm.neon.vrsqrte.v2i32")
1640 "rsqrte_f32" => Intrinsic
{
1641 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }
,
1643 definition
: Named("llvm.neon.vrsqrte.v2f32")
1645 "rsqrteq_u32" => Intrinsic
{
1646 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }
,
1648 definition
: Named("llvm.neon.vrsqrte.v4i32")
1650 "rsqrteq_f32" => Intrinsic
{
1651 inputs
: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }
,
1653 definition
: Named("llvm.neon.vrsqrte.v4f32")
1655 "rsqrts_f32" => Intrinsic
{
1656 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
1658 definition
: Named("llvm.neon.vrsqrts.v2f32")
1660 "rsqrtsq_f32" => Intrinsic
{
1661 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
1663 definition
: Named("llvm.neon.vrsqrts.v4f32")
1665 "bsl_s8" => Intrinsic
{
1666 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS }
,
1668 definition
: Named("llvm.neon.vbsl.v8i8")
1670 "bsl_u8" => Intrinsic
{
1671 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
1673 definition
: Named("llvm.neon.vbsl.v8i8")
1675 "bsl_s16" => Intrinsic
{
1676 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS }
,
1678 definition
: Named("llvm.neon.vbsl.v4i16")
1680 "bsl_u16" => Intrinsic
{
1681 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
1683 definition
: Named("llvm.neon.vbsl.v4i16")
1685 "bsl_s32" => Intrinsic
{
1686 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS }
,
1688 definition
: Named("llvm.neon.vbsl.v2i32")
1690 "bsl_u32" => Intrinsic
{
1691 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
1693 definition
: Named("llvm.neon.vbsl.v2i32")
1695 "bsl_s64" => Intrinsic
{
1696 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS }
,
1698 definition
: Named("llvm.neon.vbsl.v1i64")
1700 "bsl_u64" => Intrinsic
{
1701 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS }
,
1703 definition
: Named("llvm.neon.vbsl.v1i64")
1705 "bslq_s8" => Intrinsic
{
1706 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }
,
1708 definition
: Named("llvm.neon.vbsl.v16i8")
1710 "bslq_u8" => Intrinsic
{
1711 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
1713 definition
: Named("llvm.neon.vbsl.v16i8")
1715 "bslq_s16" => Intrinsic
{
1716 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }
,
1718 definition
: Named("llvm.neon.vbsl.v8i16")
1720 "bslq_u16" => Intrinsic
{
1721 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
1723 definition
: Named("llvm.neon.vbsl.v8i16")
1725 "bslq_s32" => Intrinsic
{
1726 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }
,
1728 definition
: Named("llvm.neon.vbsl.v4i32")
1730 "bslq_u32" => Intrinsic
{
1731 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
1733 definition
: Named("llvm.neon.vbsl.v4i32")
1735 "bslq_s64" => Intrinsic
{
1736 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }
,
1738 definition
: Named("llvm.neon.vbsl.v2i64")
1740 "bslq_u64" => Intrinsic
{
1741 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }
,
1743 definition
: Named("llvm.neon.vbsl.v2i64")
1745 "padd_s8" => Intrinsic
{
1746 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
1748 definition
: Named("llvm.neon.vpadd.v8i8")
1750 "padd_u8" => Intrinsic
{
1751 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
1753 definition
: Named("llvm.neon.vpadd.v8i8")
1755 "padd_s16" => Intrinsic
{
1756 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
1758 definition
: Named("llvm.neon.vpadd.v4i16")
1760 "padd_u16" => Intrinsic
{
1761 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
1763 definition
: Named("llvm.neon.vpadd.v4i16")
1765 "padd_s32" => Intrinsic
{
1766 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
1768 definition
: Named("llvm.neon.vpadd.v2i32")
1770 "padd_u32" => Intrinsic
{
1771 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
1773 definition
: Named("llvm.neon.vpadd.v2i32")
1775 "padd_f32" => Intrinsic
{
1776 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
1778 definition
: Named("llvm.neon.vpadd.v2f32")
1780 "paddl_s16" => Intrinsic
{
1781 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }
,
1783 definition
: Named("llvm.neon.vpaddls.v4i16.v8i8")
1785 "paddl_u16" => Intrinsic
{
1786 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }
,
1788 definition
: Named("llvm.neon.vpaddlu.v4i16.v8i8")
1790 "paddl_s32" => Intrinsic
{
1791 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }
,
1793 definition
: Named("llvm.neon.vpaddls.v2i32.v4i16")
1795 "paddl_u32" => Intrinsic
{
1796 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }
,
1798 definition
: Named("llvm.neon.vpaddlu.v2i32.v4i16")
1800 "paddl_s64" => Intrinsic
{
1801 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }
,
1803 definition
: Named("llvm.neon.vpaddls.v1i64.v2i32")
1805 "paddl_u64" => Intrinsic
{
1806 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }
,
1808 definition
: Named("llvm.neon.vpaddlu.v1i64.v2i32")
1810 "paddlq_s16" => Intrinsic
{
1811 inputs
: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }
,
1813 definition
: Named("llvm.neon.vpaddls.v8i16.v16i8")
1815 "paddlq_u16" => Intrinsic
{
1816 inputs
: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }
,
1818 definition
: Named("llvm.neon.vpaddlu.v8i16.v16i8")
1820 "paddlq_s32" => Intrinsic
{
1821 inputs
: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }
,
1823 definition
: Named("llvm.neon.vpaddls.v4i32.v8i16")
1825 "paddlq_u32" => Intrinsic
{
1826 inputs
: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }
,
1828 definition
: Named("llvm.neon.vpaddlu.v4i32.v8i16")
1830 "paddlq_s64" => Intrinsic
{
1831 inputs
: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }
,
1833 definition
: Named("llvm.neon.vpaddls.v2i64.v4i32")
1835 "paddlq_u64" => Intrinsic
{
1836 inputs
: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }
,
1838 definition
: Named("llvm.neon.vpaddlu.v2i64.v4i32")
1840 "padal_s16" => Intrinsic
{
1841 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I8x8]; &INPUTS }
,
1843 definition
: Named("llvm.neon.vpadals.v4i16.v4i16")
1845 "padal_u16" => Intrinsic
{
1846 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U8x8]; &INPUTS }
,
1848 definition
: Named("llvm.neon.vpadalu.v4i16.v4i16")
1850 "padal_s32" => Intrinsic
{
1851 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I16x4]; &INPUTS }
,
1853 definition
: Named("llvm.neon.vpadals.v2i32.v2i32")
1855 "padal_u32" => Intrinsic
{
1856 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U16x4]; &INPUTS }
,
1858 definition
: Named("llvm.neon.vpadalu.v2i32.v2i32")
1860 "padal_s64" => Intrinsic
{
1861 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I32x2]; &INPUTS }
,
1863 definition
: Named("llvm.neon.vpadals.v1i64.v1i64")
1865 "padal_u64" => Intrinsic
{
1866 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U32x2]; &INPUTS }
,
1868 definition
: Named("llvm.neon.vpadalu.v1i64.v1i64")
1870 "padalq_s16" => Intrinsic
{
1871 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I8x16]; &INPUTS }
,
1873 definition
: Named("llvm.neon.vpadals.v8i16.v8i16")
1875 "padalq_u16" => Intrinsic
{
1876 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U8x16]; &INPUTS }
,
1878 definition
: Named("llvm.neon.vpadalu.v8i16.v8i16")
1880 "padalq_s32" => Intrinsic
{
1881 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I16x8]; &INPUTS }
,
1883 definition
: Named("llvm.neon.vpadals.v4i32.v4i32")
1885 "padalq_u32" => Intrinsic
{
1886 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U16x8]; &INPUTS }
,
1888 definition
: Named("llvm.neon.vpadalu.v4i32.v4i32")
1890 "padalq_s64" => Intrinsic
{
1891 inputs
: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I32x4]; &INPUTS }
,
1893 definition
: Named("llvm.neon.vpadals.v2i64.v2i64")
1895 "padalq_u64" => Intrinsic
{
1896 inputs
: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32x4]; &INPUTS }
,
1898 definition
: Named("llvm.neon.vpadalu.v2i64.v2i64")
1900 "pmax_s8" => Intrinsic
{
1901 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
1903 definition
: Named("llvm.neon.vpmaxs.v8i8")
1905 "pmax_u8" => Intrinsic
{
1906 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
1908 definition
: Named("llvm.neon.vpmaxu.v8i8")
1910 "pmax_s16" => Intrinsic
{
1911 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
1913 definition
: Named("llvm.neon.vpmaxs.v4i16")
1915 "pmax_u16" => Intrinsic
{
1916 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
1918 definition
: Named("llvm.neon.vpmaxu.v4i16")
1920 "pmax_s32" => Intrinsic
{
1921 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
1923 definition
: Named("llvm.neon.vpmaxs.v2i32")
1925 "pmax_u32" => Intrinsic
{
1926 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
1928 definition
: Named("llvm.neon.vpmaxu.v2i32")
1930 "pmax_f32" => Intrinsic
{
1931 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
1933 definition
: Named("llvm.neon.vpmaxf.v2f32")
1935 "pmin_s8" => Intrinsic
{
1936 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }
,
1938 definition
: Named("llvm.neon.vpmins.v8i8")
1940 "pmin_u8" => Intrinsic
{
1941 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
1943 definition
: Named("llvm.neon.vpminu.v8i8")
1945 "pmin_s16" => Intrinsic
{
1946 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }
,
1948 definition
: Named("llvm.neon.vpmins.v4i16")
1950 "pmin_u16" => Intrinsic
{
1951 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }
,
1953 definition
: Named("llvm.neon.vpminu.v4i16")
1955 "pmin_s32" => Intrinsic
{
1956 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }
,
1958 definition
: Named("llvm.neon.vpmins.v2i32")
1960 "pmin_u32" => Intrinsic
{
1961 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }
,
1963 definition
: Named("llvm.neon.vpminu.v2i32")
1965 "pmin_f32" => Intrinsic
{
1966 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }
,
1968 definition
: Named("llvm.neon.vpminf.v2f32")
1970 "pminq_s8" => Intrinsic
{
1971 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }
,
1973 definition
: Named("llvm.neon.vpmins.v16i8")
1975 "pminq_u8" => Intrinsic
{
1976 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }
,
1978 definition
: Named("llvm.neon.vpminu.v16i8")
1980 "pminq_s16" => Intrinsic
{
1981 inputs
: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }
,
1983 definition
: Named("llvm.neon.vpmins.v8i16")
1985 "pminq_u16" => Intrinsic
{
1986 inputs
: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }
,
1988 definition
: Named("llvm.neon.vpminu.v8i16")
1990 "pminq_s32" => Intrinsic
{
1991 inputs
: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }
,
1993 definition
: Named("llvm.neon.vpmins.v4i32")
1995 "pminq_u32" => Intrinsic
{
1996 inputs
: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }
,
1998 definition
: Named("llvm.neon.vpminu.v4i32")
2000 "pminq_f32" => Intrinsic
{
2001 inputs
: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }
,
2003 definition
: Named("llvm.neon.vpminf.v4f32")
2005 "tbl1_s8" => Intrinsic
{
2006 inputs
: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::U8x8]; &INPUTS }
,
2008 definition
: Named("llvm.neon.vtbl1")
2010 "tbl1_u8" => Intrinsic
{
2011 inputs
: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }
,
2013 definition
: Named("llvm.neon.vtbl1")
2015 "tbx1_s8" => Intrinsic
{
2016 inputs
: { static INPUTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::U8x8]; &INPUTS }
,
2018 definition
: Named("llvm.neon.vtbx1")
2020 "tbx1_u8" => Intrinsic
{
2021 inputs
: { static INPUTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &INPUTS }
,
2023 definition
: Named("llvm.neon.vtbx1")
2025 "tbl2_s8" => Intrinsic
{
2026 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
2028 definition
: Named("llvm.neon.vtbl2")
2030 "tbl2_u8" => Intrinsic
{
2031 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
2033 definition
: Named("llvm.neon.vtbl2")
2035 "tbx2_s8" => Intrinsic
{
2036 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
2038 definition
: Named("llvm.neon.vtbx2")
2040 "tbx2_u8" => Intrinsic
{
2041 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
2043 definition
: Named("llvm.neon.vtbx2")
2045 "tbl3_s8" => Intrinsic
{
2046 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::I8x8]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
2048 definition
: Named("llvm.neon.vtbl3")
2050 "tbl3_u8" => Intrinsic
{
2051 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
2053 definition
: Named("llvm.neon.vtbl3")
2055 "tbx3_s8" => Intrinsic
{
2056 inputs
: { static INPUTS: [&'static Type; 3] = [&::I8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::I8x8]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
2058 definition
: Named("llvm.neon.vtbx3")
2060 "tbx3_u8" => Intrinsic
{
2061 inputs
: { static INPUTS: [&'static Type; 3] = [&::U8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
2063 definition
: Named("llvm.neon.vtbx3")
2065 "tbl4_s8" => Intrinsic
{
2066 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x8, &::I8x8, &::I8x8, &::I8x8]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
2068 definition
: Named("llvm.neon.vtbl4")
2070 "tbl4_u8" => Intrinsic
{
2071 inputs
: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x8, &::U8x8, &::U8x8, &::U8x8]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
2073 definition
: Named("llvm.neon.vtbl4")
2075 "tbx4_s8" => Intrinsic
{
2076 inputs
: { static INPUTS: [&'static Type; 3] = [&::I8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x8, &::I8x8, &::I8x8, &::I8x8]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
2078 definition
: Named("llvm.neon.vtbx4")
2080 "tbx4_u8" => Intrinsic
{
2081 inputs
: { static INPUTS: [&'static Type; 3] = [&::U8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x8, &::U8x8, &::U8x8, &::U8x8]; &PARTS }
); &AGG
}, &::U8x8
]; &INPUTS
},
2083 definition
: Named("llvm.neon.vtbx4")