1 // Targets the Cortex-M4F and Cortex-M7F processors (ARMv7E-M)
3 // This target assumes that the device does have a FPU (Floating Point Unit) and lowers all (single
4 // precision) floating point operations to hardware instructions.
6 // Additionally, this target uses the "hard" floating convention (ABI) where floating point values
7 // are passed to/from subroutines via FPU registers (S0, S1, D0, D1, etc.).
9 // To opt into double precision hardware support, use the `-C target-feature=+fp64` flag.
11 use crate::spec
::{LinkerFlavor, LldFlavor, Target, TargetOptions, TargetResult}
;
13 pub fn target() -> TargetResult
{
15 llvm_target
: "thumbv7em-none-eabihf".to_string(),
16 target_endian
: "little".to_string(),
17 target_pointer_width
: "32".to_string(),
18 target_c_int_width
: "32".to_string(),
19 data_layout
: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".to_string(),
20 arch
: "arm".to_string(),
21 target_os
: "none".to_string(),
22 target_env
: String
::new(),
23 target_vendor
: String
::new(),
24 linker_flavor
: LinkerFlavor
::Lld(LldFlavor
::Ld
),
26 options
: TargetOptions
{
27 // `+vfp4` is the lowest common denominator between the Cortex-M4 (vfp4-16) and the
29 // `-d32` both the Cortex-M4 and the Cortex-M7 only have 16 double-precision registers
31 // `-fp64` The Cortex-M4 only supports single precision floating point operations
32 // whereas in the Cortex-M7 double precision is optional
35 // ARMv7-M Architecture Reference Manual - A2.5 The optional floating-point extension
36 features
: "+vfp4,-d32,-fp64".to_string(),
37 max_atomic_width
: Some(32),
38 ..super::thumb_base
::opts()