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1 //===-- RegisterClassInfo.h - Dynamic Register Class Info -*- C++ -*-------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the RegisterClassInfo class which provides dynamic
11 // information about target register classes. Callee saved and reserved
12 // registers depends on calling conventions and other dynamic information, so
13 // some things cannot be determined statically.
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H
18 #define LLVM_CODEGEN_REGISTERCLASSINFO_H
20 #include "llvm/ADT/ArrayRef.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
26 class RegisterClassInfo
{
32 uint16_t LastCostChange
;
33 std::unique_ptr
<MCPhysReg
[]> Order
;
36 : Tag(0), NumRegs(0), ProperSubClass(false), MinCost(0),
39 operator ArrayRef
<MCPhysReg
>() const {
40 return makeArrayRef(Order
.get(), NumRegs
);
44 // Brief cached information for each register class.
45 std::unique_ptr
<RCInfo
[]> RegClass
;
47 // Tag changes whenever cached information needs to be recomputed. An RCInfo
48 // entry is valid when its tag matches.
51 const MachineFunction
*MF
;
52 const TargetRegisterInfo
*TRI
;
54 // Callee saved registers of last MF. Assumed to be valid until the next
55 // runOnFunction() call.
56 const MCPhysReg
*CalleeSaved
;
58 // Map register number to CalleeSaved index + 1;
59 SmallVector
<uint8_t, 4> CSRNum
;
61 // Reserved registers in the current MF.
64 std::unique_ptr
<unsigned[]> PSetLimits
;
66 // Compute all information about RC.
67 void compute(const TargetRegisterClass
*RC
) const;
69 // Return an up-to-date RCInfo for RC.
70 const RCInfo
&get(const TargetRegisterClass
*RC
) const {
71 const RCInfo
&RCI
= RegClass
[RC
->getID()];
80 /// runOnFunction - Prepare to answer questions about MF. This must be called
81 /// before any other methods are used.
82 void runOnMachineFunction(const MachineFunction
&MF
);
84 /// getNumAllocatableRegs - Returns the number of actually allocatable
85 /// registers in RC in the current function.
86 unsigned getNumAllocatableRegs(const TargetRegisterClass
*RC
) const {
87 return get(RC
).NumRegs
;
90 /// getOrder - Returns the preferred allocation order for RC. The order
91 /// contains no reserved registers, and registers that alias callee saved
92 /// registers come last.
93 ArrayRef
<MCPhysReg
> getOrder(const TargetRegisterClass
*RC
) const {
97 /// isProperSubClass - Returns true if RC has a legal super-class with more
98 /// allocatable registers.
100 /// Register classes like GR32_NOSP are not proper sub-classes because %esp
101 /// is not allocatable. Similarly, tGPR is not a proper sub-class in Thumb
102 /// mode because the GPR super-class is not legal.
103 bool isProperSubClass(const TargetRegisterClass
*RC
) const {
104 return get(RC
).ProperSubClass
;
107 /// getLastCalleeSavedAlias - Returns the last callee saved register that
108 /// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR.
109 unsigned getLastCalleeSavedAlias(unsigned PhysReg
) const {
110 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg
));
111 if (unsigned N
= CSRNum
[PhysReg
])
112 return CalleeSaved
[N
-1];
116 /// Get the minimum register cost in RC's allocation order.
117 /// This is the smallest value returned by TRI->getCostPerUse(Reg) for all
118 /// the registers in getOrder(RC).
119 unsigned getMinCost(const TargetRegisterClass
*RC
) {
120 return get(RC
).MinCost
;
123 /// Get the position of the last cost change in getOrder(RC).
125 /// All registers in getOrder(RC).slice(getLastCostChange(RC)) will have the
126 /// same cost according to TRI->getCostPerUse().
127 unsigned getLastCostChange(const TargetRegisterClass
*RC
) {
128 return get(RC
).LastCostChange
;
131 /// Get the register unit limit for the given pressure set index.
133 /// RegisterClassInfo adjusts this limit for reserved registers.
134 unsigned getRegPressureSetLimit(unsigned Idx
) const {
135 if (!PSetLimits
[Idx
])
136 PSetLimits
[Idx
] = computePSetLimit(Idx
);
137 return PSetLimits
[Idx
];
141 unsigned computePSetLimit(unsigned Idx
) const;
143 } // end namespace llvm