1 //=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_MC_MCREGISTERINFO_H
17 #define LLVM_MC_MCREGISTERINFO_H
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/Support/ErrorHandling.h"
25 /// An unsigned integer type large enough to represent all physical registers,
26 /// but not necessarily virtual registers.
27 typedef uint16_t MCPhysReg
;
29 /// MCRegisterClass - Base class of TargetRegisterClass.
30 class MCRegisterClass
{
32 typedef const MCPhysReg
* iterator
;
33 typedef const MCPhysReg
* const_iterator
;
35 const iterator RegsBegin
;
36 const uint8_t *const RegSet
;
37 const uint32_t NameIdx
;
38 const uint16_t RegsSize
;
39 const uint16_t RegSetSize
;
41 const uint16_t RegSize
, Alignment
; // Size & Alignment of register in bytes
42 const int8_t CopyCost
;
43 const bool Allocatable
;
45 /// getID() - Return the register class ID number.
47 unsigned getID() const { return ID
; }
49 /// begin/end - Return all of the registers in this class.
51 iterator
begin() const { return RegsBegin
; }
52 iterator
end() const { return RegsBegin
+ RegsSize
; }
54 /// getNumRegs - Return the number of registers in this class.
56 unsigned getNumRegs() const { return RegsSize
; }
58 /// getRegister - Return the specified register in the class.
60 unsigned getRegister(unsigned i
) const {
61 assert(i
< getNumRegs() && "Register number out of range!");
65 /// contains - Return true if the specified register is included in this
66 /// register class. This does not include virtual registers.
67 bool contains(unsigned Reg
) const {
68 unsigned InByte
= Reg
% 8;
69 unsigned Byte
= Reg
/ 8;
70 if (Byte
>= RegSetSize
)
72 return (RegSet
[Byte
] & (1 << InByte
)) != 0;
75 /// contains - Return true if both registers are in this class.
76 bool contains(unsigned Reg1
, unsigned Reg2
) const {
77 return contains(Reg1
) && contains(Reg2
);
80 /// getSize - Return the size of the register in bytes, which is also the size
81 /// of a stack slot allocated to hold a spilled copy of this register.
82 unsigned getSize() const { return RegSize
; }
84 /// getAlignment - Return the minimum required alignment for a register of
86 unsigned getAlignment() const { return Alignment
; }
88 /// getCopyCost - Return the cost of copying a value between two registers in
89 /// this class. A negative number means the register class is very expensive
90 /// to copy e.g. status flag register classes.
91 int getCopyCost() const { return CopyCost
; }
93 /// isAllocatable - Return true if this register class may be used to create
94 /// virtual registers.
95 bool isAllocatable() const { return Allocatable
; }
98 /// MCRegisterDesc - This record contains information about a particular
99 /// register. The SubRegs field is a zero terminated array of registers that
100 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers
101 /// of AX. The SuperRegs field is a zero terminated array of registers that are
102 /// super-registers of the specific register, e.g. RAX, EAX, are
103 /// super-registers of AX.
105 struct MCRegisterDesc
{
106 uint32_t Name
; // Printable name for the reg (for debugging)
107 uint32_t SubRegs
; // Sub-register set, described above
108 uint32_t SuperRegs
; // Super-register set, described above
110 // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
111 // sub-register in SubRegs.
112 uint32_t SubRegIndices
;
114 // RegUnits - Points to the list of register units. The low 4 bits holds the
115 // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
118 /// Index into list with lane mask sequences. The sequence contains a lanemask
119 /// for every register unit.
120 uint16_t RegUnitLaneMasks
;
123 /// MCRegisterInfo base class - We assume that the target defines a static
124 /// array of MCRegisterDesc objects that represent all of the machine
125 /// registers that the target has. As such, we simply have to track a pointer
126 /// to this array so that we can turn register number into a register
129 /// Note this class is designed to be a base class of TargetRegisterInfo, which
130 /// is the interface used by codegen. However, specific targets *should never*
131 /// specialize this class. MCRegisterInfo should only contain getters to access
132 /// TableGen generated physical register data. It must not be extended with
135 class MCRegisterInfo
{
137 typedef const MCRegisterClass
*regclass_iterator
;
139 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
140 /// performed with a binary search.
141 struct DwarfLLVMRegPair
{
145 bool operator<(DwarfLLVMRegPair RHS
) const { return FromReg
< RHS
.FromReg
; }
148 /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
149 /// index, -1 in any being invalid.
150 struct SubRegCoveredBits
{
155 const MCRegisterDesc
*Desc
; // Pointer to the descriptor array
156 unsigned NumRegs
; // Number of entries in the array
157 unsigned RAReg
; // Return address register
158 unsigned PCReg
; // Program counter register
159 const MCRegisterClass
*Classes
; // Pointer to the regclass array
160 unsigned NumClasses
; // Number of entries in the array
161 unsigned NumRegUnits
; // Number of regunits.
162 const MCPhysReg (*RegUnitRoots
)[2]; // Pointer to regunit root table.
163 const MCPhysReg
*DiffLists
; // Pointer to the difflists array
164 const unsigned *RegUnitMaskSequences
; // Pointer to lane mask sequences
165 // for register units.
166 const char *RegStrings
; // Pointer to the string table.
167 const char *RegClassStrings
; // Pointer to the class strings.
168 const uint16_t *SubRegIndices
; // Pointer to the subreg lookup
170 const SubRegCoveredBits
*SubRegIdxRanges
; // Pointer to the subreg covered
172 unsigned NumSubRegIndices
; // Number of subreg indices.
173 const uint16_t *RegEncodingTable
; // Pointer to array of register
176 unsigned L2DwarfRegsSize
;
177 unsigned EHL2DwarfRegsSize
;
178 unsigned Dwarf2LRegsSize
;
179 unsigned EHDwarf2LRegsSize
;
180 const DwarfLLVMRegPair
*L2DwarfRegs
; // LLVM to Dwarf regs mapping
181 const DwarfLLVMRegPair
*EHL2DwarfRegs
; // LLVM to Dwarf regs mapping EH
182 const DwarfLLVMRegPair
*Dwarf2LRegs
; // Dwarf to LLVM regs mapping
183 const DwarfLLVMRegPair
*EHDwarf2LRegs
; // Dwarf to LLVM regs mapping EH
184 DenseMap
<unsigned, int> L2SEHRegs
; // LLVM to SEH regs mapping
187 /// DiffListIterator - Base iterator class that can traverse the
188 /// differentially encoded register and regunit lists in DiffLists.
189 /// Don't use this class directly, use one of the specialized sub-classes
191 class DiffListIterator
{
193 const MCPhysReg
*List
;
196 /// Create an invalid iterator. Call init() to point to something useful.
197 DiffListIterator() : Val(0), List(nullptr) {}
199 /// init - Point the iterator to InitVal, decoding subsequent values from
200 /// DiffList. The iterator will initially point to InitVal, sub-classes are
201 /// responsible for skipping the seed value if it is not part of the list.
202 void init(MCPhysReg InitVal
, const MCPhysReg
*DiffList
) {
207 /// advance - Move to the next list position, return the applied
208 /// differential. This function does not detect the end of the list, that
209 /// is the caller's responsibility (by checking for a 0 return value).
211 assert(isValid() && "Cannot move off the end of the list.");
212 MCPhysReg D
= *List
++;
219 /// isValid - returns true if this iterator is not yet at the end.
220 bool isValid() const { return List
; }
222 /// Dereference the iterator to get the value at the current position.
223 unsigned operator*() const { return Val
; }
225 /// Pre-increment to move to the next position.
227 // The end of the list is encoded as a 0 differential.
233 // These iterators are allowed to sub-class DiffListIterator and access
234 // internal list pointers.
235 friend class MCSubRegIterator
;
236 friend class MCSubRegIndexIterator
;
237 friend class MCSuperRegIterator
;
238 friend class MCRegUnitIterator
;
239 friend class MCRegUnitMaskIterator
;
240 friend class MCRegUnitRootIterator
;
242 /// \brief Initialize MCRegisterInfo, called by TableGen
243 /// auto-generated routines. *DO NOT USE*.
244 void InitMCRegisterInfo(const MCRegisterDesc
*D
, unsigned NR
, unsigned RA
,
246 const MCRegisterClass
*C
, unsigned NC
,
247 const MCPhysReg (*RURoots
)[2],
250 const unsigned *RUMS
,
252 const char *ClassStrings
,
253 const uint16_t *SubIndices
,
255 const SubRegCoveredBits
*SubIdxRanges
,
256 const uint16_t *RET
) {
263 RegUnitMaskSequences
= RUMS
;
264 RegStrings
= Strings
;
265 RegClassStrings
= ClassStrings
;
267 RegUnitRoots
= RURoots
;
269 SubRegIndices
= SubIndices
;
270 NumSubRegIndices
= NumIndices
;
271 SubRegIdxRanges
= SubIdxRanges
;
272 RegEncodingTable
= RET
;
275 /// \brief Used to initialize LLVM register to Dwarf
276 /// register number mapping. Called by TableGen auto-generated routines.
278 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair
*Map
, unsigned Size
,
282 EHL2DwarfRegsSize
= Size
;
285 L2DwarfRegsSize
= Size
;
289 /// \brief Used to initialize Dwarf register to LLVM
290 /// register number mapping. Called by TableGen auto-generated routines.
292 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair
*Map
, unsigned Size
,
296 EHDwarf2LRegsSize
= Size
;
299 Dwarf2LRegsSize
= Size
;
303 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
304 /// number mapping. By default the SEH register number is just the same
305 /// as the LLVM register number.
306 /// FIXME: TableGen these numbers. Currently this requires target specific
307 /// initialization code.
308 void mapLLVMRegToSEHReg(unsigned LLVMReg
, int SEHReg
) {
309 L2SEHRegs
[LLVMReg
] = SEHReg
;
312 /// \brief This method should return the register where the return
313 /// address can be found.
314 unsigned getRARegister() const {
318 /// Return the register which is the program counter.
319 unsigned getProgramCounter() const {
323 const MCRegisterDesc
&operator[](unsigned RegNo
) const {
324 assert(RegNo
< NumRegs
&&
325 "Attempting to access record for invalid register number!");
329 /// \brief Provide a get method, equivalent to [], but more useful with a
330 /// pointer to this object.
331 const MCRegisterDesc
&get(unsigned RegNo
) const {
332 return operator[](RegNo
);
335 /// \brief Returns the physical register number of sub-register "Index"
336 /// for physical register RegNo. Return zero if the sub-register does not
338 unsigned getSubReg(unsigned Reg
, unsigned Idx
) const;
340 /// \brief Return a super-register of the specified register
341 /// Reg so its sub-register of index SubIdx is Reg.
342 unsigned getMatchingSuperReg(unsigned Reg
, unsigned SubIdx
,
343 const MCRegisterClass
*RC
) const;
345 /// \brief For a given register pair, return the sub-register index
346 /// if the second register is a sub-register of the first. Return zero
348 unsigned getSubRegIndex(unsigned RegNo
, unsigned SubRegNo
) const;
350 /// \brief Get the size of the bit range covered by a sub-register index.
351 /// If the index isn't continuous, return the sum of the sizes of its parts.
352 /// If the index is used to access subregisters of different sizes, return -1.
353 unsigned getSubRegIdxSize(unsigned Idx
) const;
355 /// \brief Get the offset of the bit range covered by a sub-register index.
356 /// If an Offset doesn't make sense (the index isn't continuous, or is used to
357 /// access sub-registers at different offsets), return -1.
358 unsigned getSubRegIdxOffset(unsigned Idx
) const;
360 /// \brief Return the human-readable symbolic target-specific name for the
361 /// specified physical register.
362 const char *getName(unsigned RegNo
) const {
363 return RegStrings
+ get(RegNo
).Name
;
366 /// \brief Return the number of registers this target has (useful for
367 /// sizing arrays holding per register information)
368 unsigned getNumRegs() const {
372 /// \brief Return the number of sub-register indices
373 /// understood by the target. Index 0 is reserved for the no-op sub-register,
374 /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
375 unsigned getNumSubRegIndices() const {
376 return NumSubRegIndices
;
379 /// \brief Return the number of (native) register units in the
380 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
381 /// can be accessed through MCRegUnitIterator defined below.
382 unsigned getNumRegUnits() const {
386 /// \brief Map a target register to an equivalent dwarf register
387 /// number. Returns -1 if there is no equivalent value. The second
388 /// parameter allows targets to use different numberings for EH info and
390 int getDwarfRegNum(unsigned RegNum
, bool isEH
) const;
392 /// \brief Map a dwarf register back to a target register.
393 int getLLVMRegNum(unsigned RegNum
, bool isEH
) const;
395 /// \brief Map a target register to an equivalent SEH register
396 /// number. Returns LLVM register number if there is no equivalent value.
397 int getSEHRegNum(unsigned RegNum
) const;
399 regclass_iterator
regclass_begin() const { return Classes
; }
400 regclass_iterator
regclass_end() const { return Classes
+NumClasses
; }
402 unsigned getNumRegClasses() const {
403 return (unsigned)(regclass_end()-regclass_begin());
406 /// \brief Returns the register class associated with the enumeration
407 /// value. See class MCOperandInfo.
408 const MCRegisterClass
& getRegClass(unsigned i
) const {
409 assert(i
< getNumRegClasses() && "Register Class ID out of range");
413 const char *getRegClassName(const MCRegisterClass
*Class
) const {
414 return RegClassStrings
+ Class
->NameIdx
;
417 /// \brief Returns the encoding for RegNo
418 uint16_t getEncodingValue(unsigned RegNo
) const {
419 assert(RegNo
< NumRegs
&&
420 "Attempting to get encoding for invalid register number!");
421 return RegEncodingTable
[RegNo
];
424 /// \brief Returns true if RegB is a sub-register of RegA.
425 bool isSubRegister(unsigned RegA
, unsigned RegB
) const {
426 return isSuperRegister(RegB
, RegA
);
429 /// \brief Returns true if RegB is a super-register of RegA.
430 bool isSuperRegister(unsigned RegA
, unsigned RegB
) const;
432 /// \brief Returns true if RegB is a sub-register of RegA or if RegB == RegA.
433 bool isSubRegisterEq(unsigned RegA
, unsigned RegB
) const {
434 return isSuperRegisterEq(RegB
, RegA
);
437 /// \brief Returns true if RegB is a super-register of RegA or if
439 bool isSuperRegisterEq(unsigned RegA
, unsigned RegB
) const {
440 return RegA
== RegB
|| isSuperRegister(RegA
, RegB
);
445 //===----------------------------------------------------------------------===//
446 // Register List Iterators
447 //===----------------------------------------------------------------------===//
449 // MCRegisterInfo provides lists of super-registers, sub-registers, and
450 // aliasing registers. Use these iterator classes to traverse the lists.
452 /// MCSubRegIterator enumerates all sub-registers of Reg.
453 /// If IncludeSelf is set, Reg itself is included in the list.
454 class MCSubRegIterator
: public MCRegisterInfo::DiffListIterator
{
456 MCSubRegIterator(unsigned Reg
, const MCRegisterInfo
*MCRI
,
457 bool IncludeSelf
= false) {
458 init(Reg
, MCRI
->DiffLists
+ MCRI
->get(Reg
).SubRegs
);
459 // Initially, the iterator points to Reg itself.
465 /// Iterator that enumerates the sub-registers of a Reg and the associated
466 /// sub-register indices.
467 class MCSubRegIndexIterator
{
468 MCSubRegIterator SRIter
;
469 const uint16_t *SRIndex
;
471 /// Constructs an iterator that traverses subregisters and their
472 /// associated subregister indices.
473 MCSubRegIndexIterator(unsigned Reg
, const MCRegisterInfo
*MCRI
)
474 : SRIter(Reg
, MCRI
) {
475 SRIndex
= MCRI
->SubRegIndices
+ MCRI
->get(Reg
).SubRegIndices
;
478 /// Returns current sub-register.
479 unsigned getSubReg() const {
482 /// Returns sub-register index of the current sub-register.
483 unsigned getSubRegIndex() const {
487 /// Returns true if this iterator is not yet at the end.
488 bool isValid() const { return SRIter
.isValid(); }
490 /// Moves to the next position.
497 /// MCSuperRegIterator enumerates all super-registers of Reg.
498 /// If IncludeSelf is set, Reg itself is included in the list.
499 class MCSuperRegIterator
: public MCRegisterInfo::DiffListIterator
{
501 MCSuperRegIterator() {}
502 MCSuperRegIterator(unsigned Reg
, const MCRegisterInfo
*MCRI
,
503 bool IncludeSelf
= false) {
504 init(Reg
, MCRI
->DiffLists
+ MCRI
->get(Reg
).SuperRegs
);
505 // Initially, the iterator points to Reg itself.
511 // Definition for isSuperRegister. Put it down here since it needs the
512 // iterator defined above in addition to the MCRegisterInfo class itself.
513 inline bool MCRegisterInfo::isSuperRegister(unsigned RegA
, unsigned RegB
) const{
514 for (MCSuperRegIterator
I(RegA
, this); I
.isValid(); ++I
)
520 //===----------------------------------------------------------------------===//
522 //===----------------------------------------------------------------------===//
524 // Register units are used to compute register aliasing. Every register has at
525 // least one register unit, but it can have more. Two registers overlap if and
526 // only if they have a common register unit.
528 // A target with a complicated sub-register structure will typically have many
529 // fewer register units than actual registers. MCRI::getNumRegUnits() returns
530 // the number of register units in the target.
532 // MCRegUnitIterator enumerates a list of register units for Reg. The list is
533 // in ascending numerical order.
534 class MCRegUnitIterator
: public MCRegisterInfo::DiffListIterator
{
536 /// MCRegUnitIterator - Create an iterator that traverses the register units
538 MCRegUnitIterator() {}
539 MCRegUnitIterator(unsigned Reg
, const MCRegisterInfo
*MCRI
) {
540 assert(Reg
&& "Null register has no regunits");
541 // Decode the RegUnits MCRegisterDesc field.
542 unsigned RU
= MCRI
->get(Reg
).RegUnits
;
543 unsigned Scale
= RU
& 15;
544 unsigned Offset
= RU
>> 4;
546 // Initialize the iterator to Reg * Scale, and the List pointer to
547 // DiffLists + Offset.
548 init(Reg
* Scale
, MCRI
->DiffLists
+ Offset
);
550 // That may not be a valid unit, we need to advance by one to get the real
551 // unit number. The first differential can be 0 which would normally
552 // terminate the list, but since we know every register has at least one
553 // unit, we can allow a 0 differential here.
558 /// MCRegUnitIterator enumerates a list of register units and their associated
559 /// lane masks for Reg. The register units are in ascending numerical order.
560 class MCRegUnitMaskIterator
{
561 MCRegUnitIterator RUIter
;
562 const unsigned *MaskListIter
;
564 MCRegUnitMaskIterator() {}
565 /// Constructs an iterator that traverses the register units and their
566 /// associated LaneMasks in Reg.
567 MCRegUnitMaskIterator(unsigned Reg
, const MCRegisterInfo
*MCRI
)
568 : RUIter(Reg
, MCRI
) {
569 uint16_t Idx
= MCRI
->get(Reg
).RegUnitLaneMasks
;
570 MaskListIter
= &MCRI
->RegUnitMaskSequences
[Idx
];
573 /// Returns a (RegUnit, LaneMask) pair.
574 std::pair
<unsigned,unsigned> operator*() const {
575 return std::make_pair(*RUIter
, *MaskListIter
);
578 /// Returns true if this iterator is not yet at the end.
579 bool isValid() const { return RUIter
.isValid(); }
581 /// Moves to the next position.
588 // Each register unit has one or two root registers. The complete set of
589 // registers containing a register unit is the union of the roots and their
590 // super-registers. All registers aliasing Unit can be visited like this:
592 // for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
593 // for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
597 /// MCRegUnitRootIterator enumerates the root registers of a register unit.
598 class MCRegUnitRootIterator
{
602 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {}
603 MCRegUnitRootIterator(unsigned RegUnit
, const MCRegisterInfo
*MCRI
) {
604 assert(RegUnit
< MCRI
->getNumRegUnits() && "Invalid register unit");
605 Reg0
= MCRI
->RegUnitRoots
[RegUnit
][0];
606 Reg1
= MCRI
->RegUnitRoots
[RegUnit
][1];
609 /// \brief Dereference to get the current root register.
610 unsigned operator*() const {
614 /// \brief Check if the iterator is at the end of the list.
615 bool isValid() const {
619 /// \brief Preincrement to move to the next root register.
621 assert(isValid() && "Cannot move off the end of the list.");
627 /// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is
628 /// set, Reg itself is included in the list. This iterator does not guarantee
629 /// any ordering or that entries are unique.
630 class MCRegAliasIterator
{
633 const MCRegisterInfo
*MCRI
;
636 MCRegUnitIterator RI
;
637 MCRegUnitRootIterator RRI
;
638 MCSuperRegIterator SI
;
640 MCRegAliasIterator(unsigned Reg
, const MCRegisterInfo
*MCRI
,
642 : Reg(Reg
), MCRI(MCRI
), IncludeSelf(IncludeSelf
) {
644 // Initialize the iterators.
645 for (RI
= MCRegUnitIterator(Reg
, MCRI
); RI
.isValid(); ++RI
) {
646 for (RRI
= MCRegUnitRootIterator(*RI
, MCRI
); RRI
.isValid(); ++RRI
) {
647 for (SI
= MCSuperRegIterator(*RRI
, MCRI
, true); SI
.isValid(); ++SI
) {
648 if (!(!IncludeSelf
&& Reg
== *SI
))
655 bool isValid() const {
659 unsigned operator*() const {
660 assert (SI
.isValid() && "Cannot dereference an invalid iterator.");
665 // Assuming SI is valid.
667 if (SI
.isValid()) return;
671 SI
= MCSuperRegIterator(*RRI
, MCRI
, true);
677 RRI
= MCRegUnitRootIterator(*RI
, MCRI
);
678 SI
= MCSuperRegIterator(*RRI
, MCRI
, true);
683 assert(isValid() && "Cannot move off the end of the list.");
685 while (!IncludeSelf
&& isValid() && *SI
== Reg
);
689 } // End llvm namespace