1 //===- RegisterCoalescer.cpp - Generic Register Coalescing Interface -------==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the generic RegisterCoalescer interface which
11 // is used as the common interface used by all clients and
12 // implementations of register coalescing.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterCoalescer.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/LiveRangeEdit.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineLoopInfo.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/CodeGen/RegisterClassInfo.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/IR/Value.h"
31 #include "llvm/Pass.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/Format.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
40 #include "llvm/Target/TargetSubtargetInfo.h"
45 #define DEBUG_TYPE "regalloc"
47 STATISTIC(numJoins
, "Number of interval joins performed");
48 STATISTIC(numCrossRCs
, "Number of cross class joins performed");
49 STATISTIC(numCommutes
, "Number of instruction commuting performed");
50 STATISTIC(numExtends
, "Number of copies extended");
51 STATISTIC(NumReMats
, "Number of instructions re-materialized");
52 STATISTIC(NumInflated
, "Number of register classes inflated");
53 STATISTIC(NumLaneConflicts
, "Number of dead lane conflicts tested");
54 STATISTIC(NumLaneResolves
, "Number of dead lane conflicts resolved");
57 EnableJoining("join-liveintervals",
58 cl::desc("Coalesce copies (default=true)"),
61 // Temporary flag to test critical edge unsplitting.
63 EnableJoinSplits("join-splitedges",
64 cl::desc("Coalesce copies on split edges (default=subtarget)"), cl::Hidden
);
66 // Temporary flag to test global copy optimization.
67 static cl::opt
<cl::boolOrDefault
>
68 EnableGlobalCopies("join-globalcopies",
69 cl::desc("Coalesce copies that span blocks (default=subtarget)"),
70 cl::init(cl::BOU_UNSET
), cl::Hidden
);
73 VerifyCoalescing("verify-coalescing",
74 cl::desc("Verify machine instrs before and after register coalescing"),
78 class RegisterCoalescer
: public MachineFunctionPass
,
79 private LiveRangeEdit::Delegate
{
81 MachineRegisterInfo
* MRI
;
82 const TargetMachine
* TM
;
83 const TargetRegisterInfo
* TRI
;
84 const TargetInstrInfo
* TII
;
86 const MachineLoopInfo
* Loops
;
88 RegisterClassInfo RegClassInfo
;
90 /// A LaneMask to remember on which subregister live ranges we need to call
91 /// shrinkToUses() later.
94 /// True if the main range of the currently coalesced intervals should be
95 /// checked for smaller live intervals.
98 /// \brief True if the coalescer should aggressively coalesce global copies
99 /// in favor of keeping local copies.
100 bool JoinGlobalCopies
;
102 /// \brief True if the coalescer should aggressively coalesce fall-thru
103 /// blocks exclusively containing copies.
106 /// Copy instructions yet to be coalesced.
107 SmallVector
<MachineInstr
*, 8> WorkList
;
108 SmallVector
<MachineInstr
*, 8> LocalWorkList
;
110 /// Set of instruction pointers that have been erased, and
111 /// that may be present in WorkList.
112 SmallPtrSet
<MachineInstr
*, 8> ErasedInstrs
;
114 /// Dead instructions that are about to be deleted.
115 SmallVector
<MachineInstr
*, 8> DeadDefs
;
117 /// Virtual registers to be considered for register class inflation.
118 SmallVector
<unsigned, 8> InflateRegs
;
120 /// Recursively eliminate dead defs in DeadDefs.
121 void eliminateDeadDefs();
123 /// LiveRangeEdit callback.
124 void LRE_WillEraseInstruction(MachineInstr
*MI
) override
;
126 /// Coalesce the LocalWorkList.
127 void coalesceLocals();
129 /// Join compatible live intervals
130 void joinAllIntervals();
132 /// Coalesce copies in the specified MBB, putting
133 /// copies that cannot yet be coalesced into WorkList.
134 void copyCoalesceInMBB(MachineBasicBlock
*MBB
);
136 /// Try to coalesce all copies in CurrList. Return
137 /// true if any progress was made.
138 bool copyCoalesceWorkList(MutableArrayRef
<MachineInstr
*> CurrList
);
140 /// Attempt to join intervals corresponding to SrcReg/DstReg,
141 /// which are the src/dst of the copy instruction CopyMI. This returns
142 /// true if the copy was successfully coalesced away. If it is not
143 /// currently possible to coalesce this interval, but it may be possible if
144 /// other things get coalesced, then it returns true by reference in
146 bool joinCopy(MachineInstr
*TheCopy
, bool &Again
);
148 /// Attempt to join these two intervals. On failure, this
149 /// returns false. The output "SrcInt" will not have been modified, so we
150 /// can use this information below to update aliases.
151 bool joinIntervals(CoalescerPair
&CP
);
153 /// Attempt joining two virtual registers. Return true on success.
154 bool joinVirtRegs(CoalescerPair
&CP
);
156 /// Attempt joining with a reserved physreg.
157 bool joinReservedPhysReg(CoalescerPair
&CP
);
159 /// Add the LiveRange @p ToMerge as a subregister liverange of @p LI.
160 /// Subranges in @p LI which only partially interfere with the desired
161 /// LaneMask are split as necessary. @p LaneMask are the lanes that
162 /// @p ToMerge will occupy in the coalescer register. @p LI has its subrange
163 /// lanemasks already adjusted to the coalesced register.
164 void mergeSubRangeInto(LiveInterval
&LI
, const LiveRange
&ToMerge
,
165 unsigned LaneMask
, CoalescerPair
&CP
);
167 /// Join the liveranges of two subregisters. Joins @p RRange into
168 /// @p LRange, @p RRange may be invalid afterwards.
169 void joinSubRegRanges(LiveRange
&LRange
, LiveRange
&RRange
,
170 unsigned LaneMask
, const CoalescerPair
&CP
);
172 /// We found a non-trivially-coalescable copy. If
173 /// the source value number is defined by a copy from the destination reg
174 /// see if we can merge these two destination reg valno# into a single
175 /// value number, eliminating a copy.
176 bool adjustCopiesBackFrom(const CoalescerPair
&CP
, MachineInstr
*CopyMI
);
178 /// Return true if there are definitions of IntB
179 /// other than BValNo val# that can reach uses of AValno val# of IntA.
180 bool hasOtherReachingDefs(LiveInterval
&IntA
, LiveInterval
&IntB
,
181 VNInfo
*AValNo
, VNInfo
*BValNo
);
183 /// We found a non-trivially-coalescable copy.
184 /// If the source value number is defined by a commutable instruction and
185 /// its other operand is coalesced to the copy dest register, see if we
186 /// can transform the copy into a noop by commuting the definition.
187 bool removeCopyByCommutingDef(const CoalescerPair
&CP
,MachineInstr
*CopyMI
);
189 /// If the source of a copy is defined by a
190 /// trivial computation, replace the copy by rematerialize the definition.
191 bool reMaterializeTrivialDef(CoalescerPair
&CP
, MachineInstr
*CopyMI
,
194 /// Return true if a physreg copy should be joined.
195 bool canJoinPhys(const CoalescerPair
&CP
);
197 /// Replace all defs and uses of SrcReg to DstReg and
198 /// update the subregister number if it is not zero. If DstReg is a
199 /// physical register and the existing subregister number of the def / use
200 /// being updated is not zero, make sure to set it to the correct physical
202 void updateRegDefsUses(unsigned SrcReg
, unsigned DstReg
, unsigned SubIdx
);
204 /// Handle copies of undef values.
205 bool eliminateUndefCopy(MachineInstr
*CopyMI
);
208 static char ID
; // Class identification, replacement for typeinfo
209 RegisterCoalescer() : MachineFunctionPass(ID
) {
210 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
213 void getAnalysisUsage(AnalysisUsage
&AU
) const override
;
215 void releaseMemory() override
;
217 /// This is the pass entry point.
218 bool runOnMachineFunction(MachineFunction
&) override
;
220 /// Implement the dump method.
221 void print(raw_ostream
&O
, const Module
* = nullptr) const override
;
223 } /// end anonymous namespace
225 char &llvm::RegisterCoalescerID
= RegisterCoalescer::ID
;
227 INITIALIZE_PASS_BEGIN(RegisterCoalescer
, "simple-register-coalescing",
228 "Simple Register Coalescing", false, false)
229 INITIALIZE_PASS_DEPENDENCY(LiveIntervals
)
230 INITIALIZE_PASS_DEPENDENCY(SlotIndexes
)
231 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo
)
232 INITIALIZE_AG_DEPENDENCY(AliasAnalysis
)
233 INITIALIZE_PASS_END(RegisterCoalescer
, "simple-register-coalescing",
234 "Simple Register Coalescing", false, false)
236 char RegisterCoalescer::ID
= 0;
238 static bool isMoveInstr(const TargetRegisterInfo
&tri
, const MachineInstr
*MI
,
239 unsigned &Src
, unsigned &Dst
,
240 unsigned &SrcSub
, unsigned &DstSub
) {
242 Dst
= MI
->getOperand(0).getReg();
243 DstSub
= MI
->getOperand(0).getSubReg();
244 Src
= MI
->getOperand(1).getReg();
245 SrcSub
= MI
->getOperand(1).getSubReg();
246 } else if (MI
->isSubregToReg()) {
247 Dst
= MI
->getOperand(0).getReg();
248 DstSub
= tri
.composeSubRegIndices(MI
->getOperand(0).getSubReg(),
249 MI
->getOperand(3).getImm());
250 Src
= MI
->getOperand(2).getReg();
251 SrcSub
= MI
->getOperand(2).getSubReg();
257 // Return true if this block should be vacated by the coalescer to eliminate
258 // branches. The important cases to handle in the coalescer are critical edges
259 // split during phi elimination which contain only copies. Simple blocks that
260 // contain non-branches should also be vacated, but this can be handled by an
261 // earlier pass similar to early if-conversion.
262 static bool isSplitEdge(const MachineBasicBlock
*MBB
) {
263 if (MBB
->pred_size() != 1 || MBB
->succ_size() != 1)
266 for (const auto &MI
: *MBB
) {
267 if (!MI
.isCopyLike() && !MI
.isUnconditionalBranch())
273 bool CoalescerPair::setRegisters(const MachineInstr
*MI
) {
277 Flipped
= CrossClass
= false;
279 unsigned Src
, Dst
, SrcSub
, DstSub
;
280 if (!isMoveInstr(TRI
, MI
, Src
, Dst
, SrcSub
, DstSub
))
282 Partial
= SrcSub
|| DstSub
;
284 // If one register is a physreg, it must be Dst.
285 if (TargetRegisterInfo::isPhysicalRegister(Src
)) {
286 if (TargetRegisterInfo::isPhysicalRegister(Dst
))
289 std::swap(SrcSub
, DstSub
);
293 const MachineRegisterInfo
&MRI
= MI
->getParent()->getParent()->getRegInfo();
295 if (TargetRegisterInfo::isPhysicalRegister(Dst
)) {
296 // Eliminate DstSub on a physreg.
298 Dst
= TRI
.getSubReg(Dst
, DstSub
);
299 if (!Dst
) return false;
303 // Eliminate SrcSub by picking a corresponding Dst superregister.
305 Dst
= TRI
.getMatchingSuperReg(Dst
, SrcSub
, MRI
.getRegClass(Src
));
306 if (!Dst
) return false;
307 } else if (!MRI
.getRegClass(Src
)->contains(Dst
)) {
311 // Both registers are virtual.
312 const TargetRegisterClass
*SrcRC
= MRI
.getRegClass(Src
);
313 const TargetRegisterClass
*DstRC
= MRI
.getRegClass(Dst
);
315 // Both registers have subreg indices.
316 if (SrcSub
&& DstSub
) {
317 // Copies between different sub-registers are never coalescable.
318 if (Src
== Dst
&& SrcSub
!= DstSub
)
321 NewRC
= TRI
.getCommonSuperRegClass(SrcRC
, SrcSub
, DstRC
, DstSub
,
326 // SrcReg will be merged with a sub-register of DstReg.
328 NewRC
= TRI
.getMatchingSuperRegClass(DstRC
, SrcRC
, DstSub
);
330 // DstReg will be merged with a sub-register of SrcReg.
332 NewRC
= TRI
.getMatchingSuperRegClass(SrcRC
, DstRC
, SrcSub
);
334 // This is a straight copy without sub-registers.
335 NewRC
= TRI
.getCommonSubClass(DstRC
, SrcRC
);
338 // The combined constraint may be impossible to satisfy.
342 // Prefer SrcReg to be a sub-register of DstReg.
343 // FIXME: Coalescer should support subregs symmetrically.
344 if (DstIdx
&& !SrcIdx
) {
346 std::swap(SrcIdx
, DstIdx
);
350 CrossClass
= NewRC
!= DstRC
|| NewRC
!= SrcRC
;
352 // Check our invariants
353 assert(TargetRegisterInfo::isVirtualRegister(Src
) && "Src must be virtual");
354 assert(!(TargetRegisterInfo::isPhysicalRegister(Dst
) && DstSub
) &&
355 "Cannot have a physical SubIdx");
361 bool CoalescerPair::flip() {
362 if (TargetRegisterInfo::isPhysicalRegister(DstReg
))
364 std::swap(SrcReg
, DstReg
);
365 std::swap(SrcIdx
, DstIdx
);
370 bool CoalescerPair::isCoalescable(const MachineInstr
*MI
) const {
373 unsigned Src
, Dst
, SrcSub
, DstSub
;
374 if (!isMoveInstr(TRI
, MI
, Src
, Dst
, SrcSub
, DstSub
))
377 // Find the virtual register that is SrcReg.
380 std::swap(SrcSub
, DstSub
);
381 } else if (Src
!= SrcReg
) {
385 // Now check that Dst matches DstReg.
386 if (TargetRegisterInfo::isPhysicalRegister(DstReg
)) {
387 if (!TargetRegisterInfo::isPhysicalRegister(Dst
))
389 assert(!DstIdx
&& !SrcIdx
&& "Inconsistent CoalescerPair state.");
390 // DstSub could be set for a physreg from INSERT_SUBREG.
392 Dst
= TRI
.getSubReg(Dst
, DstSub
);
395 return DstReg
== Dst
;
396 // This is a partial register copy. Check that the parts match.
397 return TRI
.getSubReg(DstReg
, SrcSub
) == Dst
;
399 // DstReg is virtual.
402 // Registers match, do the subregisters line up?
403 return TRI
.composeSubRegIndices(SrcIdx
, SrcSub
) ==
404 TRI
.composeSubRegIndices(DstIdx
, DstSub
);
408 void RegisterCoalescer::getAnalysisUsage(AnalysisUsage
&AU
) const {
409 AU
.setPreservesCFG();
410 AU
.addRequired
<AliasAnalysis
>();
411 AU
.addRequired
<LiveIntervals
>();
412 AU
.addPreserved
<LiveIntervals
>();
413 AU
.addPreserved
<SlotIndexes
>();
414 AU
.addRequired
<MachineLoopInfo
>();
415 AU
.addPreserved
<MachineLoopInfo
>();
416 AU
.addPreservedID(MachineDominatorsID
);
417 MachineFunctionPass::getAnalysisUsage(AU
);
420 void RegisterCoalescer::eliminateDeadDefs() {
421 SmallVector
<unsigned, 8> NewRegs
;
422 LiveRangeEdit(nullptr, NewRegs
, *MF
, *LIS
,
423 nullptr, this).eliminateDeadDefs(DeadDefs
);
426 // Callback from eliminateDeadDefs().
427 void RegisterCoalescer::LRE_WillEraseInstruction(MachineInstr
*MI
) {
428 // MI may be in WorkList. Make sure we don't visit it.
429 ErasedInstrs
.insert(MI
);
432 /// We found a non-trivially-coalescable copy with IntA
433 /// being the source and IntB being the dest, thus this defines a value number
434 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
435 /// see if we can merge these two pieces of B into a single value number,
436 /// eliminating a copy. For example:
440 /// B1 = A3 <- this copy
442 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
443 /// value number to be replaced with B0 (which simplifies the B liveinterval).
445 /// This returns true if an interval was modified.
447 bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair
&CP
,
448 MachineInstr
*CopyMI
) {
449 assert(!CP
.isPartial() && "This doesn't work for partial copies.");
450 assert(!CP
.isPhys() && "This doesn't work for physreg copies.");
453 LIS
->getInterval(CP
.isFlipped() ? CP
.getDstReg() : CP
.getSrcReg());
455 LIS
->getInterval(CP
.isFlipped() ? CP
.getSrcReg() : CP
.getDstReg());
456 SlotIndex CopyIdx
= LIS
->getInstructionIndex(CopyMI
).getRegSlot();
458 // BValNo is a value number in B that is defined by a copy from A. 'B1' in
459 // the example above.
460 LiveInterval::iterator BS
= IntB
.FindSegmentContaining(CopyIdx
);
461 if (BS
== IntB
.end()) return false;
462 VNInfo
*BValNo
= BS
->valno
;
464 // Get the location that B is defined at. Two options: either this value has
465 // an unknown definition point or it is defined at CopyIdx. If unknown, we
467 if (BValNo
->def
!= CopyIdx
) return false;
469 // AValNo is the value number in A that defines the copy, A3 in the example.
470 SlotIndex CopyUseIdx
= CopyIdx
.getRegSlot(true);
471 LiveInterval::iterator AS
= IntA
.FindSegmentContaining(CopyUseIdx
);
472 // The live segment might not exist after fun with physreg coalescing.
473 if (AS
== IntA
.end()) return false;
474 VNInfo
*AValNo
= AS
->valno
;
476 // If AValNo is defined as a copy from IntB, we can potentially process this.
477 // Get the instruction that defines this value number.
478 MachineInstr
*ACopyMI
= LIS
->getInstructionFromIndex(AValNo
->def
);
479 // Don't allow any partial copies, even if isCoalescable() allows them.
480 if (!CP
.isCoalescable(ACopyMI
) || !ACopyMI
->isFullCopy())
483 // Get the Segment in IntB that this value number starts with.
484 LiveInterval::iterator ValS
=
485 IntB
.FindSegmentContaining(AValNo
->def
.getPrevSlot());
486 if (ValS
== IntB
.end())
489 // Make sure that the end of the live segment is inside the same block as
491 MachineInstr
*ValSEndInst
=
492 LIS
->getInstructionFromIndex(ValS
->end
.getPrevSlot());
493 if (!ValSEndInst
|| ValSEndInst
->getParent() != CopyMI
->getParent())
496 // Okay, we now know that ValS ends in the same block that the CopyMI
497 // live-range starts. If there are no intervening live segments between them
498 // in IntB, we can merge them.
499 if (ValS
+1 != BS
) return false;
501 DEBUG(dbgs() << "Extending: " << PrintReg(IntB
.reg
, TRI
));
503 SlotIndex FillerStart
= ValS
->end
, FillerEnd
= BS
->start
;
504 // We are about to delete CopyMI, so need to remove it as the 'instruction
505 // that defines this value #'. Update the valnum with the new defining
507 BValNo
->def
= FillerStart
;
509 // Okay, we can merge them. We need to insert a new liverange:
510 // [ValS.end, BS.begin) of either value number, then we merge the
511 // two value numbers.
512 IntB
.addSegment(LiveInterval::Segment(FillerStart
, FillerEnd
, BValNo
));
514 // Okay, merge "B1" into the same value number as "B0".
515 if (BValNo
!= ValS
->valno
)
516 IntB
.MergeValueNumberInto(BValNo
, ValS
->valno
);
518 // Do the same for the subregister segments.
519 for (LiveInterval::SubRange
&S
: IntB
.subranges()) {
520 VNInfo
*SubBValNo
= S
.getVNInfoAt(CopyIdx
);
521 S
.addSegment(LiveInterval::Segment(FillerStart
, FillerEnd
, SubBValNo
));
522 VNInfo
*SubValSNo
= S
.getVNInfoAt(AValNo
->def
.getPrevSlot());
523 if (SubBValNo
!= SubValSNo
)
524 S
.MergeValueNumberInto(SubBValNo
, SubValSNo
);
527 DEBUG(dbgs() << " result = " << IntB
<< '\n');
529 // If the source instruction was killing the source register before the
530 // merge, unset the isKill marker given the live range has been extended.
531 int UIdx
= ValSEndInst
->findRegisterUseOperandIdx(IntB
.reg
, true);
533 ValSEndInst
->getOperand(UIdx
).setIsKill(false);
536 // Rewrite the copy. If the copy instruction was killing the destination
537 // register before the merge, find the last use and trim the live range. That
538 // will also add the isKill marker.
539 CopyMI
->substituteRegister(IntA
.reg
, IntB
.reg
, 0, *TRI
);
540 if (AS
->end
== CopyIdx
)
541 LIS
->shrinkToUses(&IntA
);
547 /// Return true if there are definitions of IntB
548 /// other than BValNo val# that can reach uses of AValno val# of IntA.
549 bool RegisterCoalescer::hasOtherReachingDefs(LiveInterval
&IntA
,
553 // If AValNo has PHI kills, conservatively assume that IntB defs can reach
555 if (LIS
->hasPHIKill(IntA
, AValNo
))
558 for (LiveRange::Segment
&ASeg
: IntA
.segments
) {
559 if (ASeg
.valno
!= AValNo
) continue;
560 LiveInterval::iterator BI
=
561 std::upper_bound(IntB
.begin(), IntB
.end(), ASeg
.start
);
562 if (BI
!= IntB
.begin())
564 for (; BI
!= IntB
.end() && ASeg
.end
>= BI
->start
; ++BI
) {
565 if (BI
->valno
== BValNo
)
567 if (BI
->start
<= ASeg
.start
&& BI
->end
> ASeg
.start
)
569 if (BI
->start
> ASeg
.start
&& BI
->start
< ASeg
.end
)
576 /// Copy segements with value number @p SrcValNo from liverange @p Src to live
577 /// range @Dst and use value number @p DstValNo there.
578 static void addSegmentsWithValNo(LiveRange
&Dst
, VNInfo
*DstValNo
,
579 const LiveRange
&Src
, const VNInfo
*SrcValNo
)
581 for (const LiveRange::Segment
&S
: Src
.segments
) {
582 if (S
.valno
!= SrcValNo
)
584 Dst
.addSegment(LiveRange::Segment(S
.start
, S
.end
, DstValNo
));
588 /// We found a non-trivially-coalescable copy with
589 /// IntA being the source and IntB being the dest, thus this defines a value
590 /// number in IntB. If the source value number (in IntA) is defined by a
591 /// commutable instruction and its other operand is coalesced to the copy dest
592 /// register, see if we can transform the copy into a noop by commuting the
593 /// definition. For example,
595 /// A3 = op A2 B0<kill>
597 /// B1 = A3 <- this copy
599 /// = op A3 <- more uses
603 /// B2 = op B0 A2<kill>
605 /// B1 = B2 <- now an identity copy
607 /// = op B2 <- more uses
609 /// This returns true if an interval was modified.
611 bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair
&CP
,
612 MachineInstr
*CopyMI
) {
613 assert(!CP
.isPhys());
616 LIS
->getInterval(CP
.isFlipped() ? CP
.getDstReg() : CP
.getSrcReg());
618 LIS
->getInterval(CP
.isFlipped() ? CP
.getSrcReg() : CP
.getDstReg());
620 // BValNo is a value number in B that is defined by a copy from A. 'B1' in
621 // the example above.
622 SlotIndex CopyIdx
= LIS
->getInstructionIndex(CopyMI
).getRegSlot();
623 VNInfo
*BValNo
= IntB
.getVNInfoAt(CopyIdx
);
624 assert(BValNo
!= nullptr && BValNo
->def
== CopyIdx
);
626 // AValNo is the value number in A that defines the copy, A3 in the example.
627 VNInfo
*AValNo
= IntA
.getVNInfoAt(CopyIdx
.getRegSlot(true));
628 assert(AValNo
&& !AValNo
->isUnused() && "COPY source not live");
629 if (AValNo
->isPHIDef())
631 MachineInstr
*DefMI
= LIS
->getInstructionFromIndex(AValNo
->def
);
634 if (!DefMI
->isCommutable())
636 // If DefMI is a two-address instruction then commuting it will change the
637 // destination register.
638 int DefIdx
= DefMI
->findRegisterDefOperandIdx(IntA
.reg
);
639 assert(DefIdx
!= -1);
641 if (!DefMI
->isRegTiedToUseOperand(DefIdx
, &UseOpIdx
))
643 unsigned Op1
, Op2
, NewDstIdx
;
644 if (!TII
->findCommutedOpIndices(DefMI
, Op1
, Op2
))
648 else if (Op2
== UseOpIdx
)
653 MachineOperand
&NewDstMO
= DefMI
->getOperand(NewDstIdx
);
654 unsigned NewReg
= NewDstMO
.getReg();
655 if (NewReg
!= IntB
.reg
|| !IntB
.Query(AValNo
->def
).isKill())
658 // Make sure there are no other definitions of IntB that would reach the
659 // uses which the new definition can reach.
660 if (hasOtherReachingDefs(IntA
, IntB
, AValNo
, BValNo
))
663 // If some of the uses of IntA.reg is already coalesced away, return false.
664 // It's not possible to determine whether it's safe to perform the coalescing.
665 for (MachineOperand
&MO
: MRI
->use_nodbg_operands(IntA
.reg
)) {
666 MachineInstr
*UseMI
= MO
.getParent();
667 unsigned OpNo
= &MO
- &UseMI
->getOperand(0);
668 SlotIndex UseIdx
= LIS
->getInstructionIndex(UseMI
);
669 LiveInterval::iterator US
= IntA
.FindSegmentContaining(UseIdx
);
670 if (US
== IntA
.end() || US
->valno
!= AValNo
)
672 // If this use is tied to a def, we can't rewrite the register.
673 if (UseMI
->isRegTiedToDefOperand(OpNo
))
677 DEBUG(dbgs() << "\tremoveCopyByCommutingDef: " << AValNo
->def
<< '\t'
680 // At this point we have decided that it is legal to do this
681 // transformation. Start by commuting the instruction.
682 MachineBasicBlock
*MBB
= DefMI
->getParent();
683 MachineInstr
*NewMI
= TII
->commuteInstruction(DefMI
);
686 if (TargetRegisterInfo::isVirtualRegister(IntA
.reg
) &&
687 TargetRegisterInfo::isVirtualRegister(IntB
.reg
) &&
688 !MRI
->constrainRegClass(IntB
.reg
, MRI
->getRegClass(IntA
.reg
)))
690 if (NewMI
!= DefMI
) {
691 LIS
->ReplaceMachineInstrInMaps(DefMI
, NewMI
);
692 MachineBasicBlock::iterator Pos
= DefMI
;
693 MBB
->insert(Pos
, NewMI
);
697 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
706 // Update uses of IntA of the specific Val# with IntB.
707 for (MachineRegisterInfo::use_iterator UI
= MRI
->use_begin(IntA
.reg
),
709 UI
!= UE
; /* ++UI is below because of possible MI removal */) {
710 MachineOperand
&UseMO
= *UI
;
714 MachineInstr
*UseMI
= UseMO
.getParent();
715 if (UseMI
->isDebugValue()) {
716 // FIXME These don't have an instruction index. Not clear we have enough
717 // info to decide whether to do this replacement or not. For now do it.
718 UseMO
.setReg(NewReg
);
721 SlotIndex UseIdx
= LIS
->getInstructionIndex(UseMI
).getRegSlot(true);
722 LiveInterval::iterator US
= IntA
.FindSegmentContaining(UseIdx
);
723 assert(US
!= IntA
.end() && "Use must be live");
724 if (US
->valno
!= AValNo
)
726 // Kill flags are no longer accurate. They are recomputed after RA.
727 UseMO
.setIsKill(false);
728 if (TargetRegisterInfo::isPhysicalRegister(NewReg
))
729 UseMO
.substPhysReg(NewReg
, *TRI
);
731 UseMO
.setReg(NewReg
);
734 if (!UseMI
->isCopy())
736 if (UseMI
->getOperand(0).getReg() != IntB
.reg
||
737 UseMI
->getOperand(0).getSubReg())
740 // This copy will become a noop. If it's defining a new val#, merge it into
742 SlotIndex DefIdx
= UseIdx
.getRegSlot();
743 VNInfo
*DVNI
= IntB
.getVNInfoAt(DefIdx
);
746 DEBUG(dbgs() << "\t\tnoop: " << DefIdx
<< '\t' << *UseMI
);
747 assert(DVNI
->def
== DefIdx
);
748 BValNo
= IntB
.MergeValueNumberInto(BValNo
, DVNI
);
749 for (LiveInterval::SubRange
&S
: IntB
.subranges()) {
750 VNInfo
*SubDVNI
= S
.getVNInfoAt(DefIdx
);
753 VNInfo
*SubBValNo
= S
.getVNInfoAt(CopyIdx
);
754 assert(SubBValNo
->def
== CopyIdx
);
755 VNInfo
*Merged
= S
.MergeValueNumberInto(SubBValNo
, SubDVNI
);
756 Merged
->def
= CopyIdx
;
759 ErasedInstrs
.insert(UseMI
);
760 LIS
->RemoveMachineInstrFromMaps(UseMI
);
761 UseMI
->eraseFromParent();
764 // Extend BValNo by merging in IntA live segments of AValNo. Val# definition
766 BumpPtrAllocator
&Allocator
= LIS
->getVNInfoAllocator();
767 if (IntB
.hasSubRanges()) {
768 if (!IntA
.hasSubRanges()) {
769 unsigned Mask
= MRI
->getMaxLaneMaskForVReg(IntA
.reg
);
770 IntA
.createSubRangeFrom(Allocator
, Mask
, IntA
);
772 SlotIndex AIdx
= CopyIdx
.getRegSlot(true);
773 for (LiveInterval::SubRange
&SA
: IntA
.subranges()) {
774 VNInfo
*ASubValNo
= SA
.getVNInfoAt(AIdx
);
775 assert(ASubValNo
!= nullptr);
777 unsigned AMask
= SA
.LaneMask
;
778 for (LiveInterval::SubRange
&SB
: IntB
.subranges()) {
779 unsigned BMask
= SB
.LaneMask
;
780 unsigned Common
= BMask
& AMask
;
785 dbgs() << format("\t\tCopy+Merge %04X into %04X\n", BMask
, Common
));
786 unsigned BRest
= BMask
& ~AMask
;
787 LiveInterval::SubRange
*CommonRange
;
790 DEBUG(dbgs() << format("\t\tReduce Lane to %04X\n", BRest
));
791 // Duplicate SubRange for newly merged common stuff.
792 CommonRange
= IntB
.createSubRangeFrom(Allocator
, Common
, SB
);
794 // We van reuse the L SubRange.
795 SB
.LaneMask
= Common
;
798 LiveRange
RangeCopy(SB
, Allocator
);
800 VNInfo
*BSubValNo
= CommonRange
->getVNInfoAt(CopyIdx
);
801 assert(BSubValNo
->def
== CopyIdx
);
802 BSubValNo
->def
= ASubValNo
->def
;
803 addSegmentsWithValNo(*CommonRange
, BSubValNo
, SA
, ASubValNo
);
807 DEBUG(dbgs() << format("\t\tNew Lane %04X\n", AMask
));
808 LiveRange
*NewRange
= IntB
.createSubRange(Allocator
, AMask
);
809 VNInfo
*BSubValNo
= NewRange
->getNextValue(CopyIdx
, Allocator
);
810 addSegmentsWithValNo(*NewRange
, BSubValNo
, SA
, ASubValNo
);
812 SA
.removeValNo(ASubValNo
);
816 BValNo
->def
= AValNo
->def
;
817 addSegmentsWithValNo(IntB
, BValNo
, IntA
, AValNo
);
818 DEBUG(dbgs() << "\t\textended: " << IntB
<< '\n');
820 IntA
.removeValNo(AValNo
);
821 // Remove valuenos in subranges (the A+B have subranges case has already been
823 if (!IntB
.hasSubRanges()) {
824 SlotIndex AIdx
= CopyIdx
.getRegSlot(true);
825 for (LiveInterval::SubRange
&SA
: IntA
.subranges()) {
826 VNInfo
*ASubValNo
= SA
.getVNInfoAt(AIdx
);
827 assert(ASubValNo
!= nullptr);
828 SA
.removeValNo(ASubValNo
);
831 DEBUG(dbgs() << "\t\ttrimmed: " << IntA
<< '\n');
836 /// If the source of a copy is defined by a trivial
837 /// computation, replace the copy by rematerialize the definition.
838 bool RegisterCoalescer::reMaterializeTrivialDef(CoalescerPair
&CP
,
839 MachineInstr
*CopyMI
,
842 unsigned SrcReg
= CP
.isFlipped() ? CP
.getDstReg() : CP
.getSrcReg();
843 unsigned SrcIdx
= CP
.isFlipped() ? CP
.getDstIdx() : CP
.getSrcIdx();
844 unsigned DstReg
= CP
.isFlipped() ? CP
.getSrcReg() : CP
.getDstReg();
845 unsigned DstIdx
= CP
.isFlipped() ? CP
.getSrcIdx() : CP
.getDstIdx();
846 if (TargetRegisterInfo::isPhysicalRegister(SrcReg
))
849 LiveInterval
&SrcInt
= LIS
->getInterval(SrcReg
);
850 SlotIndex CopyIdx
= LIS
->getInstructionIndex(CopyMI
);
851 VNInfo
*ValNo
= SrcInt
.Query(CopyIdx
).valueIn();
852 assert(ValNo
&& "CopyMI input register not live");
853 if (ValNo
->isPHIDef() || ValNo
->isUnused())
855 MachineInstr
*DefMI
= LIS
->getInstructionFromIndex(ValNo
->def
);
858 if (DefMI
->isCopyLike()) {
862 if (!TII
->isAsCheapAsAMove(DefMI
))
864 if (!TII
->isTriviallyReMaterializable(DefMI
, AA
))
866 bool SawStore
= false;
867 if (!DefMI
->isSafeToMove(TII
, AA
, SawStore
))
869 const MCInstrDesc
&MCID
= DefMI
->getDesc();
870 if (MCID
.getNumDefs() != 1)
872 // Only support subregister destinations when the def is read-undef.
873 MachineOperand
&DstOperand
= CopyMI
->getOperand(0);
874 unsigned CopyDstReg
= DstOperand
.getReg();
875 if (DstOperand
.getSubReg() && !DstOperand
.isUndef())
878 // If both SrcIdx and DstIdx are set, correct rematerialization would widen
879 // the register substantially (beyond both source and dest size). This is bad
880 // for performance since it can cascade through a function, introducing many
881 // extra spills and fills (e.g. ARM can easily end up copying QQQQPR registers
882 // around after a few subreg copies).
883 if (SrcIdx
&& DstIdx
)
886 const TargetRegisterClass
*DefRC
= TII
->getRegClass(MCID
, 0, TRI
, *MF
);
887 if (!DefMI
->isImplicitDef()) {
888 if (TargetRegisterInfo::isPhysicalRegister(DstReg
)) {
889 unsigned NewDstReg
= DstReg
;
891 unsigned NewDstIdx
= TRI
->composeSubRegIndices(CP
.getSrcIdx(),
892 DefMI
->getOperand(0).getSubReg());
894 NewDstReg
= TRI
->getSubReg(DstReg
, NewDstIdx
);
896 // Finally, make sure that the physical subregister that will be
897 // constructed later is permitted for the instruction.
898 if (!DefRC
->contains(NewDstReg
))
901 // Theoretically, some stack frame reference could exist. Just make sure
902 // it hasn't actually happened.
903 assert(TargetRegisterInfo::isVirtualRegister(DstReg
) &&
904 "Only expect to deal with virtual or physical registers");
908 MachineBasicBlock
*MBB
= CopyMI
->getParent();
909 MachineBasicBlock::iterator MII
=
910 std::next(MachineBasicBlock::iterator(CopyMI
));
911 TII
->reMaterialize(*MBB
, MII
, DstReg
, SrcIdx
, DefMI
, *TRI
);
912 MachineInstr
*NewMI
= std::prev(MII
);
914 LIS
->ReplaceMachineInstrInMaps(CopyMI
, NewMI
);
915 CopyMI
->eraseFromParent();
916 ErasedInstrs
.insert(CopyMI
);
918 // NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86).
919 // We need to remember these so we can add intervals once we insert
920 // NewMI into SlotIndexes.
921 SmallVector
<unsigned, 4> NewMIImplDefs
;
922 for (unsigned i
= NewMI
->getDesc().getNumOperands(),
923 e
= NewMI
->getNumOperands(); i
!= e
; ++i
) {
924 MachineOperand
&MO
= NewMI
->getOperand(i
);
926 assert(MO
.isDef() && MO
.isImplicit() && MO
.isDead() &&
927 TargetRegisterInfo::isPhysicalRegister(MO
.getReg()));
928 NewMIImplDefs
.push_back(MO
.getReg());
932 if (TargetRegisterInfo::isVirtualRegister(DstReg
)) {
933 const TargetRegisterClass
*NewRC
= CP
.getNewRC();
934 unsigned NewIdx
= NewMI
->getOperand(0).getSubReg();
937 NewRC
= TRI
->getMatchingSuperRegClass(NewRC
, DefRC
, NewIdx
);
939 NewRC
= TRI
->getCommonSubClass(NewRC
, DefRC
);
941 assert(NewRC
&& "subreg chosen for remat incompatible with instruction");
942 MRI
->setRegClass(DstReg
, NewRC
);
944 updateRegDefsUses(DstReg
, DstReg
, DstIdx
);
945 NewMI
->getOperand(0).setSubReg(NewIdx
);
946 } else if (NewMI
->getOperand(0).getReg() != CopyDstReg
) {
947 // The New instruction may be defining a sub-register of what's actually
948 // been asked for. If so it must implicitly define the whole thing.
949 assert(TargetRegisterInfo::isPhysicalRegister(DstReg
) &&
950 "Only expect virtual or physical registers in remat");
951 NewMI
->getOperand(0).setIsDead(true);
952 NewMI
->addOperand(MachineOperand::CreateReg(CopyDstReg
,
956 // Record small dead def live-ranges for all the subregisters
957 // of the destination register.
958 // Otherwise, variables that live through may miss some
959 // interferences, thus creating invalid allocation.
961 // vreg1 = somedef ; vreg1 GR8
962 // vreg2 = remat ; vreg2 GR32
963 // CL = COPY vreg2.sub_8bit
964 // = somedef vreg1 ; vreg1 GR8
966 // vreg1 = somedef ; vreg1 GR8
967 // ECX<def, dead> = remat ; CL<imp-def>
968 // = somedef vreg1 ; vreg1 GR8
969 // vreg1 will see the inteferences with CL but not with CH since
970 // no live-ranges would have been created for ECX.
972 SlotIndex NewMIIdx
= LIS
->getInstructionIndex(NewMI
);
973 for (MCRegUnitIterator
Units(NewMI
->getOperand(0).getReg(), TRI
);
974 Units
.isValid(); ++Units
)
975 if (LiveRange
*LR
= LIS
->getCachedRegUnit(*Units
))
976 LR
->createDeadDef(NewMIIdx
.getRegSlot(), LIS
->getVNInfoAllocator());
979 if (NewMI
->getOperand(0).getSubReg())
980 NewMI
->getOperand(0).setIsUndef();
982 // CopyMI may have implicit operands, transfer them over to the newly
983 // rematerialized instruction. And update implicit def interval valnos.
984 for (unsigned i
= CopyMI
->getDesc().getNumOperands(),
985 e
= CopyMI
->getNumOperands(); i
!= e
; ++i
) {
986 MachineOperand
&MO
= CopyMI
->getOperand(i
);
988 assert(MO
.isImplicit() && "No explicit operands after implict operands.");
989 // Discard VReg implicit defs.
990 if (TargetRegisterInfo::isPhysicalRegister(MO
.getReg())) {
991 NewMI
->addOperand(MO
);
996 SlotIndex NewMIIdx
= LIS
->getInstructionIndex(NewMI
);
997 for (unsigned i
= 0, e
= NewMIImplDefs
.size(); i
!= e
; ++i
) {
998 unsigned Reg
= NewMIImplDefs
[i
];
999 for (MCRegUnitIterator
Units(Reg
, TRI
); Units
.isValid(); ++Units
)
1000 if (LiveRange
*LR
= LIS
->getCachedRegUnit(*Units
))
1001 LR
->createDeadDef(NewMIIdx
.getRegSlot(), LIS
->getVNInfoAllocator());
1004 DEBUG(dbgs() << "Remat: " << *NewMI
);
1007 // The source interval can become smaller because we removed a use.
1008 LIS
->shrinkToUses(&SrcInt
, &DeadDefs
);
1009 if (!DeadDefs
.empty()) {
1010 // If the virtual SrcReg is completely eliminated, update all DBG_VALUEs
1011 // to describe DstReg instead.
1012 for (MachineOperand
&UseMO
: MRI
->use_operands(SrcReg
)) {
1013 MachineInstr
*UseMI
= UseMO
.getParent();
1014 if (UseMI
->isDebugValue()) {
1015 UseMO
.setReg(DstReg
);
1016 DEBUG(dbgs() << "\t\tupdated: " << *UseMI
);
1019 eliminateDeadDefs();
1025 static void removeUndefValue(LiveRange
&LR
, SlotIndex At
)
1027 VNInfo
*VNInfo
= LR
.getVNInfoAt(At
);
1028 assert(VNInfo
!= nullptr && SlotIndex::isSameInstr(VNInfo
->def
, At
));
1029 LR
.removeValNo(VNInfo
);
1032 /// ProcessImpicitDefs may leave some copies of <undef>
1033 /// values, it only removes local variables. When we have a copy like:
1035 /// %vreg1 = COPY %vreg2<undef>
1037 /// We delete the copy and remove the corresponding value number from %vreg1.
1038 /// Any uses of that value number are marked as <undef>.
1039 bool RegisterCoalescer::eliminateUndefCopy(MachineInstr
*CopyMI
) {
1040 // Note that we do not query CoalescerPair here but redo isMoveInstr as the
1041 // CoalescerPair may have a new register class with adjusted subreg indices
1043 unsigned SrcReg
, DstReg
, SrcSubIdx
, DstSubIdx
;
1044 isMoveInstr(*TRI
, CopyMI
, SrcReg
, DstReg
, SrcSubIdx
, DstSubIdx
);
1046 SlotIndex Idx
= LIS
->getInstructionIndex(CopyMI
);
1047 const LiveInterval
&SrcLI
= LIS
->getInterval(SrcReg
);
1048 // CopyMI is undef iff SrcReg is not live before the instruction.
1049 if (SrcSubIdx
!= 0 && SrcLI
.hasSubRanges()) {
1050 unsigned SrcMask
= TRI
->getSubRegIndexLaneMask(SrcSubIdx
);
1051 for (const LiveInterval::SubRange
&SR
: SrcLI
.subranges()) {
1052 if ((SR
.LaneMask
& SrcMask
) == 0)
1057 } else if (SrcLI
.liveAt(Idx
))
1060 DEBUG(dbgs() << "\tEliminating copy of <undef> value\n");
1062 // Remove any DstReg segments starting at the instruction.
1063 LiveInterval
&DstLI
= LIS
->getInterval(DstReg
);
1064 unsigned DstMask
= TRI
->getSubRegIndexLaneMask(DstSubIdx
);
1065 SlotIndex RegIndex
= Idx
.getRegSlot();
1066 for (LiveInterval::SubRange
&SR
: DstLI
.subranges()) {
1067 if ((SR
.LaneMask
& DstMask
) == 0)
1069 removeUndefValue(SR
, RegIndex
);
1071 DstLI
.removeEmptySubRanges();
1073 // Remove value or merge with previous one in case of a subregister def.
1074 if (VNInfo
*PrevVNI
= DstLI
.getVNInfoAt(Idx
)) {
1075 VNInfo
*VNInfo
= DstLI
.getVNInfoAt(RegIndex
);
1076 DstLI
.MergeValueNumberInto(VNInfo
, PrevVNI
);
1078 removeUndefValue(DstLI
, RegIndex
);
1081 // Mark uses as undef.
1082 for (MachineOperand
&MO
: MRI
->reg_nodbg_operands(DstReg
)) {
1083 if (MO
.isDef() /*|| MO.isUndef()*/)
1085 const MachineInstr
&MI
= *MO
.getParent();
1086 SlotIndex UseIdx
= LIS
->getInstructionIndex(&MI
);
1087 unsigned UseMask
= TRI
->getSubRegIndexLaneMask(MO
.getSubReg());
1089 if (UseMask
!= ~0u && DstLI
.hasSubRanges()) {
1091 for (const LiveInterval::SubRange
&SR
: DstLI
.subranges()) {
1092 if ((SR
.LaneMask
& UseMask
) == 0)
1094 if (SR
.liveAt(UseIdx
)) {
1100 isLive
= DstLI
.liveAt(UseIdx
);
1103 MO
.setIsUndef(true);
1104 DEBUG(dbgs() << "\tnew undef: " << UseIdx
<< '\t' << MI
);
1109 /// Replace all defs and uses of SrcReg to DstReg and update the subregister
1110 /// number if it is not zero. If DstReg is a physical register and the existing
1111 /// subregister number of the def / use being updated is not zero, make sure to
1112 /// set it to the correct physical subregister.
1113 void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg
,
1116 bool DstIsPhys
= TargetRegisterInfo::isPhysicalRegister(DstReg
);
1117 LiveInterval
*DstInt
= DstIsPhys
? nullptr : &LIS
->getInterval(DstReg
);
1119 SmallPtrSet
<MachineInstr
*, 8> Visited
;
1120 for (MachineRegisterInfo::reg_instr_iterator
1121 I
= MRI
->reg_instr_begin(SrcReg
), E
= MRI
->reg_instr_end();
1123 MachineInstr
*UseMI
= &*(I
++);
1125 // Each instruction can only be rewritten once because sub-register
1126 // composition is not always idempotent. When SrcReg != DstReg, rewriting
1127 // the UseMI operands removes them from the SrcReg use-def chain, but when
1128 // SrcReg is DstReg we could encounter UseMI twice if it has multiple
1129 // operands mentioning the virtual register.
1130 if (SrcReg
== DstReg
&& !Visited
.insert(UseMI
).second
)
1133 SmallVector
<unsigned,8> Ops
;
1135 std::tie(Reads
, Writes
) = UseMI
->readsWritesVirtualRegister(SrcReg
, &Ops
);
1137 // If SrcReg wasn't read, it may still be the case that DstReg is live-in
1138 // because SrcReg is a sub-register.
1139 if (DstInt
&& !Reads
&& SubIdx
)
1140 Reads
= DstInt
->liveAt(LIS
->getInstructionIndex(UseMI
));
1142 // Replace SrcReg with DstReg in all UseMI operands.
1143 for (unsigned i
= 0, e
= Ops
.size(); i
!= e
; ++i
) {
1144 MachineOperand
&MO
= UseMI
->getOperand(Ops
[i
]);
1146 // Adjust <undef> flags in case of sub-register joins. We don't want to
1147 // turn a full def into a read-modify-write sub-register def and vice
1149 if (SubIdx
&& MO
.isDef())
1150 MO
.setIsUndef(!Reads
);
1152 // A subreg use of a partially undef (super) register may be a complete
1153 // undef use now and then has to be marked that way.
1154 if (SubIdx
!= 0 && MO
.isUse() && MRI
->tracksSubRegLiveness()) {
1155 if (!DstInt
->hasSubRanges()) {
1156 BumpPtrAllocator
&Allocator
= LIS
->getVNInfoAllocator();
1157 unsigned Mask
= MRI
->getMaxLaneMaskForVReg(DstInt
->reg
);
1158 DstInt
->createSubRangeFrom(Allocator
, Mask
, *DstInt
);
1160 unsigned Mask
= TRI
->getSubRegIndexLaneMask(SubIdx
);
1161 bool IsUndef
= true;
1162 SlotIndex MIIdx
= UseMI
->isDebugValue()
1163 ? LIS
->getSlotIndexes()->getIndexBefore(UseMI
)
1164 : LIS
->getInstructionIndex(UseMI
);
1165 SlotIndex UseIdx
= MIIdx
.getRegSlot(true);
1166 for (LiveInterval::SubRange
&S
: DstInt
->subranges()) {
1167 if ((S
.LaneMask
& Mask
) == 0)
1169 if (S
.liveAt(UseIdx
)) {
1175 MO
.setIsUndef(true);
1176 // We found out some subregister use is actually reading an undefined
1177 // value. In some cases the whole vreg has become undefined at this
1178 // point so we have to potentially shrink the main range if the
1179 // use was ending a live segment there.
1180 LiveQueryResult Q
= DstInt
->Query(MIIdx
);
1181 if (Q
.valueOut() == nullptr)
1182 ShrinkMainRange
= true;
1187 MO
.substPhysReg(DstReg
, *TRI
);
1189 MO
.substVirtReg(DstReg
, SubIdx
, *TRI
);
1193 dbgs() << "\t\tupdated: ";
1194 if (!UseMI
->isDebugValue())
1195 dbgs() << LIS
->getInstructionIndex(UseMI
) << "\t";
1201 /// Return true if a copy involving a physreg should be joined.
1202 bool RegisterCoalescer::canJoinPhys(const CoalescerPair
&CP
) {
1203 /// Always join simple intervals that are defined by a single copy from a
1204 /// reserved register. This doesn't increase register pressure, so it is
1205 /// always beneficial.
1206 if (!MRI
->isReserved(CP
.getDstReg())) {
1207 DEBUG(dbgs() << "\tCan only merge into reserved registers.\n");
1211 LiveInterval
&JoinVInt
= LIS
->getInterval(CP
.getSrcReg());
1212 if (CP
.isFlipped() && JoinVInt
.containsOneValue())
1215 DEBUG(dbgs() << "\tCannot join defs into reserved register.\n");
1219 /// Attempt to join intervals corresponding to SrcReg/DstReg,
1220 /// which are the src/dst of the copy instruction CopyMI. This returns true
1221 /// if the copy was successfully coalesced away. If it is not currently
1222 /// possible to coalesce this interval, but it may be possible if other
1223 /// things get coalesced, then it returns true by reference in 'Again'.
1224 bool RegisterCoalescer::joinCopy(MachineInstr
*CopyMI
, bool &Again
) {
1227 DEBUG(dbgs() << LIS
->getInstructionIndex(CopyMI
) << '\t' << *CopyMI
);
1229 CoalescerPair
CP(*TRI
);
1230 if (!CP
.setRegisters(CopyMI
)) {
1231 DEBUG(dbgs() << "\tNot coalescable.\n");
1235 if (CP
.getNewRC()) {
1236 auto SrcRC
= MRI
->getRegClass(CP
.getSrcReg());
1237 auto DstRC
= MRI
->getRegClass(CP
.getDstReg());
1238 unsigned SrcIdx
= CP
.getSrcIdx();
1239 unsigned DstIdx
= CP
.getDstIdx();
1240 if (CP
.isFlipped()) {
1241 std::swap(SrcIdx
, DstIdx
);
1242 std::swap(SrcRC
, DstRC
);
1244 if (!TRI
->shouldCoalesce(CopyMI
, SrcRC
, SrcIdx
, DstRC
, DstIdx
,
1246 DEBUG(dbgs() << "\tSubtarget bailed on coalescing.\n");
1251 // Dead code elimination. This really should be handled by MachineDCE, but
1252 // sometimes dead copies slip through, and we can't generate invalid live
1254 if (!CP
.isPhys() && CopyMI
->allDefsAreDead()) {
1255 DEBUG(dbgs() << "\tCopy is dead.\n");
1256 DeadDefs
.push_back(CopyMI
);
1257 eliminateDeadDefs();
1261 // Eliminate undefs.
1262 if (!CP
.isPhys() && eliminateUndefCopy(CopyMI
)) {
1263 LIS
->RemoveMachineInstrFromMaps(CopyMI
);
1264 CopyMI
->eraseFromParent();
1265 return false; // Not coalescable.
1268 // Coalesced copies are normally removed immediately, but transformations
1269 // like removeCopyByCommutingDef() can inadvertently create identity copies.
1270 // When that happens, just join the values and remove the copy.
1271 if (CP
.getSrcReg() == CP
.getDstReg()) {
1272 LiveInterval
&LI
= LIS
->getInterval(CP
.getSrcReg());
1273 DEBUG(dbgs() << "\tCopy already coalesced: " << LI
<< '\n');
1274 const SlotIndex CopyIdx
= LIS
->getInstructionIndex(CopyMI
);
1275 LiveQueryResult LRQ
= LI
.Query(CopyIdx
);
1276 if (VNInfo
*DefVNI
= LRQ
.valueDefined()) {
1277 VNInfo
*ReadVNI
= LRQ
.valueIn();
1278 assert(ReadVNI
&& "No value before copy and no <undef> flag.");
1279 assert(ReadVNI
!= DefVNI
&& "Cannot read and define the same value.");
1280 LI
.MergeValueNumberInto(DefVNI
, ReadVNI
);
1282 // Process subregister liveranges.
1283 for (LiveInterval::SubRange
&S
: LI
.subranges()) {
1284 LiveQueryResult SLRQ
= S
.Query(CopyIdx
);
1285 if (VNInfo
*SDefVNI
= SLRQ
.valueDefined()) {
1286 VNInfo
*SReadVNI
= SLRQ
.valueIn();
1287 S
.MergeValueNumberInto(SDefVNI
, SReadVNI
);
1290 DEBUG(dbgs() << "\tMerged values: " << LI
<< '\n');
1292 LIS
->RemoveMachineInstrFromMaps(CopyMI
);
1293 CopyMI
->eraseFromParent();
1297 // Enforce policies.
1299 DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP
.getSrcReg(), TRI
)
1300 << " with " << PrintReg(CP
.getDstReg(), TRI
, CP
.getSrcIdx())
1302 if (!canJoinPhys(CP
)) {
1303 // Before giving up coalescing, if definition of source is defined by
1304 // trivial computation, try rematerializing it.
1306 if (reMaterializeTrivialDef(CP
, CopyMI
, IsDefCopy
))
1309 Again
= true; // May be possible to coalesce later.
1313 // When possible, let DstReg be the larger interval.
1314 if (!CP
.isPartial() && LIS
->getInterval(CP
.getSrcReg()).size() >
1315 LIS
->getInterval(CP
.getDstReg()).size())
1319 dbgs() << "\tConsidering merging to "
1320 << TRI
->getRegClassName(CP
.getNewRC()) << " with ";
1321 if (CP
.getDstIdx() && CP
.getSrcIdx())
1322 dbgs() << PrintReg(CP
.getDstReg()) << " in "
1323 << TRI
->getSubRegIndexName(CP
.getDstIdx()) << " and "
1324 << PrintReg(CP
.getSrcReg()) << " in "
1325 << TRI
->getSubRegIndexName(CP
.getSrcIdx()) << '\n';
1327 dbgs() << PrintReg(CP
.getSrcReg(), TRI
) << " in "
1328 << PrintReg(CP
.getDstReg(), TRI
, CP
.getSrcIdx()) << '\n';
1333 ShrinkMainRange
= false;
1335 // Okay, attempt to join these two intervals. On failure, this returns false.
1336 // Otherwise, if one of the intervals being joined is a physreg, this method
1337 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1338 // been modified, so we can use this information below to update aliases.
1339 if (!joinIntervals(CP
)) {
1340 // Coalescing failed.
1342 // If definition of source is defined by trivial computation, try
1343 // rematerializing it.
1345 if (reMaterializeTrivialDef(CP
, CopyMI
, IsDefCopy
))
1348 // If we can eliminate the copy without merging the live segments, do so
1350 if (!CP
.isPartial() && !CP
.isPhys()) {
1351 if (adjustCopiesBackFrom(CP
, CopyMI
) ||
1352 removeCopyByCommutingDef(CP
, CopyMI
)) {
1353 LIS
->RemoveMachineInstrFromMaps(CopyMI
);
1354 CopyMI
->eraseFromParent();
1355 DEBUG(dbgs() << "\tTrivial!\n");
1360 // Otherwise, we are unable to join the intervals.
1361 DEBUG(dbgs() << "\tInterference!\n");
1362 Again
= true; // May be possible to coalesce later.
1366 // Coalescing to a virtual register that is of a sub-register class of the
1367 // other. Make sure the resulting register is set to the right register class.
1368 if (CP
.isCrossClass()) {
1370 MRI
->setRegClass(CP
.getDstReg(), CP
.getNewRC());
1373 // Removing sub-register copies can ease the register class constraints.
1374 // Make sure we attempt to inflate the register class of DstReg.
1375 if (!CP
.isPhys() && RegClassInfo
.isProperSubClass(CP
.getNewRC()))
1376 InflateRegs
.push_back(CP
.getDstReg());
1378 // CopyMI has been erased by joinIntervals at this point. Remove it from
1379 // ErasedInstrs since copyCoalesceWorkList() won't add a successful join back
1380 // to the work list. This keeps ErasedInstrs from growing needlessly.
1381 ErasedInstrs
.erase(CopyMI
);
1383 // Rewrite all SrcReg operands to DstReg.
1384 // Also update DstReg operands to include DstIdx if it is set.
1386 updateRegDefsUses(CP
.getDstReg(), CP
.getDstReg(), CP
.getDstIdx());
1387 updateRegDefsUses(CP
.getSrcReg(), CP
.getDstReg(), CP
.getSrcIdx());
1389 // Shrink subregister ranges if necessary.
1390 if (ShrinkMask
!= 0) {
1391 LiveInterval
&LI
= LIS
->getInterval(CP
.getDstReg());
1392 for (LiveInterval::SubRange
&S
: LI
.subranges()) {
1393 if ((S
.LaneMask
& ShrinkMask
) == 0)
1395 DEBUG(dbgs() << "Shrink LaneUses (Lane "
1396 << format("%04X", S
.LaneMask
) << ")\n");
1397 LIS
->shrinkToUses(S
, LI
.reg
);
1400 if (ShrinkMainRange
) {
1401 LiveInterval
&LI
= LIS
->getInterval(CP
.getDstReg());
1402 LIS
->shrinkToUses(&LI
);
1405 // SrcReg is guaranteed to be the register whose live interval that is
1407 LIS
->removeInterval(CP
.getSrcReg());
1409 // Update regalloc hint.
1410 TRI
->UpdateRegAllocHint(CP
.getSrcReg(), CP
.getDstReg(), *MF
);
1413 dbgs() << "\tSuccess: " << PrintReg(CP
.getSrcReg(), TRI
, CP
.getSrcIdx())
1414 << " -> " << PrintReg(CP
.getDstReg(), TRI
, CP
.getDstIdx()) << '\n';
1415 dbgs() << "\tResult = ";
1417 dbgs() << PrintReg(CP
.getDstReg(), TRI
);
1419 dbgs() << LIS
->getInterval(CP
.getDstReg());
1427 /// Attempt joining with a reserved physreg.
1428 bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair
&CP
) {
1429 assert(CP
.isPhys() && "Must be a physreg copy");
1430 assert(MRI
->isReserved(CP
.getDstReg()) && "Not a reserved register");
1431 LiveInterval
&RHS
= LIS
->getInterval(CP
.getSrcReg());
1432 DEBUG(dbgs() << "\t\tRHS = " << RHS
<< '\n');
1434 assert(CP
.isFlipped() && RHS
.containsOneValue() &&
1435 "Invalid join with reserved register");
1437 // Optimization for reserved registers like ESP. We can only merge with a
1438 // reserved physreg if RHS has a single value that is a copy of CP.DstReg().
1439 // The live range of the reserved register will look like a set of dead defs
1440 // - we don't properly track the live range of reserved registers.
1442 // Deny any overlapping intervals. This depends on all the reserved
1443 // register live ranges to look like dead defs.
1444 for (MCRegUnitIterator
UI(CP
.getDstReg(), TRI
); UI
.isValid(); ++UI
)
1445 if (RHS
.overlaps(LIS
->getRegUnit(*UI
))) {
1446 DEBUG(dbgs() << "\t\tInterference: " << PrintRegUnit(*UI
, TRI
) << '\n');
1450 // Skip any value computations, we are not adding new values to the
1451 // reserved register. Also skip merging the live ranges, the reserved
1452 // register live range doesn't need to be accurate as long as all the
1455 // Delete the identity copy.
1456 MachineInstr
*CopyMI
= MRI
->getVRegDef(RHS
.reg
);
1457 LIS
->RemoveMachineInstrFromMaps(CopyMI
);
1458 CopyMI
->eraseFromParent();
1460 // We don't track kills for reserved registers.
1461 MRI
->clearKillFlags(CP
.getSrcReg());
1466 //===----------------------------------------------------------------------===//
1467 // Interference checking and interval joining
1468 //===----------------------------------------------------------------------===//
1470 // In the easiest case, the two live ranges being joined are disjoint, and
1471 // there is no interference to consider. It is quite common, though, to have
1472 // overlapping live ranges, and we need to check if the interference can be
1475 // The live range of a single SSA value forms a sub-tree of the dominator tree.
1476 // This means that two SSA values overlap if and only if the def of one value
1477 // is contained in the live range of the other value. As a special case, the
1478 // overlapping values can be defined at the same index.
1480 // The interference from an overlapping def can be resolved in these cases:
1482 // 1. Coalescable copies. The value is defined by a copy that would become an
1483 // identity copy after joining SrcReg and DstReg. The copy instruction will
1484 // be removed, and the value will be merged with the source value.
1486 // There can be several copies back and forth, causing many values to be
1487 // merged into one. We compute a list of ultimate values in the joined live
1488 // range as well as a mappings from the old value numbers.
1490 // 2. IMPLICIT_DEF. This instruction is only inserted to ensure all PHI
1491 // predecessors have a live out value. It doesn't cause real interference,
1492 // and can be merged into the value it overlaps. Like a coalescable copy, it
1493 // can be erased after joining.
1495 // 3. Copy of external value. The overlapping def may be a copy of a value that
1496 // is already in the other register. This is like a coalescable copy, but
1497 // the live range of the source register must be trimmed after erasing the
1498 // copy instruction:
1501 // %dst = COPY %ext <-- Remove this COPY, trim the live range of %ext.
1503 // 4. Clobbering undefined lanes. Vector registers are sometimes built by
1504 // defining one lane at a time:
1506 // %dst:ssub0<def,read-undef> = FOO
1508 // %dst:ssub1<def> = COPY %src
1510 // The live range of %src overlaps the %dst value defined by FOO, but
1511 // merging %src into %dst:ssub1 is only going to clobber the ssub1 lane
1512 // which was undef anyway.
1514 // The value mapping is more complicated in this case. The final live range
1515 // will have different value numbers for both FOO and BAR, but there is no
1516 // simple mapping from old to new values. It may even be necessary to add
1519 // 5. Clobbering dead lanes. A def may clobber a lane of a vector register that
1520 // is live, but never read. This can happen because we don't compute
1521 // individual live ranges per lane.
1525 // %dst:ssub1<def> = COPY %src
1527 // This kind of interference is only resolved locally. If the clobbered
1528 // lane value escapes the block, the join is aborted.
1531 /// Track information about values in a single virtual register about to be
1532 /// joined. Objects of this class are always created in pairs - one for each
1533 /// side of the CoalescerPair (or one for each lane of a side of the coalescer
1536 /// Live range we work on.
1538 /// (Main) register we work on.
1541 // Reg (and therefore the values in this liverange) will end up as subregister
1542 // SubIdx in the coalesced register. Either CP.DstIdx or CP.SrcIdx.
1543 const unsigned SubIdx
;
1544 // The LaneMask that this liverange will occupy the coalesced register. May be
1545 // smaller than the lanemask produced by SubIdx when merging subranges.
1546 const unsigned LaneMask
;
1548 /// This is true when joining sub register ranges, false when joining main
1550 const bool SubRangeJoin
;
1551 /// Whether the current LiveInterval tracks subregister liveness.
1552 const bool TrackSubRegLiveness
;
1554 // Values that will be present in the final live range.
1555 SmallVectorImpl
<VNInfo
*> &NewVNInfo
;
1557 const CoalescerPair
&CP
;
1559 SlotIndexes
*Indexes
;
1560 const TargetRegisterInfo
*TRI
;
1562 // Value number assignments. Maps value numbers in LI to entries in NewVNInfo.
1563 // This is suitable for passing to LiveInterval::join().
1564 SmallVector
<int, 8> Assignments
;
1566 // Conflict resolution for overlapping values.
1567 enum ConflictResolution
{
1568 // No overlap, simply keep this value.
1571 // Merge this value into OtherVNI and erase the defining instruction.
1572 // Used for IMPLICIT_DEF, coalescable copies, and copies from external
1576 // Merge this value into OtherVNI but keep the defining instruction.
1577 // This is for the special case where OtherVNI is defined by the same
1581 // Keep this value, and have it replace OtherVNI where possible. This
1582 // complicates value mapping since OtherVNI maps to two different values
1583 // before and after this def.
1584 // Used when clobbering undefined or dead lanes.
1587 // Unresolved conflict. Visit later when all values have been mapped.
1590 // Unresolvable conflict. Abort the join.
1594 // Per-value info for LI. The lane bit masks are all relative to the final
1595 // joined register, so they can be compared directly between SrcReg and
1598 ConflictResolution Resolution
;
1600 // Lanes written by this def, 0 for unanalyzed values.
1601 unsigned WriteLanes
;
1603 // Lanes with defined values in this register. Other lanes are undef and
1605 unsigned ValidLanes
;
1607 // Value in LI being redefined by this def.
1610 // Value in the other live range that overlaps this def, if any.
1613 // Is this value an IMPLICIT_DEF that can be erased?
1615 // IMPLICIT_DEF values should only exist at the end of a basic block that
1616 // is a predecessor to a phi-value. These IMPLICIT_DEF instructions can be
1617 // safely erased if they are overlapping a live value in the other live
1620 // Weird control flow graphs and incomplete PHI handling in
1621 // ProcessImplicitDefs can very rarely create IMPLICIT_DEF values with
1622 // longer live ranges. Such IMPLICIT_DEF values should be treated like
1624 bool ErasableImplicitDef
;
1626 // True when the live range of this value will be pruned because of an
1627 // overlapping CR_Replace value in the other live range.
1630 // True once Pruned above has been computed.
1631 bool PrunedComputed
;
1633 Val() : Resolution(CR_Keep
), WriteLanes(0), ValidLanes(0),
1634 RedefVNI(nullptr), OtherVNI(nullptr), ErasableImplicitDef(false),
1635 Pruned(false), PrunedComputed(false) {}
1637 bool isAnalyzed() const { return WriteLanes
!= 0; }
1640 // One entry per value number in LI.
1641 SmallVector
<Val
, 8> Vals
;
1643 unsigned computeWriteLanes(const MachineInstr
*DefMI
, bool &Redef
) const;
1644 std::pair
<const VNInfo
*,unsigned> followCopyChain(const VNInfo
*VNI
) const;
1645 bool valuesIdentical(VNInfo
*Val0
, VNInfo
*Val1
, const JoinVals
&Other
) const;
1646 ConflictResolution
analyzeValue(unsigned ValNo
, JoinVals
&Other
);
1647 void computeAssignment(unsigned ValNo
, JoinVals
&Other
);
1648 bool taintExtent(unsigned, unsigned, JoinVals
&,
1649 SmallVectorImpl
<std::pair
<SlotIndex
, unsigned> >&);
1650 bool usesLanes(const MachineInstr
*MI
, unsigned, unsigned, unsigned) const;
1651 bool isPrunedValue(unsigned ValNo
, JoinVals
&Other
);
1654 JoinVals(LiveRange
&LR
, unsigned Reg
, unsigned SubIdx
, unsigned LaneMask
,
1655 SmallVectorImpl
<VNInfo
*> &newVNInfo
, const CoalescerPair
&cp
,
1656 LiveIntervals
*lis
, const TargetRegisterInfo
*TRI
, bool SubRangeJoin
,
1657 bool TrackSubRegLiveness
)
1658 : LR(LR
), Reg(Reg
), SubIdx(SubIdx
), LaneMask(LaneMask
),
1659 SubRangeJoin(SubRangeJoin
), TrackSubRegLiveness(TrackSubRegLiveness
),
1660 NewVNInfo(newVNInfo
), CP(cp
), LIS(lis
), Indexes(LIS
->getSlotIndexes()),
1661 TRI(TRI
), Assignments(LR
.getNumValNums(), -1), Vals(LR
.getNumValNums())
1664 /// Analyze defs in LR and compute a value mapping in NewVNInfo.
1665 /// Returns false if any conflicts were impossible to resolve.
1666 bool mapValues(JoinVals
&Other
);
1668 /// Try to resolve conflicts that require all values to be mapped.
1669 /// Returns false if any conflicts were impossible to resolve.
1670 bool resolveConflicts(JoinVals
&Other
);
1672 /// Prune the live range of values in Other.LR where they would conflict with
1673 /// CR_Replace values in LR. Collect end points for restoring the live range
1675 void pruneValues(JoinVals
&Other
, SmallVectorImpl
<SlotIndex
> &EndPoints
,
1678 // Removes subranges starting at copies that get removed. This sometimes
1679 // happens when undefined subranges are copied around. These ranges contain
1680 // no usefull information and can be removed.
1681 void pruneSubRegValues(LiveInterval
&LI
, unsigned &ShrinkMask
);
1683 /// Erase any machine instructions that have been coalesced away.
1684 /// Add erased instructions to ErasedInstrs.
1685 /// Add foreign virtual registers to ShrinkRegs if their live range ended at
1686 /// the erased instrs.
1687 void eraseInstrs(SmallPtrSetImpl
<MachineInstr
*> &ErasedInstrs
,
1688 SmallVectorImpl
<unsigned> &ShrinkRegs
);
1690 /// Get the value assignments suitable for passing to LiveInterval::join.
1691 const int *getAssignments() const { return Assignments
.data(); }
1693 } // end anonymous namespace
1695 /// Compute the bitmask of lanes actually written by DefMI.
1696 /// Set Redef if there are any partial register definitions that depend on the
1697 /// previous value of the register.
1698 unsigned JoinVals::computeWriteLanes(const MachineInstr
*DefMI
, bool &Redef
)
1701 for (ConstMIOperands
MO(DefMI
); MO
.isValid(); ++MO
) {
1702 if (!MO
->isReg() || MO
->getReg() != Reg
|| !MO
->isDef())
1704 L
|= TRI
->getSubRegIndexLaneMask(
1705 TRI
->composeSubRegIndices(SubIdx
, MO
->getSubReg()));
1712 /// Find the ultimate value that VNI was copied from.
1713 std::pair
<const VNInfo
*, unsigned> JoinVals::followCopyChain(
1714 const VNInfo
*VNI
) const {
1715 unsigned Reg
= this->Reg
;
1717 while (!VNI
->isPHIDef()) {
1718 SlotIndex Def
= VNI
->def
;
1719 MachineInstr
*MI
= Indexes
->getInstructionFromIndex(Def
);
1720 assert(MI
&& "No defining instruction");
1721 if (!MI
->isFullCopy())
1722 return std::make_pair(VNI
, Reg
);
1723 unsigned SrcReg
= MI
->getOperand(1).getReg();
1724 if (!TargetRegisterInfo::isVirtualRegister(SrcReg
))
1725 return std::make_pair(VNI
, Reg
);
1727 const LiveInterval
&LI
= LIS
->getInterval(SrcReg
);
1728 const VNInfo
*ValueIn
;
1729 // No subrange involved.
1730 if (!SubRangeJoin
|| !LI
.hasSubRanges()) {
1731 LiveQueryResult LRQ
= LI
.Query(Def
);
1732 ValueIn
= LRQ
.valueIn();
1734 // Query subranges. Pick the first matching one.
1736 for (const LiveInterval::SubRange
&S
: LI
.subranges()) {
1737 // Transform lanemask to a mask in the joined live interval.
1738 unsigned SMask
= TRI
->composeSubRegIndexLaneMask(SubIdx
, S
.LaneMask
);
1739 if ((SMask
& LaneMask
) == 0)
1741 LiveQueryResult LRQ
= S
.Query(Def
);
1742 ValueIn
= LRQ
.valueIn();
1746 if (ValueIn
== nullptr)
1751 return std::make_pair(VNI
, Reg
);
1754 bool JoinVals::valuesIdentical(VNInfo
*Value0
, VNInfo
*Value1
,
1755 const JoinVals
&Other
) const {
1756 const VNInfo
*Orig0
;
1758 std::tie(Orig0
, Reg0
) = followCopyChain(Value0
);
1759 if (Orig0
== Value1
)
1762 const VNInfo
*Orig1
;
1764 std::tie(Orig1
, Reg1
) = Other
.followCopyChain(Value1
);
1766 // The values are equal if they are defined at the same place and use the
1767 // same register. Note that we cannot compare VNInfos directly as some of
1768 // them might be from a copy created in mergeSubRangeInto() while the other
1769 // is from the original LiveInterval.
1770 return Orig0
->def
== Orig1
->def
&& Reg0
== Reg1
;
1773 /// Analyze ValNo in this live range, and set all fields of Vals[ValNo].
1774 /// Return a conflict resolution when possible, but leave the hard cases as
1776 /// Recursively calls computeAssignment() on this and Other, guaranteeing that
1777 /// both OtherVNI and RedefVNI have been analyzed and mapped before returning.
1778 /// The recursion always goes upwards in the dominator tree, making loops
1780 JoinVals::ConflictResolution
1781 JoinVals::analyzeValue(unsigned ValNo
, JoinVals
&Other
) {
1782 Val
&V
= Vals
[ValNo
];
1783 assert(!V
.isAnalyzed() && "Value has already been analyzed!");
1784 VNInfo
*VNI
= LR
.getValNumInfo(ValNo
);
1785 if (VNI
->isUnused()) {
1790 // Get the instruction defining this value, compute the lanes written.
1791 const MachineInstr
*DefMI
= nullptr;
1792 if (VNI
->isPHIDef()) {
1793 // Conservatively assume that all lanes in a PHI are valid.
1794 unsigned Lanes
= SubRangeJoin
? 1 : TRI
->getSubRegIndexLaneMask(SubIdx
);
1795 V
.ValidLanes
= V
.WriteLanes
= Lanes
;
1797 DefMI
= Indexes
->getInstructionFromIndex(VNI
->def
);
1798 assert(DefMI
!= nullptr);
1800 // We don't care about the lanes when joining subregister ranges.
1801 V
.ValidLanes
= V
.WriteLanes
= 1;
1804 V
.ValidLanes
= V
.WriteLanes
= computeWriteLanes(DefMI
, Redef
);
1806 // If this is a read-modify-write instruction, there may be more valid
1807 // lanes than the ones written by this instruction.
1808 // This only covers partial redef operands. DefMI may have normal use
1809 // operands reading the register. They don't contribute valid lanes.
1811 // This adds ssub1 to the set of valid lanes in %src:
1813 // %src:ssub1<def> = FOO
1815 // This leaves only ssub1 valid, making any other lanes undef:
1817 // %src:ssub1<def,read-undef> = FOO %src:ssub2
1819 // The <read-undef> flag on the def operand means that old lane values are
1822 V
.RedefVNI
= LR
.Query(VNI
->def
).valueIn();
1823 assert((TrackSubRegLiveness
|| V
.RedefVNI
) &&
1824 "Instruction is reading nonexistent value");
1825 if (V
.RedefVNI
!= nullptr) {
1826 computeAssignment(V
.RedefVNI
->id
, Other
);
1827 V
.ValidLanes
|= Vals
[V
.RedefVNI
->id
].ValidLanes
;
1831 // An IMPLICIT_DEF writes undef values.
1832 if (DefMI
->isImplicitDef()) {
1833 // We normally expect IMPLICIT_DEF values to be live only until the end
1834 // of their block. If the value is really live longer and gets pruned in
1835 // another block, this flag is cleared again.
1836 V
.ErasableImplicitDef
= true;
1837 V
.ValidLanes
&= ~V
.WriteLanes
;
1842 // Find the value in Other that overlaps VNI->def, if any.
1843 LiveQueryResult OtherLRQ
= Other
.LR
.Query(VNI
->def
);
1845 // It is possible that both values are defined by the same instruction, or
1846 // the values are PHIs defined in the same block. When that happens, the two
1847 // values should be merged into one, but not into any preceding value.
1848 // The first value defined or visited gets CR_Keep, the other gets CR_Merge.
1849 if (VNInfo
*OtherVNI
= OtherLRQ
.valueDefined()) {
1850 assert(SlotIndex::isSameInstr(VNI
->def
, OtherVNI
->def
) && "Broken LRQ");
1852 // One value stays, the other is merged. Keep the earlier one, or the first
1854 if (OtherVNI
->def
< VNI
->def
)
1855 Other
.computeAssignment(OtherVNI
->id
, *this);
1856 else if (VNI
->def
< OtherVNI
->def
&& OtherLRQ
.valueIn()) {
1857 // This is an early-clobber def overlapping a live-in value in the other
1858 // register. Not mergeable.
1859 V
.OtherVNI
= OtherLRQ
.valueIn();
1860 return CR_Impossible
;
1862 V
.OtherVNI
= OtherVNI
;
1863 Val
&OtherV
= Other
.Vals
[OtherVNI
->id
];
1864 // Keep this value, check for conflicts when analyzing OtherVNI.
1865 if (!OtherV
.isAnalyzed())
1867 // Both sides have been analyzed now.
1868 // Allow overlapping PHI values. Any real interference would show up in a
1869 // predecessor, the PHI itself can't introduce any conflicts.
1870 if (VNI
->isPHIDef())
1872 if (V
.ValidLanes
& OtherV
.ValidLanes
)
1873 // Overlapping lanes can't be resolved.
1874 return CR_Impossible
;
1879 // No simultaneous def. Is Other live at the def?
1880 V
.OtherVNI
= OtherLRQ
.valueIn();
1882 // No overlap, no conflict.
1885 assert(!SlotIndex::isSameInstr(VNI
->def
, V
.OtherVNI
->def
) && "Broken LRQ");
1887 // We have overlapping values, or possibly a kill of Other.
1888 // Recursively compute assignments up the dominator tree.
1889 Other
.computeAssignment(V
.OtherVNI
->id
, *this);
1890 Val
&OtherV
= Other
.Vals
[V
.OtherVNI
->id
];
1892 // Check if OtherV is an IMPLICIT_DEF that extends beyond its basic block.
1893 // This shouldn't normally happen, but ProcessImplicitDefs can leave such
1894 // IMPLICIT_DEF instructions behind, and there is nothing wrong with it
1897 // WHen it happens, treat that IMPLICIT_DEF as a normal value, and don't try
1898 // to erase the IMPLICIT_DEF instruction.
1899 if (OtherV
.ErasableImplicitDef
&& DefMI
&&
1900 DefMI
->getParent() != Indexes
->getMBBFromIndex(V
.OtherVNI
->def
)) {
1901 DEBUG(dbgs() << "IMPLICIT_DEF defined at " << V
.OtherVNI
->def
1902 << " extends into BB#" << DefMI
->getParent()->getNumber()
1903 << ", keeping it.\n");
1904 OtherV
.ErasableImplicitDef
= false;
1907 // Allow overlapping PHI values. Any real interference would show up in a
1908 // predecessor, the PHI itself can't introduce any conflicts.
1909 if (VNI
->isPHIDef())
1912 // Check for simple erasable conflicts.
1913 if (DefMI
->isImplicitDef()) {
1914 // We need the def for the subregister if there is nothing else live at the
1915 // subrange at this point.
1916 if (TrackSubRegLiveness
1917 && (V
.WriteLanes
& (OtherV
.ValidLanes
| OtherV
.WriteLanes
)) == 0)
1922 // Include the non-conflict where DefMI is a coalescable copy that kills
1923 // OtherVNI. We still want the copy erased and value numbers merged.
1924 if (CP
.isCoalescable(DefMI
)) {
1925 // Some of the lanes copied from OtherVNI may be undef, making them undef
1927 V
.ValidLanes
&= ~V
.WriteLanes
| OtherV
.ValidLanes
;
1931 // This may not be a real conflict if DefMI simply kills Other and defines
1933 if (OtherLRQ
.isKill() && OtherLRQ
.endPoint() <= VNI
->def
)
1936 // Handle the case where VNI and OtherVNI can be proven to be identical:
1938 // %other = COPY %ext
1939 // %this = COPY %ext <-- Erase this copy
1941 if (DefMI
->isFullCopy() && !CP
.isPartial()
1942 && valuesIdentical(VNI
, V
.OtherVNI
, Other
))
1945 // If the lanes written by this instruction were all undef in OtherVNI, it is
1946 // still safe to join the live ranges. This can't be done with a simple value
1947 // mapping, though - OtherVNI will map to multiple values:
1949 // 1 %dst:ssub0 = FOO <-- OtherVNI
1950 // 2 %src = BAR <-- VNI
1951 // 3 %dst:ssub1 = COPY %src<kill> <-- Eliminate this copy.
1953 // 5 QUUX %src<kill>
1955 // Here OtherVNI will map to itself in [1;2), but to VNI in [2;5). CR_Replace
1956 // handles this complex value mapping.
1957 if ((V
.WriteLanes
& OtherV
.ValidLanes
) == 0)
1960 // If the other live range is killed by DefMI and the live ranges are still
1961 // overlapping, it must be because we're looking at an early clobber def:
1963 // %dst<def,early-clobber> = ASM %src<kill>
1965 // In this case, it is illegal to merge the two live ranges since the early
1966 // clobber def would clobber %src before it was read.
1967 if (OtherLRQ
.isKill()) {
1968 // This case where the def doesn't overlap the kill is handled above.
1969 assert(VNI
->def
.isEarlyClobber() &&
1970 "Only early clobber defs can overlap a kill");
1971 return CR_Impossible
;
1974 // VNI is clobbering live lanes in OtherVNI, but there is still the
1975 // possibility that no instructions actually read the clobbered lanes.
1976 // If we're clobbering all the lanes in OtherVNI, at least one must be read.
1977 // Otherwise Other.RI wouldn't be live here.
1978 if ((TRI
->getSubRegIndexLaneMask(Other
.SubIdx
) & ~V
.WriteLanes
) == 0)
1979 return CR_Impossible
;
1981 // We need to verify that no instructions are reading the clobbered lanes. To
1982 // save compile time, we'll only check that locally. Don't allow the tainted
1983 // value to escape the basic block.
1984 MachineBasicBlock
*MBB
= Indexes
->getMBBFromIndex(VNI
->def
);
1985 if (OtherLRQ
.endPoint() >= Indexes
->getMBBEndIdx(MBB
))
1986 return CR_Impossible
;
1988 // There are still some things that could go wrong besides clobbered lanes
1989 // being read, for example OtherVNI may be only partially redefined in MBB,
1990 // and some clobbered lanes could escape the block. Save this analysis for
1991 // resolveConflicts() when all values have been mapped. We need to know
1992 // RedefVNI and WriteLanes for any later defs in MBB, and we can't compute
1993 // that now - the recursive analyzeValue() calls must go upwards in the
1995 return CR_Unresolved
;
1998 /// Compute the value assignment for ValNo in RI.
1999 /// This may be called recursively by analyzeValue(), but never for a ValNo on
2001 void JoinVals::computeAssignment(unsigned ValNo
, JoinVals
&Other
) {
2002 Val
&V
= Vals
[ValNo
];
2003 if (V
.isAnalyzed()) {
2004 // Recursion should always move up the dominator tree, so ValNo is not
2005 // supposed to reappear before it has been assigned.
2006 assert(Assignments
[ValNo
] != -1 && "Bad recursion?");
2009 switch ((V
.Resolution
= analyzeValue(ValNo
, Other
))) {
2012 // Merge this ValNo into OtherVNI.
2013 assert(V
.OtherVNI
&& "OtherVNI not assigned, can't merge.");
2014 assert(Other
.Vals
[V
.OtherVNI
->id
].isAnalyzed() && "Missing recursion");
2015 Assignments
[ValNo
] = Other
.Assignments
[V
.OtherVNI
->id
];
2016 DEBUG(dbgs() << "\t\tmerge " << PrintReg(Reg
) << ':' << ValNo
<< '@'
2017 << LR
.getValNumInfo(ValNo
)->def
<< " into "
2018 << PrintReg(Other
.Reg
) << ':' << V
.OtherVNI
->id
<< '@'
2019 << V
.OtherVNI
->def
<< " --> @"
2020 << NewVNInfo
[Assignments
[ValNo
]]->def
<< '\n');
2023 case CR_Unresolved
: {
2024 // The other value is going to be pruned if this join is successful.
2025 assert(V
.OtherVNI
&& "OtherVNI not assigned, can't prune");
2026 Val
&OtherV
= Other
.Vals
[V
.OtherVNI
->id
];
2027 // We cannot erase an IMPLICIT_DEF if we don't have valid values for all
2029 if ((OtherV
.WriteLanes
& ~V
.ValidLanes
) != 0 && TrackSubRegLiveness
)
2030 OtherV
.ErasableImplicitDef
= false;
2031 OtherV
.Pruned
= true;
2035 // This value number needs to go in the final joined live range.
2036 Assignments
[ValNo
] = NewVNInfo
.size();
2037 NewVNInfo
.push_back(LR
.getValNumInfo(ValNo
));
2042 bool JoinVals::mapValues(JoinVals
&Other
) {
2043 for (unsigned i
= 0, e
= LR
.getNumValNums(); i
!= e
; ++i
) {
2044 computeAssignment(i
, Other
);
2045 if (Vals
[i
].Resolution
== CR_Impossible
) {
2046 DEBUG(dbgs() << "\t\tinterference at " << PrintReg(Reg
) << ':' << i
2047 << '@' << LR
.getValNumInfo(i
)->def
<< '\n');
2054 /// Assuming ValNo is going to clobber some valid lanes in Other.LR, compute
2055 /// the extent of the tainted lanes in the block.
2057 /// Multiple values in Other.LR can be affected since partial redefinitions can
2058 /// preserve previously tainted lanes.
2060 /// 1 %dst = VLOAD <-- Define all lanes in %dst
2061 /// 2 %src = FOO <-- ValNo to be joined with %dst:ssub0
2062 /// 3 %dst:ssub1 = BAR <-- Partial redef doesn't clear taint in ssub0
2063 /// 4 %dst:ssub0 = COPY %src <-- Conflict resolved, ssub0 wasn't read
2065 /// For each ValNo in Other that is affected, add an (EndIndex, TaintedLanes)
2066 /// entry to TaintedVals.
2068 /// Returns false if the tainted lanes extend beyond the basic block.
2070 taintExtent(unsigned ValNo
, unsigned TaintedLanes
, JoinVals
&Other
,
2071 SmallVectorImpl
<std::pair
<SlotIndex
, unsigned> > &TaintExtent
) {
2072 VNInfo
*VNI
= LR
.getValNumInfo(ValNo
);
2073 MachineBasicBlock
*MBB
= Indexes
->getMBBFromIndex(VNI
->def
);
2074 SlotIndex MBBEnd
= Indexes
->getMBBEndIdx(MBB
);
2076 // Scan Other.LR from VNI.def to MBBEnd.
2077 LiveInterval::iterator OtherI
= Other
.LR
.find(VNI
->def
);
2078 assert(OtherI
!= Other
.LR
.end() && "No conflict?");
2080 // OtherI is pointing to a tainted value. Abort the join if the tainted
2081 // lanes escape the block.
2082 SlotIndex End
= OtherI
->end
;
2083 if (End
>= MBBEnd
) {
2084 DEBUG(dbgs() << "\t\ttaints global " << PrintReg(Other
.Reg
) << ':'
2085 << OtherI
->valno
->id
<< '@' << OtherI
->start
<< '\n');
2088 DEBUG(dbgs() << "\t\ttaints local " << PrintReg(Other
.Reg
) << ':'
2089 << OtherI
->valno
->id
<< '@' << OtherI
->start
2090 << " to " << End
<< '\n');
2091 // A dead def is not a problem.
2094 TaintExtent
.push_back(std::make_pair(End
, TaintedLanes
));
2096 // Check for another def in the MBB.
2097 if (++OtherI
== Other
.LR
.end() || OtherI
->start
>= MBBEnd
)
2100 // Lanes written by the new def are no longer tainted.
2101 const Val
&OV
= Other
.Vals
[OtherI
->valno
->id
];
2102 TaintedLanes
&= ~OV
.WriteLanes
;
2105 } while (TaintedLanes
);
2109 /// Return true if MI uses any of the given Lanes from Reg.
2110 /// This does not include partial redefinitions of Reg.
2111 bool JoinVals::usesLanes(const MachineInstr
*MI
, unsigned Reg
, unsigned SubIdx
,
2112 unsigned Lanes
) const {
2113 if (MI
->isDebugValue())
2115 for (ConstMIOperands
MO(MI
); MO
.isValid(); ++MO
) {
2116 if (!MO
->isReg() || MO
->isDef() || MO
->getReg() != Reg
)
2118 if (!MO
->readsReg())
2120 if (Lanes
& TRI
->getSubRegIndexLaneMask(
2121 TRI
->composeSubRegIndices(SubIdx
, MO
->getSubReg())))
2127 bool JoinVals::resolveConflicts(JoinVals
&Other
) {
2128 for (unsigned i
= 0, e
= LR
.getNumValNums(); i
!= e
; ++i
) {
2130 assert (V
.Resolution
!= CR_Impossible
&& "Unresolvable conflict");
2131 if (V
.Resolution
!= CR_Unresolved
)
2133 DEBUG(dbgs() << "\t\tconflict at " << PrintReg(Reg
) << ':' << i
2134 << '@' << LR
.getValNumInfo(i
)->def
<< '\n');
2139 assert(V
.OtherVNI
&& "Inconsistent conflict resolution.");
2140 VNInfo
*VNI
= LR
.getValNumInfo(i
);
2141 const Val
&OtherV
= Other
.Vals
[V
.OtherVNI
->id
];
2143 // VNI is known to clobber some lanes in OtherVNI. If we go ahead with the
2144 // join, those lanes will be tainted with a wrong value. Get the extent of
2145 // the tainted lanes.
2146 unsigned TaintedLanes
= V
.WriteLanes
& OtherV
.ValidLanes
;
2147 SmallVector
<std::pair
<SlotIndex
, unsigned>, 8> TaintExtent
;
2148 if (!taintExtent(i
, TaintedLanes
, Other
, TaintExtent
))
2149 // Tainted lanes would extend beyond the basic block.
2152 assert(!TaintExtent
.empty() && "There should be at least one conflict.");
2154 // Now look at the instructions from VNI->def to TaintExtent (inclusive).
2155 MachineBasicBlock
*MBB
= Indexes
->getMBBFromIndex(VNI
->def
);
2156 MachineBasicBlock::iterator MI
= MBB
->begin();
2157 if (!VNI
->isPHIDef()) {
2158 MI
= Indexes
->getInstructionFromIndex(VNI
->def
);
2159 // No need to check the instruction defining VNI for reads.
2162 assert(!SlotIndex::isSameInstr(VNI
->def
, TaintExtent
.front().first
) &&
2163 "Interference ends on VNI->def. Should have been handled earlier");
2164 MachineInstr
*LastMI
=
2165 Indexes
->getInstructionFromIndex(TaintExtent
.front().first
);
2166 assert(LastMI
&& "Range must end at a proper instruction");
2167 unsigned TaintNum
= 0;
2169 assert(MI
!= MBB
->end() && "Bad LastMI");
2170 if (usesLanes(MI
, Other
.Reg
, Other
.SubIdx
, TaintedLanes
)) {
2171 DEBUG(dbgs() << "\t\ttainted lanes used by: " << *MI
);
2174 // LastMI is the last instruction to use the current value.
2175 if (&*MI
== LastMI
) {
2176 if (++TaintNum
== TaintExtent
.size())
2178 LastMI
= Indexes
->getInstructionFromIndex(TaintExtent
[TaintNum
].first
);
2179 assert(LastMI
&& "Range must end at a proper instruction");
2180 TaintedLanes
= TaintExtent
[TaintNum
].second
;
2185 // The tainted lanes are unused.
2186 V
.Resolution
= CR_Replace
;
2192 // Determine if ValNo is a copy of a value number in LR or Other.LR that will
2196 // %src = COPY %dst <-- This value to be pruned.
2197 // %dst = COPY %src <-- This value is a copy of a pruned value.
2199 bool JoinVals::isPrunedValue(unsigned ValNo
, JoinVals
&Other
) {
2200 Val
&V
= Vals
[ValNo
];
2201 if (V
.Pruned
|| V
.PrunedComputed
)
2204 if (V
.Resolution
!= CR_Erase
&& V
.Resolution
!= CR_Merge
)
2207 // Follow copies up the dominator tree and check if any intermediate value
2209 V
.PrunedComputed
= true;
2210 V
.Pruned
= Other
.isPrunedValue(V
.OtherVNI
->id
, *this);
2214 void JoinVals::pruneValues(JoinVals
&Other
,
2215 SmallVectorImpl
<SlotIndex
> &EndPoints
,
2216 bool changeInstrs
) {
2217 for (unsigned i
= 0, e
= LR
.getNumValNums(); i
!= e
; ++i
) {
2218 SlotIndex Def
= LR
.getValNumInfo(i
)->def
;
2219 switch (Vals
[i
].Resolution
) {
2223 // This value takes precedence over the value in Other.LR.
2224 LIS
->pruneValue(Other
.LR
, Def
, &EndPoints
);
2225 // Check if we're replacing an IMPLICIT_DEF value. The IMPLICIT_DEF
2226 // instructions are only inserted to provide a live-out value for PHI
2227 // predecessors, so the instruction should simply go away once its value
2228 // has been replaced.
2229 Val
&OtherV
= Other
.Vals
[Vals
[i
].OtherVNI
->id
];
2230 bool EraseImpDef
= OtherV
.ErasableImplicitDef
&&
2231 OtherV
.Resolution
== CR_Keep
;
2232 if (!Def
.isBlock()) {
2234 // Remove <def,read-undef> flags. This def is now a partial redef.
2235 // Also remove <def,dead> flags since the joined live range will
2236 // continue past this instruction.
2237 for (MIOperands
MO(Indexes
->getInstructionFromIndex(Def
));
2238 MO
.isValid(); ++MO
) {
2239 if (MO
->isReg() && MO
->isDef() && MO
->getReg() == Reg
) {
2240 MO
->setIsUndef(EraseImpDef
);
2241 MO
->setIsDead(false);
2245 // This value will reach instructions below, but we need to make sure
2246 // the live range also reaches the instruction at Def.
2248 EndPoints
.push_back(Def
);
2250 DEBUG(dbgs() << "\t\tpruned " << PrintReg(Other
.Reg
) << " at " << Def
2251 << ": " << Other
.LR
<< '\n');
2256 if (isPrunedValue(i
, Other
)) {
2257 // This value is ultimately a copy of a pruned value in LR or Other.LR.
2258 // We can no longer trust the value mapping computed by
2259 // computeAssignment(), the value that was originally copied could have
2261 LIS
->pruneValue(LR
, Def
, &EndPoints
);
2262 DEBUG(dbgs() << "\t\tpruned all of " << PrintReg(Reg
) << " at "
2263 << Def
<< ": " << LR
<< '\n');
2268 llvm_unreachable("Unresolved conflicts");
2273 void JoinVals::pruneSubRegValues(LiveInterval
&LI
, unsigned &ShrinkMask
)
2275 // Look for values being erased.
2276 bool DidPrune
= false;
2277 for (unsigned i
= 0, e
= LR
.getNumValNums(); i
!= e
; ++i
) {
2278 if (Vals
[i
].Resolution
!= CR_Erase
)
2281 // Check subranges at the point where the copy will be removed.
2282 SlotIndex Def
= LR
.getValNumInfo(i
)->def
;
2283 for (LiveInterval::SubRange
&S
: LI
.subranges()) {
2284 LiveQueryResult Q
= S
.Query(Def
);
2286 // If a subrange starts at the copy then an undefined value has been
2287 // copied and we must remove that subrange value as well.
2288 VNInfo
*ValueOut
= Q
.valueOutOrDead();
2289 if (ValueOut
!= nullptr && Q
.valueIn() == nullptr) {
2290 DEBUG(dbgs() << "\t\tPrune sublane " << format("%04X", S
.LaneMask
)
2291 << " at " << Def
<< "\n");
2292 LIS
->pruneValue(S
, Def
, nullptr);
2294 // Mark value number as unused.
2295 ValueOut
->markUnused();
2298 // If a subrange ends at the copy, then a value was copied but only
2299 // partially used later. Shrink the subregister range apropriately.
2300 if (Q
.valueIn() != nullptr && Q
.valueOut() == nullptr) {
2301 DEBUG(dbgs() << "\t\tDead uses at sublane "
2302 << format("%04X", S
.LaneMask
) << " at " << Def
<< "\n");
2303 ShrinkMask
|= S
.LaneMask
;
2308 LI
.removeEmptySubRanges();
2311 void JoinVals::eraseInstrs(SmallPtrSetImpl
<MachineInstr
*> &ErasedInstrs
,
2312 SmallVectorImpl
<unsigned> &ShrinkRegs
) {
2313 for (unsigned i
= 0, e
= LR
.getNumValNums(); i
!= e
; ++i
) {
2314 // Get the def location before markUnused() below invalidates it.
2315 SlotIndex Def
= LR
.getValNumInfo(i
)->def
;
2316 switch (Vals
[i
].Resolution
) {
2318 // If an IMPLICIT_DEF value is pruned, it doesn't serve a purpose any
2319 // longer. The IMPLICIT_DEF instructions are only inserted by
2320 // PHIElimination to guarantee that all PHI predecessors have a value.
2321 if (!Vals
[i
].ErasableImplicitDef
|| !Vals
[i
].Pruned
)
2323 // Remove value number i from LR. Note that this VNInfo is still present
2324 // in NewVNInfo, so it will appear as an unused value number in the final
2326 LR
.getValNumInfo(i
)->markUnused();
2327 LR
.removeValNo(LR
.getValNumInfo(i
));
2328 DEBUG(dbgs() << "\t\tremoved " << i
<< '@' << Def
<< ": " << LR
<< '\n');
2332 MachineInstr
*MI
= Indexes
->getInstructionFromIndex(Def
);
2333 assert(MI
&& "No instruction to erase");
2335 unsigned Reg
= MI
->getOperand(1).getReg();
2336 if (TargetRegisterInfo::isVirtualRegister(Reg
) &&
2337 Reg
!= CP
.getSrcReg() && Reg
!= CP
.getDstReg())
2338 ShrinkRegs
.push_back(Reg
);
2340 ErasedInstrs
.insert(MI
);
2341 DEBUG(dbgs() << "\t\terased:\t" << Def
<< '\t' << *MI
);
2342 LIS
->RemoveMachineInstrFromMaps(MI
);
2343 MI
->eraseFromParent();
2352 void RegisterCoalescer::joinSubRegRanges(LiveRange
&LRange
, LiveRange
&RRange
,
2354 const CoalescerPair
&CP
) {
2355 SmallVector
<VNInfo
*, 16> NewVNInfo
;
2356 JoinVals
RHSVals(RRange
, CP
.getSrcReg(), CP
.getSrcIdx(), LaneMask
,
2357 NewVNInfo
, CP
, LIS
, TRI
, true, true);
2358 JoinVals
LHSVals(LRange
, CP
.getDstReg(), CP
.getDstIdx(), LaneMask
,
2359 NewVNInfo
, CP
, LIS
, TRI
, true, true);
2361 /// Compute NewVNInfo and resolve conflicts (see also joinVirtRegs())
2362 /// Conflicts should already be resolved so the mapping/resolution should
2364 if (!LHSVals
.mapValues(RHSVals
) || !RHSVals
.mapValues(LHSVals
))
2365 llvm_unreachable("Can't join subrange although main ranges are compatible");
2366 if (!LHSVals
.resolveConflicts(RHSVals
) || !RHSVals
.resolveConflicts(LHSVals
))
2367 llvm_unreachable("Can't join subrange although main ranges are compatible");
2369 // The merging algorithm in LiveInterval::join() can't handle conflicting
2370 // value mappings, so we need to remove any live ranges that overlap a
2371 // CR_Replace resolution. Collect a set of end points that can be used to
2372 // restore the live range after joining.
2373 SmallVector
<SlotIndex
, 8> EndPoints
;
2374 LHSVals
.pruneValues(RHSVals
, EndPoints
, false);
2375 RHSVals
.pruneValues(LHSVals
, EndPoints
, false);
2380 // Join RRange into LHS.
2381 LRange
.join(RRange
, LHSVals
.getAssignments(), RHSVals
.getAssignments(),
2384 DEBUG(dbgs() << "\t\tjoined lanes: " << LRange
<< "\n");
2385 if (EndPoints
.empty())
2388 // Recompute the parts of the live range we had to remove because of
2389 // CR_Replace conflicts.
2390 DEBUG(dbgs() << "\t\trestoring liveness to " << EndPoints
.size()
2391 << " points: " << LRange
<< '\n');
2392 LIS
->extendToIndices(LRange
, EndPoints
);
2395 void RegisterCoalescer::mergeSubRangeInto(LiveInterval
&LI
,
2396 const LiveRange
&ToMerge
,
2397 unsigned LaneMask
, CoalescerPair
&CP
) {
2398 BumpPtrAllocator
&Allocator
= LIS
->getVNInfoAllocator();
2399 for (LiveInterval::SubRange
&R
: LI
.subranges()) {
2400 unsigned RMask
= R
.LaneMask
;
2401 // LaneMask of subregisters common to subrange R and ToMerge.
2402 unsigned Common
= RMask
& LaneMask
;
2403 // There is nothing to do without common subregs.
2407 DEBUG(dbgs() << format("\t\tCopy+Merge %04X into %04X\n", RMask
, Common
));
2408 // LaneMask of subregisters contained in the R range but not in ToMerge,
2409 // they have to split into their own subrange.
2410 unsigned LRest
= RMask
& ~LaneMask
;
2411 LiveInterval::SubRange
*CommonRange
;
2414 DEBUG(dbgs() << format("\t\tReduce Lane to %04X\n", LRest
));
2415 // Duplicate SubRange for newly merged common stuff.
2416 CommonRange
= LI
.createSubRangeFrom(Allocator
, Common
, R
);
2418 // Reuse the existing range.
2419 R
.LaneMask
= Common
;
2422 LiveRange
RangeCopy(ToMerge
, Allocator
);
2423 joinSubRegRanges(*CommonRange
, RangeCopy
, Common
, CP
);
2427 if (LaneMask
!= 0) {
2428 DEBUG(dbgs() << format("\t\tNew Lane %04X\n", LaneMask
));
2429 LI
.createSubRangeFrom(Allocator
, LaneMask
, ToMerge
);
2433 bool RegisterCoalescer::joinVirtRegs(CoalescerPair
&CP
) {
2434 SmallVector
<VNInfo
*, 16> NewVNInfo
;
2435 LiveInterval
&RHS
= LIS
->getInterval(CP
.getSrcReg());
2436 LiveInterval
&LHS
= LIS
->getInterval(CP
.getDstReg());
2437 bool TrackSubRegLiveness
= MRI
->tracksSubRegLiveness();
2438 JoinVals
RHSVals(RHS
, CP
.getSrcReg(), CP
.getSrcIdx(), 0, NewVNInfo
, CP
, LIS
,
2439 TRI
, false, TrackSubRegLiveness
);
2440 JoinVals
LHSVals(LHS
, CP
.getDstReg(), CP
.getDstIdx(), 0, NewVNInfo
, CP
, LIS
,
2441 TRI
, false, TrackSubRegLiveness
);
2443 DEBUG(dbgs() << "\t\tRHS = " << RHS
2444 << "\n\t\tLHS = " << LHS
2447 // First compute NewVNInfo and the simple value mappings.
2448 // Detect impossible conflicts early.
2449 if (!LHSVals
.mapValues(RHSVals
) || !RHSVals
.mapValues(LHSVals
))
2452 // Some conflicts can only be resolved after all values have been mapped.
2453 if (!LHSVals
.resolveConflicts(RHSVals
) || !RHSVals
.resolveConflicts(LHSVals
))
2456 // All clear, the live ranges can be merged.
2457 if (RHS
.hasSubRanges() || LHS
.hasSubRanges()) {
2458 BumpPtrAllocator
&Allocator
= LIS
->getVNInfoAllocator();
2460 // Transform lanemasks from the LHS to masks in the coalesced register and
2461 // create initial subranges if necessary.
2462 unsigned DstIdx
= CP
.getDstIdx();
2463 if (!LHS
.hasSubRanges()) {
2464 unsigned Mask
= DstIdx
== 0 ? CP
.getNewRC()->getLaneMask()
2465 : TRI
->getSubRegIndexLaneMask(DstIdx
);
2466 // LHS must support subregs or we wouldn't be in this codepath.
2468 LHS
.createSubRangeFrom(Allocator
, Mask
, LHS
);
2469 } else if (DstIdx
!= 0) {
2470 // Transform LHS lanemasks to new register class if necessary.
2471 for (LiveInterval::SubRange
&R
: LHS
.subranges()) {
2472 unsigned Mask
= TRI
->composeSubRegIndexLaneMask(DstIdx
, R
.LaneMask
);
2476 DEBUG(dbgs() << "\t\tLHST = " << PrintReg(CP
.getDstReg())
2477 << ' ' << LHS
<< '\n');
2479 // Determine lanemasks of RHS in the coalesced register and merge subranges.
2480 unsigned SrcIdx
= CP
.getSrcIdx();
2481 if (!RHS
.hasSubRanges()) {
2482 unsigned Mask
= SrcIdx
== 0 ? CP
.getNewRC()->getLaneMask()
2483 : TRI
->getSubRegIndexLaneMask(SrcIdx
);
2484 mergeSubRangeInto(LHS
, RHS
, Mask
, CP
);
2486 // Pair up subranges and merge.
2487 for (LiveInterval::SubRange
&R
: RHS
.subranges()) {
2488 unsigned Mask
= TRI
->composeSubRegIndexLaneMask(SrcIdx
, R
.LaneMask
);
2489 mergeSubRangeInto(LHS
, R
, Mask
, CP
);
2493 DEBUG(dbgs() << "\tJoined SubRanges " << LHS
<< "\n");
2495 LHSVals
.pruneSubRegValues(LHS
, ShrinkMask
);
2496 RHSVals
.pruneSubRegValues(LHS
, ShrinkMask
);
2499 // The merging algorithm in LiveInterval::join() can't handle conflicting
2500 // value mappings, so we need to remove any live ranges that overlap a
2501 // CR_Replace resolution. Collect a set of end points that can be used to
2502 // restore the live range after joining.
2503 SmallVector
<SlotIndex
, 8> EndPoints
;
2504 LHSVals
.pruneValues(RHSVals
, EndPoints
, true);
2505 RHSVals
.pruneValues(LHSVals
, EndPoints
, true);
2507 // Erase COPY and IMPLICIT_DEF instructions. This may cause some external
2508 // registers to require trimming.
2509 SmallVector
<unsigned, 8> ShrinkRegs
;
2510 LHSVals
.eraseInstrs(ErasedInstrs
, ShrinkRegs
);
2511 RHSVals
.eraseInstrs(ErasedInstrs
, ShrinkRegs
);
2512 while (!ShrinkRegs
.empty())
2513 LIS
->shrinkToUses(&LIS
->getInterval(ShrinkRegs
.pop_back_val()));
2515 // Join RHS into LHS.
2516 LHS
.join(RHS
, LHSVals
.getAssignments(), RHSVals
.getAssignments(), NewVNInfo
);
2518 // Kill flags are going to be wrong if the live ranges were overlapping.
2519 // Eventually, we should simply clear all kill flags when computing live
2520 // ranges. They are reinserted after register allocation.
2521 MRI
->clearKillFlags(LHS
.reg
);
2522 MRI
->clearKillFlags(RHS
.reg
);
2524 if (!EndPoints
.empty()) {
2525 // Recompute the parts of the live range we had to remove because of
2526 // CR_Replace conflicts.
2527 DEBUG(dbgs() << "\t\trestoring liveness to " << EndPoints
.size()
2528 << " points: " << LHS
<< '\n');
2529 LIS
->extendToIndices((LiveRange
&)LHS
, EndPoints
);
2535 /// Attempt to join these two intervals. On failure, this returns false.
2536 bool RegisterCoalescer::joinIntervals(CoalescerPair
&CP
) {
2537 return CP
.isPhys() ? joinReservedPhysReg(CP
) : joinVirtRegs(CP
);
2541 // Information concerning MBB coalescing priority.
2542 struct MBBPriorityInfo
{
2543 MachineBasicBlock
*MBB
;
2547 MBBPriorityInfo(MachineBasicBlock
*mbb
, unsigned depth
, bool issplit
)
2548 : MBB(mbb
), Depth(depth
), IsSplit(issplit
) {}
2552 // C-style comparator that sorts first based on the loop depth of the basic
2553 // block (the unsigned), and then on the MBB number.
2555 // EnableGlobalCopies assumes that the primary sort key is loop depth.
2556 static int compareMBBPriority(const MBBPriorityInfo
*LHS
,
2557 const MBBPriorityInfo
*RHS
) {
2558 // Deeper loops first
2559 if (LHS
->Depth
!= RHS
->Depth
)
2560 return LHS
->Depth
> RHS
->Depth
? -1 : 1;
2562 // Try to unsplit critical edges next.
2563 if (LHS
->IsSplit
!= RHS
->IsSplit
)
2564 return LHS
->IsSplit
? -1 : 1;
2566 // Prefer blocks that are more connected in the CFG. This takes care of
2567 // the most difficult copies first while intervals are short.
2568 unsigned cl
= LHS
->MBB
->pred_size() + LHS
->MBB
->succ_size();
2569 unsigned cr
= RHS
->MBB
->pred_size() + RHS
->MBB
->succ_size();
2571 return cl
> cr
? -1 : 1;
2573 // As a last resort, sort by block number.
2574 return LHS
->MBB
->getNumber() < RHS
->MBB
->getNumber() ? -1 : 1;
2577 /// \returns true if the given copy uses or defines a local live range.
2578 static bool isLocalCopy(MachineInstr
*Copy
, const LiveIntervals
*LIS
) {
2579 if (!Copy
->isCopy())
2582 if (Copy
->getOperand(1).isUndef())
2585 unsigned SrcReg
= Copy
->getOperand(1).getReg();
2586 unsigned DstReg
= Copy
->getOperand(0).getReg();
2587 if (TargetRegisterInfo::isPhysicalRegister(SrcReg
)
2588 || TargetRegisterInfo::isPhysicalRegister(DstReg
))
2591 return LIS
->intervalIsInOneMBB(LIS
->getInterval(SrcReg
))
2592 || LIS
->intervalIsInOneMBB(LIS
->getInterval(DstReg
));
2595 // Try joining WorkList copies starting from index From.
2596 // Null out any successful joins.
2597 bool RegisterCoalescer::
2598 copyCoalesceWorkList(MutableArrayRef
<MachineInstr
*> CurrList
) {
2599 bool Progress
= false;
2600 for (unsigned i
= 0, e
= CurrList
.size(); i
!= e
; ++i
) {
2603 // Skip instruction pointers that have already been erased, for example by
2604 // dead code elimination.
2605 if (ErasedInstrs
.erase(CurrList
[i
])) {
2606 CurrList
[i
] = nullptr;
2610 bool Success
= joinCopy(CurrList
[i
], Again
);
2611 Progress
|= Success
;
2612 if (Success
|| !Again
)
2613 CurrList
[i
] = nullptr;
2619 RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock
*MBB
) {
2620 DEBUG(dbgs() << MBB
->getName() << ":\n");
2622 // Collect all copy-like instructions in MBB. Don't start coalescing anything
2623 // yet, it might invalidate the iterator.
2624 const unsigned PrevSize
= WorkList
.size();
2625 if (JoinGlobalCopies
) {
2626 // Coalesce copies bottom-up to coalesce local defs before local uses. They
2627 // are not inherently easier to resolve, but slightly preferable until we
2628 // have local live range splitting. In particular this is required by
2629 // cmp+jmp macro fusion.
2630 for (MachineBasicBlock::iterator MII
= MBB
->begin(), E
= MBB
->end();
2632 if (!MII
->isCopyLike())
2634 if (isLocalCopy(&(*MII
), LIS
))
2635 LocalWorkList
.push_back(&(*MII
));
2637 WorkList
.push_back(&(*MII
));
2641 for (MachineBasicBlock::iterator MII
= MBB
->begin(), E
= MBB
->end();
2643 if (MII
->isCopyLike())
2644 WorkList
.push_back(MII
);
2646 // Try coalescing the collected copies immediately, and remove the nulls.
2647 // This prevents the WorkList from getting too large since most copies are
2648 // joinable on the first attempt.
2649 MutableArrayRef
<MachineInstr
*>
2650 CurrList(WorkList
.begin() + PrevSize
, WorkList
.end());
2651 if (copyCoalesceWorkList(CurrList
))
2652 WorkList
.erase(std::remove(WorkList
.begin() + PrevSize
, WorkList
.end(),
2653 (MachineInstr
*)nullptr), WorkList
.end());
2656 void RegisterCoalescer::coalesceLocals() {
2657 copyCoalesceWorkList(LocalWorkList
);
2658 for (unsigned j
= 0, je
= LocalWorkList
.size(); j
!= je
; ++j
) {
2659 if (LocalWorkList
[j
])
2660 WorkList
.push_back(LocalWorkList
[j
]);
2662 LocalWorkList
.clear();
2665 void RegisterCoalescer::joinAllIntervals() {
2666 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
2667 assert(WorkList
.empty() && LocalWorkList
.empty() && "Old data still around.");
2669 std::vector
<MBBPriorityInfo
> MBBs
;
2670 MBBs
.reserve(MF
->size());
2671 for (MachineFunction::iterator I
= MF
->begin(), E
= MF
->end();I
!= E
;++I
){
2672 MachineBasicBlock
*MBB
= I
;
2673 MBBs
.push_back(MBBPriorityInfo(MBB
, Loops
->getLoopDepth(MBB
),
2674 JoinSplitEdges
&& isSplitEdge(MBB
)));
2676 array_pod_sort(MBBs
.begin(), MBBs
.end(), compareMBBPriority
);
2678 // Coalesce intervals in MBB priority order.
2679 unsigned CurrDepth
= UINT_MAX
;
2680 for (unsigned i
= 0, e
= MBBs
.size(); i
!= e
; ++i
) {
2681 // Try coalescing the collected local copies for deeper loops.
2682 if (JoinGlobalCopies
&& MBBs
[i
].Depth
< CurrDepth
) {
2684 CurrDepth
= MBBs
[i
].Depth
;
2686 copyCoalesceInMBB(MBBs
[i
].MBB
);
2690 // Joining intervals can allow other intervals to be joined. Iteratively join
2691 // until we make no progress.
2692 while (copyCoalesceWorkList(WorkList
))
2696 void RegisterCoalescer::releaseMemory() {
2697 ErasedInstrs
.clear();
2700 InflateRegs
.clear();
2703 bool RegisterCoalescer::runOnMachineFunction(MachineFunction
&fn
) {
2705 MRI
= &fn
.getRegInfo();
2706 TM
= &fn
.getTarget();
2707 TRI
= TM
->getSubtargetImpl()->getRegisterInfo();
2708 TII
= TM
->getSubtargetImpl()->getInstrInfo();
2709 LIS
= &getAnalysis
<LiveIntervals
>();
2710 AA
= &getAnalysis
<AliasAnalysis
>();
2711 Loops
= &getAnalysis
<MachineLoopInfo
>();
2713 const TargetSubtargetInfo
&ST
= TM
->getSubtarget
<TargetSubtargetInfo
>();
2714 if (EnableGlobalCopies
== cl::BOU_UNSET
)
2715 JoinGlobalCopies
= ST
.useMachineScheduler();
2717 JoinGlobalCopies
= (EnableGlobalCopies
== cl::BOU_TRUE
);
2719 // The MachineScheduler does not currently require JoinSplitEdges. This will
2720 // either be enabled unconditionally or replaced by a more general live range
2721 // splitting optimization.
2722 JoinSplitEdges
= EnableJoinSplits
;
2724 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
2725 << "********** Function: " << MF
->getName() << '\n');
2727 if (VerifyCoalescing
)
2728 MF
->verify(this, "Before register coalescing");
2730 RegClassInfo
.runOnMachineFunction(fn
);
2732 // Join (coalesce) intervals if requested.
2736 // After deleting a lot of copies, register classes may be less constrained.
2737 // Removing sub-register operands may allow GR32_ABCD -> GR32 and DPR_VFP2 ->
2739 array_pod_sort(InflateRegs
.begin(), InflateRegs
.end());
2740 InflateRegs
.erase(std::unique(InflateRegs
.begin(), InflateRegs
.end()),
2742 DEBUG(dbgs() << "Trying to inflate " << InflateRegs
.size() << " regs.\n");
2743 for (unsigned i
= 0, e
= InflateRegs
.size(); i
!= e
; ++i
) {
2744 unsigned Reg
= InflateRegs
[i
];
2745 if (MRI
->reg_nodbg_empty(Reg
))
2747 if (MRI
->recomputeRegClass(Reg
, *TM
)) {
2748 DEBUG(dbgs() << PrintReg(Reg
) << " inflated to "
2749 << TRI
->getRegClassName(MRI
->getRegClass(Reg
)) << '\n');
2750 LiveInterval
&LI
= LIS
->getInterval(Reg
);
2751 unsigned MaxMask
= MRI
->getMaxLaneMaskForVReg(Reg
);
2753 // If the inflated register class does not support subregisters anymore
2754 // remove the subranges.
2755 LI
.clearSubRanges();
2757 // If subranges are still supported, then the same subregs should still
2760 for (LiveInterval::SubRange
&S
: LI
.subranges()) {
2761 assert ((S
.LaneMask
& ~MaxMask
) == 0);
2770 if (VerifyCoalescing
)
2771 MF
->verify(this, "After register coalescing");
2775 /// Implement the dump method.
2776 void RegisterCoalescer::print(raw_ostream
&O
, const Module
* m
) const {