src/llvm/lib/CodeGen/TargetInstrInfo.cpp

   1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/Target/TargetInstrInfo.h"
  15 #include "llvm/CodeGen/MachineFrameInfo.h"
  16 #include "llvm/CodeGen/MachineInstrBuilder.h"
  17 #include "llvm/CodeGen/MachineMemOperand.h"
  18 #include "llvm/CodeGen/MachineRegisterInfo.h"
  19 #include "llvm/CodeGen/PseudoSourceValue.h"
  20 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
  21 #include "llvm/CodeGen/StackMaps.h"
  22 #include "llvm/IR/DataLayout.h"
  23 #include "llvm/MC/MCAsmInfo.h"
  24 #include "llvm/MC/MCInstrItineraries.h"
  25 #include "llvm/Support/CommandLine.h"
  26 #include "llvm/Support/ErrorHandling.h"
  27 #include "llvm/Support/raw_ostream.h"
  28 #include "llvm/Target/TargetFrameLowering.h"
  29 #include "llvm/Target/TargetLowering.h"
  30 #include "llvm/Target/TargetMachine.h"
  31 #include "llvm/Target/TargetRegisterInfo.h"
  32 #include <cctype>
  33 using namespace llvm;
  34
  35 static cl::opt<bool> DisableHazardRecognizer(
  36   "disable-sched-hazard", cl::Hidden, cl::init(false),
  37   cl::desc("Disable hazard detection during preRA scheduling"));
  38
  39 TargetInstrInfo::~TargetInstrInfo() {
  40 }
  41
  42 const TargetRegisterClass*
  43 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
  44                              const TargetRegisterInfo *TRI,
  45                              const MachineFunction &MF) const {
  46   if (OpNum >= MCID.getNumOperands())
  47     return nullptr;
  48
  49   short RegClass = MCID.OpInfo[OpNum].RegClass;
  50   if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
  51     return TRI->getPointerRegClass(MF, RegClass);
  52
  53   // Instructions like INSERT_SUBREG do not have fixed register classes.
  54   if (RegClass < 0)
  55     return nullptr;
  56
  57   // Otherwise just look it up normally.
  58   return TRI->getRegClass(RegClass);
  59 }
  60
  61 /// insertNoop - Insert a noop into the instruction stream at the specified
  62 /// point.
  63 void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
  64                                  MachineBasicBlock::iterator MI) const {
  65   llvm_unreachable("Target didn't implement insertNoop!");
  66 }
  67
  68 /// Measure the specified inline asm to determine an approximation of its
  69 /// length.
  70 /// Comments (which run till the next SeparatorString or newline) do not
  71 /// count as an instruction.
  72 /// Any other non-whitespace text is considered an instruction, with
  73 /// multiple instructions separated by SeparatorString or newlines.
  74 /// Variable-length instructions are not handled here; this function
  75 /// may be overloaded in the target code to do that.
  76 unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
  77                                              const MCAsmInfo &MAI) const {
  78
  79
  80   // Count the number of instructions in the asm.
  81   bool atInsnStart = true;
  82   unsigned Length = 0;
  83   for (; *Str; ++Str) {
  84     if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
  85                                 strlen(MAI.getSeparatorString())) == 0)
  86       atInsnStart = true;
  87     if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
  88       Length += MAI.getMaxInstLength();
  89       atInsnStart = false;
  90     }
  91     if (atInsnStart && strncmp(Str, MAI.getCommentString(),
  92                                strlen(MAI.getCommentString())) == 0)
  93       atInsnStart = false;
  94   }
  95
  96   return Length;
  97 }
  98
  99 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
 100 /// after it, replacing it with an unconditional branch to NewDest.
 101 void
 102 TargetInstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
 103                                          MachineBasicBlock *NewDest) const {
 104   MachineBasicBlock *MBB = Tail->getParent();
 105
 106   // Remove all the old successors of MBB from the CFG.
 107   while (!MBB->succ_empty())
 108     MBB->removeSuccessor(MBB->succ_begin());
 109
 110   // Remove all the dead instructions from the end of MBB.
 111   MBB->erase(Tail, MBB->end());
 112
 113   // If MBB isn't immediately before MBB, insert a branch to it.
 114   if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest))
 115     InsertBranch(*MBB, NewDest, nullptr, SmallVector<MachineOperand, 0>(),
 116                  Tail->getDebugLoc());
 117   MBB->addSuccessor(NewDest);
 118 }
 119
 120 // commuteInstruction - The default implementation of this method just exchanges
 121 // the two operands returned by findCommutedOpIndices.
 122 MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI,
 123                                                   bool NewMI) const {
 124   const MCInstrDesc &MCID = MI->getDesc();
 125   bool HasDef = MCID.getNumDefs();
 126   if (HasDef && !MI->getOperand(0).isReg())
 127     // No idea how to commute this instruction. Target should implement its own.
 128     return nullptr;
 129   unsigned Idx1, Idx2;
 130   if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
 131     assert(MI->isCommutable() && "Precondition violation: MI must be commutable.");
 132     return nullptr;
 133   }
 134
 135   assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
 136          "This only knows how to commute register operands so far");
 137   unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
 138   unsigned Reg1 = MI->getOperand(Idx1).getReg();
 139   unsigned Reg2 = MI->getOperand(Idx2).getReg();
 140   unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0;
 141   unsigned SubReg1 = MI->getOperand(Idx1).getSubReg();
 142   unsigned SubReg2 = MI->getOperand(Idx2).getSubReg();
 143   bool Reg1IsKill = MI->getOperand(Idx1).isKill();
 144   bool Reg2IsKill = MI->getOperand(Idx2).isKill();
 145   // If destination is tied to either of the commuted source register, then
 146   // it must be updated.
 147   if (HasDef && Reg0 == Reg1 &&
 148       MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
 149     Reg2IsKill = false;
 150     Reg0 = Reg2;
 151     SubReg0 = SubReg2;
 152   } else if (HasDef && Reg0 == Reg2 &&
 153              MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
 154     Reg1IsKill = false;
 155     Reg0 = Reg1;
 156     SubReg0 = SubReg1;
 157   }
 158
 159   if (NewMI) {
 160     // Create a new instruction.
 161     MachineFunction &MF = *MI->getParent()->getParent();
 162     MI = MF.CloneMachineInstr(MI);
 163   }
 164
 165   if (HasDef) {
 166     MI->getOperand(0).setReg(Reg0);
 167     MI->getOperand(0).setSubReg(SubReg0);
 168   }
 169   MI->getOperand(Idx2).setReg(Reg1);
 170   MI->getOperand(Idx1).setReg(Reg2);
 171   MI->getOperand(Idx2).setSubReg(SubReg1);
 172   MI->getOperand(Idx1).setSubReg(SubReg2);
 173   MI->getOperand(Idx2).setIsKill(Reg1IsKill);
 174   MI->getOperand(Idx1).setIsKill(Reg2IsKill);
 175   return MI;
 176 }
 177
 178 /// findCommutedOpIndices - If specified MI is commutable, return the two
 179 /// operand indices that would swap value. Return true if the instruction
 180 /// is not in a form which this routine understands.
 181 bool TargetInstrInfo::findCommutedOpIndices(MachineInstr *MI,
 182                                             unsigned &SrcOpIdx1,
 183                                             unsigned &SrcOpIdx2) const {
 184   assert(!MI->isBundle() &&
 185          "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
 186
 187   const MCInstrDesc &MCID = MI->getDesc();
 188   if (!MCID.isCommutable())
 189     return false;
 190   // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
 191   // is not true, then the target must implement this.
 192   SrcOpIdx1 = MCID.getNumDefs();
 193   SrcOpIdx2 = SrcOpIdx1 + 1;
 194   if (!MI->getOperand(SrcOpIdx1).isReg() ||
 195       !MI->getOperand(SrcOpIdx2).isReg())
 196     // No idea.
 197     return false;
 198   return true;
 199 }
 200
 201
 202 bool
 203 TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
 204   if (!MI->isTerminator()) return false;
 205
 206   // Conditional branch is a special case.
 207   if (MI->isBranch() && !MI->isBarrier())
 208     return true;
 209   if (!MI->isPredicable())
 210     return true;
 211   return !isPredicated(MI);
 212 }
 213
 214
 215 bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
 216                             const SmallVectorImpl<MachineOperand> &Pred) const {
 217   bool MadeChange = false;
 218
 219   assert(!MI->isBundle() &&
 220          "TargetInstrInfo::PredicateInstruction() can't handle bundles");
 221
 222   const MCInstrDesc &MCID = MI->getDesc();
 223   if (!MI->isPredicable())
 224     return false;
 225
 226   for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
 227     if (MCID.OpInfo[i].isPredicate()) {
 228       MachineOperand &MO = MI->getOperand(i);
 229       if (MO.isReg()) {
 230         MO.setReg(Pred[j].getReg());
 231         MadeChange = true;
 232       } else if (MO.isImm()) {
 233         MO.setImm(Pred[j].getImm());
 234         MadeChange = true;
 235       } else if (MO.isMBB()) {
 236         MO.setMBB(Pred[j].getMBB());
 237         MadeChange = true;
 238       }
 239       ++j;
 240     }
 241   }
 242   return MadeChange;
 243 }
 244
 245 bool TargetInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
 246                                            const MachineMemOperand *&MMO,
 247                                            int &FrameIndex) const {
 248   for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
 249          oe = MI->memoperands_end();
 250        o != oe;
 251        ++o) {
 252     if ((*o)->isLoad()) {
 253       if (const FixedStackPseudoSourceValue *Value =
 254           dyn_cast_or_null<FixedStackPseudoSourceValue>(
 255               (*o)->getPseudoValue())) {
 256         FrameIndex = Value->getFrameIndex();
 257         MMO = *o;
 258         return true;
 259       }
 260     }
 261   }
 262   return false;
 263 }
 264
 265 bool TargetInstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
 266                                           const MachineMemOperand *&MMO,
 267                                           int &FrameIndex) const {
 268   for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
 269          oe = MI->memoperands_end();
 270        o != oe;
 271        ++o) {
 272     if ((*o)->isStore()) {
 273       if (const FixedStackPseudoSourceValue *Value =
 274           dyn_cast_or_null<FixedStackPseudoSourceValue>(
 275               (*o)->getPseudoValue())) {
 276         FrameIndex = Value->getFrameIndex();
 277         MMO = *o;
 278         return true;
 279       }
 280     }
 281   }
 282   return false;
 283 }
 284
 285 bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
 286                                         unsigned SubIdx, unsigned &Size,
 287                                         unsigned &Offset,
 288                                         const TargetMachine *TM) const {
 289   if (!SubIdx) {
 290     Size = RC->getSize();
 291     Offset = 0;
 292     return true;
 293   }
 294   unsigned BitSize =
 295       TM->getSubtargetImpl()->getRegisterInfo()->getSubRegIdxSize(SubIdx);
 296   // Convert bit size to byte size to be consistent with
 297   // MCRegisterClass::getSize().
 298   if (BitSize % 8)
 299     return false;
 300
 301   int BitOffset =
 302       TM->getSubtargetImpl()->getRegisterInfo()->getSubRegIdxOffset(SubIdx);
 303   if (BitOffset < 0 || BitOffset % 8)
 304     return false;
 305
 306   Size = BitSize /= 8;
 307   Offset = (unsigned)BitOffset / 8;
 308
 309   assert(RC->getSize() >= (Offset + Size) && "bad subregister range");
 310
 311   if (!TM->getSubtargetImpl()->getDataLayout()->isLittleEndian()) {
 312     Offset = RC->getSize() - (Offset + Size);
 313   }
 314   return true;
 315 }
 316
 317 void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
 318                                     MachineBasicBlock::iterator I,
 319                                     unsigned DestReg,
 320                                     unsigned SubIdx,
 321                                     const MachineInstr *Orig,
 322                                     const TargetRegisterInfo &TRI) const {
 323   MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
 324   MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
 325   MBB.insert(I, MI);
 326 }
 327
 328 bool
 329 TargetInstrInfo::produceSameValue(const MachineInstr *MI0,
 330                                   const MachineInstr *MI1,
 331                                   const MachineRegisterInfo *MRI) const {
 332   return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
 333 }
 334
 335 MachineInstr *TargetInstrInfo::duplicate(MachineInstr *Orig,
 336                                          MachineFunction &MF) const {
 337   assert(!Orig->isNotDuplicable() &&
 338          "Instruction cannot be duplicated");
 339   return MF.CloneMachineInstr(Orig);
 340 }
 341
 342 // If the COPY instruction in MI can be folded to a stack operation, return
 343 // the register class to use.
 344 static const TargetRegisterClass *canFoldCopy(const MachineInstr *MI,
 345                                               unsigned FoldIdx) {
 346   assert(MI->isCopy() && "MI must be a COPY instruction");
 347   if (MI->getNumOperands() != 2)
 348     return nullptr;
 349   assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
 350
 351   const MachineOperand &FoldOp = MI->getOperand(FoldIdx);
 352   const MachineOperand &LiveOp = MI->getOperand(1-FoldIdx);
 353
 354   if (FoldOp.getSubReg() || LiveOp.getSubReg())
 355     return nullptr;
 356
 357   unsigned FoldReg = FoldOp.getReg();
 358   unsigned LiveReg = LiveOp.getReg();
 359
 360   assert(TargetRegisterInfo::isVirtualRegister(FoldReg) &&
 361          "Cannot fold physregs");
 362
 363   const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
 364   const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
 365
 366   if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
 367     return RC->contains(LiveOp.getReg()) ? RC : nullptr;
 368
 369   if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
 370     return RC;
 371
 372   // FIXME: Allow folding when register classes are memory compatible.
 373   return nullptr;
 374 }
 375
 376 void TargetInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
 377   llvm_unreachable("Not a MachO target");
 378 }
 379
 380 bool TargetInstrInfo::
 381 canFoldMemoryOperand(const MachineInstr *MI,
 382                      const SmallVectorImpl<unsigned> &Ops) const {
 383   return MI->isCopy() && Ops.size() == 1 && canFoldCopy(MI, Ops[0]);
 384 }
 385
 386 static MachineInstr* foldPatchpoint(MachineFunction &MF,
 387                                     MachineInstr *MI,
 388                                     const SmallVectorImpl<unsigned> &Ops,
 389                                     int FrameIndex,
 390                                     const TargetInstrInfo &TII) {
 391   unsigned StartIdx = 0;
 392   switch (MI->getOpcode()) {
 393   case TargetOpcode::STACKMAP:
 394     StartIdx = 2; // Skip ID, nShadowBytes.
 395     break;
 396   case TargetOpcode::PATCHPOINT: {
 397     // For PatchPoint, the call args are not foldable.
 398     PatchPointOpers opers(MI);
 399     StartIdx = opers.getVarIdx();
 400     break;
 401   }
 402   default:
 403     llvm_unreachable("unexpected stackmap opcode");
 404   }
 405
 406   // Return false if any operands requested for folding are not foldable (not
 407   // part of the stackmap's live values).
 408   for (SmallVectorImpl<unsigned>::const_iterator I = Ops.begin(), E = Ops.end();
 409        I != E; ++I) {
 410     if (*I < StartIdx)
 411       return nullptr;
 412   }
 413
 414   MachineInstr *NewMI =
 415     MF.CreateMachineInstr(TII.get(MI->getOpcode()), MI->getDebugLoc(), true);
 416   MachineInstrBuilder MIB(MF, NewMI);
 417
 418   // No need to fold return, the meta data, and function arguments
 419   for (unsigned i = 0; i < StartIdx; ++i)
 420     MIB.addOperand(MI->getOperand(i));
 421
 422   for (unsigned i = StartIdx; i < MI->getNumOperands(); ++i) {
 423     MachineOperand &MO = MI->getOperand(i);
 424     if (std::find(Ops.begin(), Ops.end(), i) != Ops.end()) {
 425       unsigned SpillSize;
 426       unsigned SpillOffset;
 427       // Compute the spill slot size and offset.
 428       const TargetRegisterClass *RC =
 429         MF.getRegInfo().getRegClass(MO.getReg());
 430       bool Valid = TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize,
 431                                          SpillOffset, &MF.getTarget());
 432       if (!Valid)
 433         report_fatal_error("cannot spill patchpoint subregister operand");
 434       MIB.addImm(StackMaps::IndirectMemRefOp);
 435       MIB.addImm(SpillSize);
 436       MIB.addFrameIndex(FrameIndex);
 437       MIB.addImm(SpillOffset);
 438     }
 439     else
 440       MIB.addOperand(MO);
 441   }
 442   return NewMI;
 443 }
 444
 445 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
 446 /// slot into the specified machine instruction for the specified operand(s).
 447 /// If this is possible, a new instruction is returned with the specified
 448 /// operand folded, otherwise NULL is returned. The client is responsible for
 449 /// removing the old instruction and adding the new one in the instruction
 450 /// stream.
 451 MachineInstr*
 452 TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
 453                                    const SmallVectorImpl<unsigned> &Ops,
 454                                    int FI) const {
 455   unsigned Flags = 0;
 456   for (unsigned i = 0, e = Ops.size(); i != e; ++i)
 457     if (MI->getOperand(Ops[i]).isDef())
 458       Flags |= MachineMemOperand::MOStore;
 459     else
 460       Flags |= MachineMemOperand::MOLoad;
 461
 462   MachineBasicBlock *MBB = MI->getParent();
 463   assert(MBB && "foldMemoryOperand needs an inserted instruction");
 464   MachineFunction &MF = *MBB->getParent();
 465
 466   MachineInstr *NewMI = nullptr;
 467
 468   if (MI->getOpcode() == TargetOpcode::STACKMAP ||
 469       MI->getOpcode() == TargetOpcode::PATCHPOINT) {
 470     // Fold stackmap/patchpoint.
 471     NewMI = foldPatchpoint(MF, MI, Ops, FI, *this);
 472   } else {
 473     // Ask the target to do the actual folding.
 474     NewMI =foldMemoryOperandImpl(MF, MI, Ops, FI);
 475   }
 476
 477   if (NewMI) {
 478     NewMI->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
 479     // Add a memory operand, foldMemoryOperandImpl doesn't do that.
 480     assert((!(Flags & MachineMemOperand::MOStore) ||
 481             NewMI->mayStore()) &&
 482            "Folded a def to a non-store!");
 483     assert((!(Flags & MachineMemOperand::MOLoad) ||
 484             NewMI->mayLoad()) &&
 485            "Folded a use to a non-load!");
 486     const MachineFrameInfo &MFI = *MF.getFrameInfo();
 487     assert(MFI.getObjectOffset(FI) != -1);
 488     MachineMemOperand *MMO =
 489       MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
 490                               Flags, MFI.getObjectSize(FI),
 491                               MFI.getObjectAlignment(FI));
 492     NewMI->addMemOperand(MF, MMO);
 493
 494     // FIXME: change foldMemoryOperandImpl semantics to also insert NewMI.
 495     return MBB->insert(MI, NewMI);
 496   }
 497
 498   // Straight COPY may fold as load/store.
 499   if (!MI->isCopy() || Ops.size() != 1)
 500     return nullptr;
 501
 502   const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
 503   if (!RC)
 504     return nullptr;
 505
 506   const MachineOperand &MO = MI->getOperand(1-Ops[0]);
 507   MachineBasicBlock::iterator Pos = MI;
 508   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
 509
 510   if (Flags == MachineMemOperand::MOStore)
 511     storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
 512   else
 513     loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
 514   return --Pos;
 515 }
 516
 517 /// foldMemoryOperand - Same as the previous version except it allows folding
 518 /// of any load and store from / to any address, not just from a specific
 519 /// stack slot.
 520 MachineInstr*
 521 TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
 522                                    const SmallVectorImpl<unsigned> &Ops,
 523                                    MachineInstr* LoadMI) const {
 524   assert(LoadMI->canFoldAsLoad() && "LoadMI isn't foldable!");
 525 #ifndef NDEBUG
 526   for (unsigned i = 0, e = Ops.size(); i != e; ++i)
 527     assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
 528 #endif
 529   MachineBasicBlock &MBB = *MI->getParent();
 530   MachineFunction &MF = *MBB.getParent();
 531
 532   // Ask the target to do the actual folding.
 533   MachineInstr *NewMI = nullptr;
 534   int FrameIndex = 0;
 535
 536   if ((MI->getOpcode() == TargetOpcode::STACKMAP ||
 537        MI->getOpcode() == TargetOpcode::PATCHPOINT) &&
 538       isLoadFromStackSlot(LoadMI, FrameIndex)) {
 539     // Fold stackmap/patchpoint.
 540     NewMI = foldPatchpoint(MF, MI, Ops, FrameIndex, *this);
 541   } else {
 542     // Ask the target to do the actual folding.
 543     NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI);
 544   }
 545
 546   if (!NewMI) return nullptr;
 547
 548   NewMI = MBB.insert(MI, NewMI);
 549
 550   // Copy the memoperands from the load to the folded instruction.
 551   if (MI->memoperands_empty()) {
 552     NewMI->setMemRefs(LoadMI->memoperands_begin(),
 553                       LoadMI->memoperands_end());
 554   }
 555   else {
 556     // Handle the rare case of folding multiple loads.
 557     NewMI->setMemRefs(MI->memoperands_begin(),
 558                       MI->memoperands_end());
 559     for (MachineInstr::mmo_iterator I = LoadMI->memoperands_begin(),
 560            E = LoadMI->memoperands_end(); I != E; ++I) {
 561       NewMI->addMemOperand(MF, *I);
 562     }
 563   }
 564   return NewMI;
 565 }
 566
 567 bool TargetInstrInfo::
 568 isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
 569                                          AliasAnalysis *AA) const {
 570   const MachineFunction &MF = *MI->getParent()->getParent();
 571   const MachineRegisterInfo &MRI = MF.getRegInfo();
 572
 573   // Remat clients assume operand 0 is the defined register.
 574   if (!MI->getNumOperands() || !MI->getOperand(0).isReg())
 575     return false;
 576   unsigned DefReg = MI->getOperand(0).getReg();
 577
 578   // A sub-register definition can only be rematerialized if the instruction
 579   // doesn't read the other parts of the register.  Otherwise it is really a
 580   // read-modify-write operation on the full virtual register which cannot be
 581   // moved safely.
 582   if (TargetRegisterInfo::isVirtualRegister(DefReg) &&
 583       MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
 584     return false;
 585
 586   // A load from a fixed stack slot can be rematerialized. This may be
 587   // redundant with subsequent checks, but it's target-independent,
 588   // simple, and a common case.
 589   int FrameIdx = 0;
 590   if (isLoadFromStackSlot(MI, FrameIdx) &&
 591       MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx))
 592     return true;
 593
 594   // Avoid instructions obviously unsafe for remat.
 595   if (MI->isNotDuplicable() || MI->mayStore() ||
 596       MI->hasUnmodeledSideEffects())
 597     return false;
 598
 599   // Don't remat inline asm. We have no idea how expensive it is
 600   // even if it's side effect free.
 601   if (MI->isInlineAsm())
 602     return false;
 603
 604   // Avoid instructions which load from potentially varying memory.
 605   if (MI->mayLoad() && !MI->isInvariantLoad(AA))
 606     return false;
 607
 608   // If any of the registers accessed are non-constant, conservatively assume
 609   // the instruction is not rematerializable.
 610   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
 611     const MachineOperand &MO = MI->getOperand(i);
 612     if (!MO.isReg()) continue;
 613     unsigned Reg = MO.getReg();
 614     if (Reg == 0)
 615       continue;
 616
 617     // Check for a well-behaved physical register.
 618     if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
 619       if (MO.isUse()) {
 620         // If the physreg has no defs anywhere, it's just an ambient register
 621         // and we can freely move its uses. Alternatively, if it's allocatable,
 622         // it could get allocated to something with a def during allocation.
 623         if (!MRI.isConstantPhysReg(Reg, MF))
 624           return false;
 625       } else {
 626         // A physreg def. We can't remat it.
 627         return false;
 628       }
 629       continue;
 630     }
 631
 632     // Only allow one virtual-register def.  There may be multiple defs of the
 633     // same virtual register, though.
 634     if (MO.isDef() && Reg != DefReg)
 635       return false;
 636
 637     // Don't allow any virtual-register uses. Rematting an instruction with
 638     // virtual register uses would length the live ranges of the uses, which
 639     // is not necessarily a good idea, certainly not "trivial".
 640     if (MO.isUse())
 641       return false;
 642   }
 643
 644   // Everything checked out.
 645   return true;
 646 }
 647
 648 int TargetInstrInfo::getSPAdjust(const MachineInstr *MI) const {
 649   const MachineFunction *MF = MI->getParent()->getParent();
 650   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
 651   bool StackGrowsDown =
 652     TFI->getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
 653
 654   int FrameSetupOpcode = getCallFrameSetupOpcode();
 655   int FrameDestroyOpcode = getCallFrameDestroyOpcode();
 656
 657   if (MI->getOpcode() != FrameSetupOpcode &&
 658       MI->getOpcode() != FrameDestroyOpcode)
 659     return 0;
 660
 661   int SPAdj = MI->getOperand(0).getImm();
 662
 663   if ((!StackGrowsDown && MI->getOpcode() == FrameSetupOpcode) ||
 664        (StackGrowsDown && MI->getOpcode() == FrameDestroyOpcode))
 665     SPAdj = -SPAdj;
 666
 667   return SPAdj;
 668 }
 669
 670 /// isSchedulingBoundary - Test if the given instruction should be
 671 /// considered a scheduling boundary. This primarily includes labels
 672 /// and terminators.
 673 bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
 674                                            const MachineBasicBlock *MBB,
 675                                            const MachineFunction &MF) const {
 676   // Terminators and labels can't be scheduled around.
 677   if (MI->isTerminator() || MI->isPosition())
 678     return true;
 679
 680   // Don't attempt to schedule around any instruction that defines
 681   // a stack-oriented pointer, as it's unlikely to be profitable. This
 682   // saves compile time, because it doesn't require every single
 683   // stack slot reference to depend on the instruction that does the
 684   // modification.
 685   const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
 686   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
 687   if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI))
 688     return true;
 689
 690   return false;
 691 }
 692
 693 // Provide a global flag for disabling the PreRA hazard recognizer that targets
 694 // may choose to honor.
 695 bool TargetInstrInfo::usePreRAHazardRecognizer() const {
 696   return !DisableHazardRecognizer;
 697 }
 698
 699 // Default implementation of CreateTargetRAHazardRecognizer.
 700 ScheduleHazardRecognizer *TargetInstrInfo::
 701 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
 702                              const ScheduleDAG *DAG) const {
 703   // Dummy hazard recognizer allows all instructions to issue.
 704   return new ScheduleHazardRecognizer();
 705 }
 706
 707 // Default implementation of CreateTargetMIHazardRecognizer.
 708 ScheduleHazardRecognizer *TargetInstrInfo::
 709 CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
 710                                const ScheduleDAG *DAG) const {
 711   return (ScheduleHazardRecognizer *)
 712     new ScoreboardHazardRecognizer(II, DAG, "misched");
 713 }
 714
 715 // Default implementation of CreateTargetPostRAHazardRecognizer.
 716 ScheduleHazardRecognizer *TargetInstrInfo::
 717 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
 718                                    const ScheduleDAG *DAG) const {
 719   return (ScheduleHazardRecognizer *)
 720     new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");
 721 }
 722
 723 //===----------------------------------------------------------------------===//
 724 //  SelectionDAG latency interface.
 725 //===----------------------------------------------------------------------===//
 726
 727 int
 728 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
 729                                    SDNode *DefNode, unsigned DefIdx,
 730                                    SDNode *UseNode, unsigned UseIdx) const {
 731   if (!ItinData || ItinData->isEmpty())
 732     return -1;
 733
 734   if (!DefNode->isMachineOpcode())
 735     return -1;
 736
 737   unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
 738   if (!UseNode->isMachineOpcode())
 739     return ItinData->getOperandCycle(DefClass, DefIdx);
 740   unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
 741   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
 742 }
 743
 744 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
 745                                      SDNode *N) const {
 746   if (!ItinData || ItinData->isEmpty())
 747     return 1;
 748
 749   if (!N->isMachineOpcode())
 750     return 1;
 751
 752   return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
 753 }
 754
 755 //===----------------------------------------------------------------------===//
 756 //  MachineInstr latency interface.
 757 //===----------------------------------------------------------------------===//
 758
 759 unsigned
 760 TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
 761                                 const MachineInstr *MI) const {
 762   if (!ItinData || ItinData->isEmpty())
 763     return 1;
 764
 765   unsigned Class = MI->getDesc().getSchedClass();
 766   int UOps = ItinData->Itineraries[Class].NumMicroOps;
 767   if (UOps >= 0)
 768     return UOps;
 769
 770   // The # of u-ops is dynamically determined. The specific target should
 771   // override this function to return the right number.
 772   return 1;
 773 }
 774
 775 /// Return the default expected latency for a def based on it's opcode.
 776 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel &SchedModel,
 777                                             const MachineInstr *DefMI) const {
 778   if (DefMI->isTransient())
 779     return 0;
 780   if (DefMI->mayLoad())
 781     return SchedModel.LoadLatency;
 782   if (isHighLatencyDef(DefMI->getOpcode()))
 783     return SchedModel.HighLatency;
 784   return 1;
 785 }
 786
 787 unsigned TargetInstrInfo::getPredicationCost(const MachineInstr *) const {
 788   return 0;
 789 }
 790
 791 unsigned TargetInstrInfo::
 792 getInstrLatency(const InstrItineraryData *ItinData,
 793                 const MachineInstr *MI,
 794                 unsigned *PredCost) const {
 795   // Default to one cycle for no itinerary. However, an "empty" itinerary may
 796   // still have a MinLatency property, which getStageLatency checks.
 797   if (!ItinData)
 798     return MI->mayLoad() ? 2 : 1;
 799
 800   return ItinData->getStageLatency(MI->getDesc().getSchedClass());
 801 }
 802
 803 bool TargetInstrInfo::hasLowDefLatency(const InstrItineraryData *ItinData,
 804                                        const MachineInstr *DefMI,
 805                                        unsigned DefIdx) const {
 806   if (!ItinData || ItinData->isEmpty())
 807     return false;
 808
 809   unsigned DefClass = DefMI->getDesc().getSchedClass();
 810   int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
 811   return (DefCycle != -1 && DefCycle <= 1);
 812 }
 813
 814 /// Both DefMI and UseMI must be valid.  By default, call directly to the
 815 /// itinerary. This may be overriden by the target.
 816 int TargetInstrInfo::
 817 getOperandLatency(const InstrItineraryData *ItinData,
 818                   const MachineInstr *DefMI, unsigned DefIdx,
 819                   const MachineInstr *UseMI, unsigned UseIdx) const {
 820   unsigned DefClass = DefMI->getDesc().getSchedClass();
 821   unsigned UseClass = UseMI->getDesc().getSchedClass();
 822   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
 823 }
 824
 825 /// If we can determine the operand latency from the def only, without itinerary
 826 /// lookup, do so. Otherwise return -1.
 827 int TargetInstrInfo::computeDefOperandLatency(
 828   const InstrItineraryData *ItinData,
 829   const MachineInstr *DefMI) const {
 830
 831   // Let the target hook getInstrLatency handle missing itineraries.
 832   if (!ItinData)
 833     return getInstrLatency(ItinData, DefMI);
 834
 835   if(ItinData->isEmpty())
 836     return defaultDefLatency(ItinData->SchedModel, DefMI);
 837
 838   // ...operand lookup required
 839   return -1;
 840 }
 841
 842 /// computeOperandLatency - Compute and return the latency of the given data
 843 /// dependent def and use when the operand indices are already known. UseMI may
 844 /// be NULL for an unknown use.
 845 ///
 846 /// FindMin may be set to get the minimum vs. expected latency. Minimum
 847 /// latency is used for scheduling groups, while expected latency is for
 848 /// instruction cost and critical path.
 849 ///
 850 /// Depending on the subtarget's itinerary properties, this may or may not need
 851 /// to call getOperandLatency(). For most subtargets, we don't need DefIdx or
 852 /// UseIdx to compute min latency.
 853 unsigned TargetInstrInfo::
 854 computeOperandLatency(const InstrItineraryData *ItinData,
 855                       const MachineInstr *DefMI, unsigned DefIdx,
 856                       const MachineInstr *UseMI, unsigned UseIdx) const {
 857
 858   int DefLatency = computeDefOperandLatency(ItinData, DefMI);
 859   if (DefLatency >= 0)
 860     return DefLatency;
 861
 862   assert(ItinData && !ItinData->isEmpty() && "computeDefOperandLatency fail");
 863
 864   int OperLatency = 0;
 865   if (UseMI)
 866     OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
 867   else {
 868     unsigned DefClass = DefMI->getDesc().getSchedClass();
 869     OperLatency = ItinData->getOperandCycle(DefClass, DefIdx);
 870   }
 871   if (OperLatency >= 0)
 872     return OperLatency;
 873
 874   // No operand latency was found.
 875   unsigned InstrLatency = getInstrLatency(ItinData, DefMI);
 876
 877   // Expected latency is the max of the stage latency and itinerary props.
 878   InstrLatency = std::max(InstrLatency,
 879                           defaultDefLatency(ItinData->SchedModel, DefMI));
 880   return InstrLatency;
 881 }
 882
 883 bool TargetInstrInfo::getRegSequenceInputs(
 884     const MachineInstr &MI, unsigned DefIdx,
 885     SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
 886   assert((MI.isRegSequence() ||
 887           MI.isRegSequenceLike()) && "Instruction do not have the proper type");
 888
 889   if (!MI.isRegSequence())
 890     return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);
 891
 892   // We are looking at:
 893   // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
 894   assert(DefIdx == 0 && "REG_SEQUENCE only has one def");
 895   for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx;
 896        OpIdx += 2) {
 897     const MachineOperand &MOReg = MI.getOperand(OpIdx);
 898     const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1);
 899     assert(MOSubIdx.isImm() &&
 900            "One of the subindex of the reg_sequence is not an immediate");
 901     // Record Reg:SubReg, SubIdx.
 902     InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(),
 903                                             (unsigned)MOSubIdx.getImm()));
 904   }
 905   return true;
 906 }
 907
 908 bool TargetInstrInfo::getExtractSubregInputs(
 909     const MachineInstr &MI, unsigned DefIdx,
 910     RegSubRegPairAndIdx &InputReg) const {
 911   assert((MI.isExtractSubreg() ||
 912       MI.isExtractSubregLike()) && "Instruction do not have the proper type");
 913
 914   if (!MI.isExtractSubreg())
 915     return getExtractSubregLikeInputs(MI, DefIdx, InputReg);
 916
 917   // We are looking at:
 918   // Def = EXTRACT_SUBREG v0.sub1, sub0.
 919   assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");
 920   const MachineOperand &MOReg = MI.getOperand(1);
 921   const MachineOperand &MOSubIdx = MI.getOperand(2);
 922   assert(MOSubIdx.isImm() &&
 923          "The subindex of the extract_subreg is not an immediate");
 924
 925   InputReg.Reg = MOReg.getReg();
 926   InputReg.SubReg = MOReg.getSubReg();
 927   InputReg.SubIdx = (unsigned)MOSubIdx.getImm();
 928   return true;
 929 }
 930
 931 bool TargetInstrInfo::getInsertSubregInputs(
 932     const MachineInstr &MI, unsigned DefIdx,
 933     RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const {
 934   assert((MI.isInsertSubreg() ||
 935       MI.isInsertSubregLike()) && "Instruction do not have the proper type");
 936
 937   if (!MI.isInsertSubreg())
 938     return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg);
 939
 940   // We are looking at:
 941   // Def = INSERT_SEQUENCE v0, v1, sub0.
 942   assert(DefIdx == 0 && "INSERT_SUBREG only has one def");
 943   const MachineOperand &MOBaseReg = MI.getOperand(1);
 944   const MachineOperand &MOInsertedReg = MI.getOperand(2);
 945   const MachineOperand &MOSubIdx = MI.getOperand(3);
 946   assert(MOSubIdx.isImm() &&
 947          "One of the subindex of the reg_sequence is not an immediate");
 948   BaseReg.Reg = MOBaseReg.getReg();
 949   BaseReg.SubReg = MOBaseReg.getSubReg();
 950
 951   InsertedReg.Reg = MOInsertedReg.getReg();
 952   InsertedReg.SubReg = MOInsertedReg.getSubReg();
 953   InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm();
 954   return true;
 955 }