1 //===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCSubtargetInfo.h"
11 #include "llvm/ADT/StringRef.h"
12 #include "llvm/ADT/Triple.h"
13 #include "llvm/MC/MCInstrItineraries.h"
14 #include "llvm/MC/SubtargetFeature.h"
15 #include "llvm/Support/raw_ostream.h"
20 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented
21 /// with feature string). Recompute feature bits and scheduling model.
23 MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU
, StringRef FS
) {
24 SubtargetFeatures
Features(FS
);
25 FeatureBits
= Features
.getFeatureBits(CPU
, ProcDesc
, ProcFeatures
);
26 InitCPUSchedModel(CPU
);
30 MCSubtargetInfo::InitCPUSchedModel(StringRef CPU
) {
32 CPUSchedModel
= getSchedModelForCPU(CPU
);
34 CPUSchedModel
= MCSchedModel::GetDefaultSchedModel();
38 MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT
, StringRef CPU
, StringRef FS
,
39 ArrayRef
<SubtargetFeatureKV
> PF
,
40 ArrayRef
<SubtargetFeatureKV
> PD
,
41 const SubtargetInfoKV
*ProcSched
,
42 const MCWriteProcResEntry
*WPR
,
43 const MCWriteLatencyEntry
*WL
,
44 const MCReadAdvanceEntry
*RA
,
51 ProcSchedModels
= ProcSched
;
52 WriteProcResTable
= WPR
;
53 WriteLatencyTable
= WL
;
54 ReadAdvanceTable
= RA
;
60 InitMCProcessorInfo(CPU
, FS
);
63 /// ToggleFeature - Toggle a feature and returns the re-computed feature
64 /// bits. This version does not change the implied bits.
65 uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB
) {
70 /// ToggleFeature - Toggle a feature and returns the re-computed feature
71 /// bits. This version will also change all implied bits.
72 uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS
) {
73 SubtargetFeatures Features
;
74 FeatureBits
= Features
.ToggleFeature(FeatureBits
, FS
, ProcFeatures
);
80 MCSubtargetInfo::getSchedModelForCPU(StringRef CPU
) const {
81 assert(ProcSchedModels
&& "Processor machine model not available!");
83 unsigned NumProcs
= ProcDesc
.size();
85 for (size_t i
= 1; i
< NumProcs
; i
++) {
86 assert(strcmp(ProcSchedModels
[i
- 1].Key
, ProcSchedModels
[i
].Key
) < 0 &&
87 "Processor machine model table is not sorted");
92 const SubtargetInfoKV
*Found
=
93 std::lower_bound(ProcSchedModels
, ProcSchedModels
+NumProcs
, CPU
);
94 if (Found
== ProcSchedModels
+NumProcs
|| StringRef(Found
->Key
) != CPU
) {
96 << "' is not a recognized processor for this target"
97 << " (ignoring processor)\n";
98 return MCSchedModel::GetDefaultSchedModel();
100 assert(Found
->Value
&& "Missing processor SchedModel value");
101 return *(const MCSchedModel
*)Found
->Value
;
105 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU
) const {
106 const MCSchedModel SchedModel
= getSchedModelForCPU(CPU
);
107 return InstrItineraryData(SchedModel
, Stages
, OperandCycles
, ForwardingPaths
);
110 /// Initialize an InstrItineraryData instance.
111 void MCSubtargetInfo::initInstrItins(InstrItineraryData
&InstrItins
) const {
113 InstrItineraryData(CPUSchedModel
, Stages
, OperandCycles
, ForwardingPaths
);