src/llvm/lib/Target/ARM/ARMSubtarget.cpp

   1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "ARMSubtarget.h"
  15 #include "ARMFrameLowering.h"
  16 #include "ARMISelLowering.h"
  17 #include "ARMInstrInfo.h"
  18 #include "ARMMachineFunctionInfo.h"
  19 #include "ARMSelectionDAGInfo.h"
  20 #include "ARMSubtarget.h"
  21 #include "ARMTargetMachine.h"
  22 #include "Thumb1FrameLowering.h"
  23 #include "Thumb1InstrInfo.h"
  24 #include "Thumb2InstrInfo.h"
  25 #include "llvm/CodeGen/MachineRegisterInfo.h"
  26 #include "llvm/IR/Attributes.h"
  27 #include "llvm/IR/Function.h"
  28 #include "llvm/IR/GlobalValue.h"
  29 #include "llvm/Support/CommandLine.h"
  30 #include "llvm/Target/TargetInstrInfo.h"
  31 #include "llvm/Target/TargetOptions.h"
  32 #include "llvm/Target/TargetRegisterInfo.h"
  33
  34 using namespace llvm;
  35
  36 #define DEBUG_TYPE "arm-subtarget"
  37
  38 #define GET_SUBTARGETINFO_TARGET_DESC
  39 #define GET_SUBTARGETINFO_CTOR
  40 #include "ARMGenSubtargetInfo.inc"
  41
  42 static cl::opt<bool>
  43 ReserveR9("arm-reserve-r9", cl::Hidden,
  44           cl::desc("Reserve R9, making it unavailable as GPR"));
  45
  46 static cl::opt<bool>
  47 ArmUseMOVT("arm-use-movt", cl::init(true), cl::Hidden);
  48
  49 static cl::opt<bool>
  50 UseFusedMulOps("arm-use-mulops",
  51                cl::init(true), cl::Hidden);
  52
  53 namespace {
  54 enum AlignMode {
  55   DefaultAlign,
  56   StrictAlign,
  57   NoStrictAlign
  58 };
  59 }
  60
  61 static cl::opt<AlignMode>
  62 Align(cl::desc("Load/store alignment support"),
  63       cl::Hidden, cl::init(DefaultAlign),
  64       cl::values(
  65           clEnumValN(DefaultAlign,  "arm-default-align",
  66                      "Generate unaligned accesses only on hardware/OS "
  67                      "combinations that are known to support them"),
  68           clEnumValN(StrictAlign,   "arm-strict-align",
  69                      "Disallow all unaligned memory accesses"),
  70           clEnumValN(NoStrictAlign, "arm-no-strict-align",
  71                      "Allow unaligned memory accesses"),
  72           clEnumValEnd));
  73
  74 enum ITMode {
  75   DefaultIT,
  76   RestrictedIT,
  77   NoRestrictedIT
  78 };
  79
  80 static cl::opt<ITMode>
  81 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
  82    cl::ZeroOrMore,
  83    cl::values(clEnumValN(DefaultIT, "arm-default-it",
  84                          "Generate IT block based on arch"),
  85               clEnumValN(RestrictedIT, "arm-restrict-it",
  86                          "Disallow deprecated IT based on ARMv8"),
  87               clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
  88                          "Allow IT blocks based on ARMv7"),
  89               clEnumValEnd));
  90
  91 static std::string computeDataLayout(ARMSubtarget &ST) {
  92   std::string Ret = "";
  93
  94   if (ST.isLittle())
  95     // Little endian.
  96     Ret += "e";
  97   else
  98     // Big endian.
  99     Ret += "E";
 100
 101   Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
 102
 103   // Pointers are 32 bits and aligned to 32 bits.
 104   Ret += "-p:32:32";
 105
 106   // ABIs other than APCS have 64 bit integers with natural alignment.
 107   if (!ST.isAPCS_ABI())
 108     Ret += "-i64:64";
 109
 110   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
 111   // bits, others to 64 bits. We always try to align to 64 bits.
 112   if (ST.isAPCS_ABI())
 113     Ret += "-f64:32:64";
 114
 115   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
 116   // to 64. We always ty to give them natural alignment.
 117   if (ST.isAPCS_ABI())
 118     Ret += "-v64:32:64-v128:32:128";
 119   else
 120     Ret += "-v128:64:128";
 121
 122   // Try to align aggregates to 32 bits (the default is 64 bits, which has no
 123   // particular hardware support on 32-bit ARM).
 124   Ret += "-a:0:32";
 125
 126   // Integer registers are 32 bits.
 127   Ret += "-n32";
 128
 129   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
 130   // aligned everywhere else.
 131   if (ST.isTargetNaCl())
 132     Ret += "-S128";
 133   else if (ST.isAAPCS_ABI())
 134     Ret += "-S64";
 135   else
 136     Ret += "-S32";
 137
 138   return Ret;
 139 }
 140
 141 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
 142 /// so that we can use initializer lists for subtarget initialization.
 143 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
 144                                                             StringRef FS) {
 145   initializeEnvironment();
 146   initSubtargetFeatures(CPU, FS);
 147   return *this;
 148 }
 149
 150 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
 151                            const std::string &FS, const ARMBaseTargetMachine &TM,
 152                            bool IsLittle)
 153     : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
 154       ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
 155       TargetTriple(TT), Options(TM.Options), TM(TM),
 156       DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS))),
 157       TSInfo(DL),
 158       InstrInfo(isThumb1Only()
 159                     ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
 160                     : !isThumb()
 161                           ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
 162                           : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
 163       TLInfo(TM),
 164       FrameLowering(!isThumb1Only()
 165                         ? new ARMFrameLowering(*this)
 166                         : (ARMFrameLowering *)new Thumb1FrameLowering(*this)) {}
 167
 168 void ARMSubtarget::initializeEnvironment() {
 169   HasV4TOps = false;
 170   HasV5TOps = false;
 171   HasV5TEOps = false;
 172   HasV6Ops = false;
 173   HasV6MOps = false;
 174   HasV6T2Ops = false;
 175   HasV7Ops = false;
 176   HasV8Ops = false;
 177   HasVFPv2 = false;
 178   HasVFPv3 = false;
 179   HasVFPv4 = false;
 180   HasFPARMv8 = false;
 181   HasNEON = false;
 182   UseNEONForSinglePrecisionFP = false;
 183   UseMulOps = UseFusedMulOps;
 184   SlowFPVMLx = false;
 185   HasVMLxForwarding = false;
 186   SlowFPBrcc = false;
 187   InThumbMode = false;
 188   HasThumb2 = false;
 189   NoARM = false;
 190   IsR9Reserved = ReserveR9;
 191   UseMovt = false;
 192   SupportsTailCall = false;
 193   HasFP16 = false;
 194   HasD16 = false;
 195   HasHardwareDivide = false;
 196   HasHardwareDivideInARM = false;
 197   HasT2ExtractPack = false;
 198   HasDataBarrier = false;
 199   Pref32BitThumb = false;
 200   AvoidCPSRPartialUpdate = false;
 201   AvoidMOVsShifterOperand = false;
 202   HasRAS = false;
 203   HasMPExtension = false;
 204   HasVirtualization = false;
 205   FPOnlySP = false;
 206   HasPerfMon = false;
 207   HasTrustZone = false;
 208   HasCrypto = false;
 209   HasCRC = false;
 210   HasZeroCycleZeroing = false;
 211   AllowsUnalignedMem = false;
 212   Thumb2DSP = false;
 213   UseNaClTrap = false;
 214   UnsafeFPMath = false;
 215 }
 216
 217 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
 218   if (CPUString.empty()) {
 219     if (isTargetDarwin() && TargetTriple.getArchName().endswith("v7s"))
 220       // Default to the Swift CPU when targeting armv7s/thumbv7s.
 221       CPUString = "swift";
 222     else
 223       CPUString = "generic";
 224   }
 225
 226   // Insert the architecture feature derived from the target triple into the
 227   // feature string. This is important for setting features that are implied
 228   // based on the architecture version.
 229   std::string ArchFS =
 230       ARM_MC::ParseARMTriple(TargetTriple.getTriple(), CPUString);
 231   if (!FS.empty()) {
 232     if (!ArchFS.empty())
 233       ArchFS = ArchFS + "," + FS.str();
 234     else
 235       ArchFS = FS;
 236   }
 237   ParseSubtargetFeatures(CPUString, ArchFS);
 238
 239   // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
 240   // Assert this for now to make the change obvious.
 241   assert(hasV6T2Ops() || !hasThumb2());
 242
 243   // Keep a pointer to static instruction cost data for the specified CPU.
 244   SchedModel = getSchedModelForCPU(CPUString);
 245
 246   // Initialize scheduling itinerary for the specified CPU.
 247   InstrItins = getInstrItineraryForCPU(CPUString);
 248
 249   // FIXME: this is invalid for WindowsCE
 250   if (isTargetWindows())
 251     NoARM = true;
 252
 253   if (isAAPCS_ABI())
 254     stackAlignment = 8;
 255   if (isTargetNaCl())
 256     stackAlignment = 16;
 257
 258   UseMovt = hasV6T2Ops() && ArmUseMOVT;
 259
 260   if (isTargetMachO()) {
 261     IsR9Reserved = ReserveR9 || !HasV6Ops;
 262     SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0);
 263   } else {
 264     IsR9Reserved = ReserveR9;
 265     SupportsTailCall = !isThumb1Only();
 266   }
 267
 268   if (Align == DefaultAlign) {
 269     // Assume pre-ARMv6 doesn't support unaligned accesses.
 270     //
 271     // ARMv6 may or may not support unaligned accesses depending on the
 272     // SCTLR.U bit, which is architecture-specific. We assume ARMv6
 273     // Darwin and NetBSD targets support unaligned accesses, and others don't.
 274     //
 275     // ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
 276     // which raises an alignment fault on unaligned accesses. Linux
 277     // defaults this bit to 0 and handles it as a system-wide (not
 278     // per-process) setting. It is therefore safe to assume that ARMv7+
 279     // Linux targets support unaligned accesses. The same goes for NaCl.
 280     //
 281     // The above behavior is consistent with GCC.
 282     AllowsUnalignedMem =
 283       (hasV7Ops() && (isTargetLinux() || isTargetNaCl() ||
 284                       isTargetNetBSD())) ||
 285       (hasV6Ops() && (isTargetMachO() || isTargetNetBSD()));
 286   } else {
 287     AllowsUnalignedMem = !(Align == StrictAlign);
 288   }
 289
 290   // No v6M core supports unaligned memory access (v6M ARM ARM A3.2)
 291   if (isV6M())
 292     AllowsUnalignedMem = false;
 293
 294   switch (IT) {
 295   case DefaultIT:
 296     RestrictIT = hasV8Ops() ? true : false;
 297     break;
 298   case RestrictedIT:
 299     RestrictIT = true;
 300     break;
 301   case NoRestrictedIT:
 302     RestrictIT = false;
 303     break;
 304   }
 305
 306   // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
 307   uint64_t Bits = getFeatureBits();
 308   if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
 309       (Options.UnsafeFPMath || isTargetDarwin()))
 310     UseNEONForSinglePrecisionFP = true;
 311 }
 312
 313 bool ARMSubtarget::isAPCS_ABI() const {
 314   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
 315   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
 316 }
 317 bool ARMSubtarget::isAAPCS_ABI() const {
 318   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
 319   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS;
 320 }
 321
 322 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
 323 bool
 324 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
 325                                  Reloc::Model RelocM) const {
 326   if (RelocM == Reloc::Static)
 327     return false;
 328
 329   bool isDecl = GV->isDeclarationForLinker();
 330
 331   if (!isTargetMachO()) {
 332     // Extra load is needed for all externally visible.
 333     if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
 334       return false;
 335     return true;
 336   } else {
 337     if (RelocM == Reloc::PIC_) {
 338       // If this is a strong reference to a definition, it is definitely not
 339       // through a stub.
 340       if (!isDecl && !GV->isWeakForLinker())
 341         return false;
 342
 343       // Unless we have a symbol with hidden visibility, we have to go through a
 344       // normal $non_lazy_ptr stub because this symbol might be resolved late.
 345       if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
 346         return true;
 347
 348       // If symbol visibility is hidden, we have a stub for common symbol
 349       // references and external declarations.
 350       if (isDecl || GV->hasCommonLinkage())
 351         // Hidden $non_lazy_ptr reference.
 352         return true;
 353
 354       return false;
 355     } else {
 356       // If this is a strong reference to a definition, it is definitely not
 357       // through a stub.
 358       if (!isDecl && !GV->isWeakForLinker())
 359         return false;
 360
 361       // Unless we have a symbol with hidden visibility, we have to go through a
 362       // normal $non_lazy_ptr stub because this symbol might be resolved late.
 363       if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
 364         return true;
 365     }
 366   }
 367
 368   return false;
 369 }
 370
 371 unsigned ARMSubtarget::getMispredictionPenalty() const {
 372   return SchedModel.MispredictPenalty;
 373 }
 374
 375 bool ARMSubtarget::hasSinCos() const {
 376   return getTargetTriple().isiOS() && !getTargetTriple().isOSVersionLT(7, 0);
 377 }
 378
 379 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
 380 bool ARMSubtarget::enablePostMachineScheduler() const {
 381   return (!isThumb() || hasThumb2());
 382 }
 383
 384 bool ARMSubtarget::enableAtomicExpand() const {
 385   return hasAnyDataBarrier() && !isThumb1Only();
 386 }
 387
 388 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
 389   // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
 390   // immediates as it is inherently position independent, and may be out of
 391   // range otherwise.
 392   return UseMovt && (isTargetWindows() ||
 393                      !MF.getFunction()->getAttributes().hasAttribute(
 394                          AttributeSet::FunctionIndex, Attribute::MinSize));
 395 }