1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
18 #include "ARMFrameLowering.h"
19 #include "ARMISelLowering.h"
20 #include "ARMInstrInfo.h"
21 #include "ARMSelectionDAGInfo.h"
22 #include "ARMSubtarget.h"
23 #include "MCTargetDesc/ARMMCTargetDesc.h"
24 #include "Thumb1FrameLowering.h"
25 #include "Thumb1InstrInfo.h"
26 #include "Thumb2InstrInfo.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/MC/MCInstrItineraries.h"
30 #include "llvm/Target/TargetSubtargetInfo.h"
33 #define GET_SUBTARGETINFO_HEADER
34 #include "ARMGenSubtargetInfo.inc"
40 class ARMBaseTargetMachine
;
42 class ARMSubtarget
: public ARMGenSubtargetInfo
{
44 enum ARMProcFamilyEnum
{
45 Others
, CortexA5
, CortexA7
, CortexA8
, CortexA9
, CortexA12
, CortexA15
,
46 CortexA17
, CortexR5
, Swift
, CortexA53
, CortexA57
, Krait
,
48 enum ARMProcClassEnum
{
49 None
, AClass
, RClass
, MClass
52 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
53 ARMProcFamilyEnum ARMProcFamily
;
55 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
56 ARMProcClassEnum ARMProcClass
;
58 /// HasV4TOps, HasV5TOps, HasV5TEOps,
59 /// HasV6Ops, HasV6MOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
60 /// Specify whether target support specific ARM ISA variants.
70 /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
71 /// floating point ISAs are supported.
78 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
79 /// specified. Use the method useNEONForSinglePrecisionFP() to
80 /// determine if NEON should actually be used.
81 bool UseNEONForSinglePrecisionFP
;
83 /// UseMulOps - True if non-microcoded fused integer multiply-add and
84 /// multiply-subtract instructions should be used.
87 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
88 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
91 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
92 /// forwarding to allow mul + mla being issued back to back.
93 bool HasVMLxForwarding
;
95 /// SlowFPBrcc - True if floating point compare + branch is slow.
98 /// InThumbMode - True if compiling for Thumb, false for ARM.
101 /// HasThumb2 - True if Thumb2 instructions are supported.
104 /// NoARM - True if subtarget does not support ARM mode execution.
107 /// IsR9Reserved - True if R9 is a not available as general purpose register.
110 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
111 /// imms (including global addresses).
114 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
115 /// must be able to synthesize call stubs for interworking between ARM and
117 bool SupportsTailCall
;
119 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
123 /// HasD16 - True if subtarget is limited to 16 double precision
124 /// FP registers for VFPv3.
127 /// HasHardwareDivide - True if subtarget supports [su]div
128 bool HasHardwareDivide
;
130 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
131 bool HasHardwareDivideInARM
;
133 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
135 bool HasT2ExtractPack
;
137 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
141 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
142 /// over 16-bit ones.
145 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
146 /// that partially update CPSR and add false dependency on the previous
147 /// CPSR setting instruction.
148 bool AvoidCPSRPartialUpdate
;
150 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
151 /// movs with shifter operand (i.e. asr, lsl, lsr).
152 bool AvoidMOVsShifterOperand
;
154 /// HasRAS - Some processors perform return stack prediction. CodeGen should
155 /// avoid issue "normal" call instructions to callees which do not return.
158 /// HasMPExtension - True if the subtarget supports Multiprocessing
159 /// extension (ARMv7 only).
162 /// HasVirtualization - True if the subtarget supports the Virtualization
164 bool HasVirtualization
;
166 /// FPOnlySP - If true, the floating point unit only supports single
170 /// If true, the processor supports the Performance Monitor Extensions. These
171 /// include a generic cycle-counter as well as more fine-grained (often
172 /// implementation-specific) events.
175 /// HasTrustZone - if true, processor supports TrustZone security extensions
178 /// HasCrypto - if true, processor supports Cryptography extensions
181 /// HasCRC - if true, processor supports CRC instructions
184 /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
185 /// particularly effective at zeroing a VFP register.
186 bool HasZeroCycleZeroing
;
188 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
189 /// accesses for some types. For details, see
190 /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
191 bool AllowsUnalignedMem
;
193 /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
194 /// blocks to conform to ARMv8 rule.
197 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
198 /// and such) instructions in Thumb2 code.
201 /// NaCl TRAP instruction is generated instead of the regular TRAP.
204 /// Target machine allowed unsafe FP math (such as use of NEON fp)
207 /// stackAlignment - The minimum alignment known to hold of the stack frame on
208 /// entry to the function and which must be maintained by every function.
209 unsigned stackAlignment
;
211 /// CPUString - String name of used CPU.
212 std::string CPUString
;
214 /// IsLittle - The target is Little Endian
217 /// TargetTriple - What processor and OS we're targeting.
220 /// SchedModel - Processor specific instruction costs.
221 MCSchedModel SchedModel
;
223 /// Selected instruction itineraries (one entry per itinerary class.)
224 InstrItineraryData InstrItins
;
226 /// Options passed via command line that could influence the target
227 const TargetOptions
&Options
;
229 const ARMBaseTargetMachine
&TM
;
232 /// This constructor initializes the data members to match that
233 /// of the specified triple.
235 ARMSubtarget(const std::string
&TT
, const std::string
&CPU
,
236 const std::string
&FS
, const ARMBaseTargetMachine
&TM
, bool IsLittle
);
238 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
239 /// that still makes it profitable to inline the call.
240 unsigned getMaxInlineSizeThreshold() const {
243 /// ParseSubtargetFeatures - Parses features string setting specified
244 /// subtarget options. Definition of function is auto generated by tblgen.
245 void ParseSubtargetFeatures(StringRef CPU
, StringRef FS
);
247 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
248 /// so that we can use initializer lists for subtarget initialization.
249 ARMSubtarget
&initializeSubtargetDependencies(StringRef CPU
, StringRef FS
);
251 const DataLayout
*getDataLayout() const override
{ return &DL
; }
252 const ARMSelectionDAGInfo
*getSelectionDAGInfo() const override
{
255 const ARMBaseInstrInfo
*getInstrInfo() const override
{
256 return InstrInfo
.get();
258 const ARMTargetLowering
*getTargetLowering() const override
{
261 const ARMFrameLowering
*getFrameLowering() const override
{
262 return FrameLowering
.get();
264 const ARMBaseRegisterInfo
*getRegisterInfo() const override
{
265 return &InstrInfo
->getRegisterInfo();
270 ARMSelectionDAGInfo TSInfo
;
271 // Either Thumb1InstrInfo or Thumb2InstrInfo.
272 std::unique_ptr
<ARMBaseInstrInfo
> InstrInfo
;
273 ARMTargetLowering TLInfo
;
274 // Either Thumb1FrameLowering or ARMFrameLowering.
275 std::unique_ptr
<ARMFrameLowering
> FrameLowering
;
277 void initializeEnvironment();
278 void initSubtargetFeatures(StringRef CPU
, StringRef FS
);
280 void computeIssueWidth();
282 bool hasV4TOps() const { return HasV4TOps
; }
283 bool hasV5TOps() const { return HasV5TOps
; }
284 bool hasV5TEOps() const { return HasV5TEOps
; }
285 bool hasV6Ops() const { return HasV6Ops
; }
286 bool hasV6MOps() const { return HasV6MOps
; }
287 bool hasV6T2Ops() const { return HasV6T2Ops
; }
288 bool hasV7Ops() const { return HasV7Ops
; }
289 bool hasV8Ops() const { return HasV8Ops
; }
291 bool isCortexA5() const { return ARMProcFamily
== CortexA5
; }
292 bool isCortexA7() const { return ARMProcFamily
== CortexA7
; }
293 bool isCortexA8() const { return ARMProcFamily
== CortexA8
; }
294 bool isCortexA9() const { return ARMProcFamily
== CortexA9
; }
295 bool isCortexA15() const { return ARMProcFamily
== CortexA15
; }
296 bool isSwift() const { return ARMProcFamily
== Swift
; }
297 bool isCortexM3() const { return CPUString
== "cortex-m3"; }
298 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
299 bool isCortexR5() const { return ARMProcFamily
== CortexR5
; }
300 bool isKrait() const { return ARMProcFamily
== Krait
; }
302 bool hasARMOps() const { return !NoARM
; }
304 bool hasVFP2() const { return HasVFPv2
; }
305 bool hasVFP3() const { return HasVFPv3
; }
306 bool hasVFP4() const { return HasVFPv4
; }
307 bool hasFPARMv8() const { return HasFPARMv8
; }
308 bool hasNEON() const { return HasNEON
; }
309 bool hasCrypto() const { return HasCrypto
; }
310 bool hasCRC() const { return HasCRC
; }
311 bool hasVirtualization() const { return HasVirtualization
; }
312 bool useNEONForSinglePrecisionFP() const {
313 return hasNEON() && UseNEONForSinglePrecisionFP
; }
315 bool hasDivide() const { return HasHardwareDivide
; }
316 bool hasDivideInARMMode() const { return HasHardwareDivideInARM
; }
317 bool hasT2ExtractPack() const { return HasT2ExtractPack
; }
318 bool hasDataBarrier() const { return HasDataBarrier
; }
319 bool hasAnyDataBarrier() const {
320 return HasDataBarrier
|| (hasV6Ops() && !isThumb());
322 bool useMulOps() const { return UseMulOps
; }
323 bool useFPVMLx() const { return !SlowFPVMLx
; }
324 bool hasVMLxForwarding() const { return HasVMLxForwarding
; }
325 bool isFPBrccSlow() const { return SlowFPBrcc
; }
326 bool isFPOnlySP() const { return FPOnlySP
; }
327 bool hasPerfMon() const { return HasPerfMon
; }
328 bool hasTrustZone() const { return HasTrustZone
; }
329 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing
; }
330 bool prefers32BitThumb() const { return Pref32BitThumb
; }
331 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate
; }
332 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand
; }
333 bool hasRAS() const { return HasRAS
; }
334 bool hasMPExtension() const { return HasMPExtension
; }
335 bool hasThumb2DSP() const { return Thumb2DSP
; }
336 bool useNaClTrap() const { return UseNaClTrap
; }
338 bool hasFP16() const { return HasFP16
; }
339 bool hasD16() const { return HasD16
; }
341 const Triple
&getTargetTriple() const { return TargetTriple
; }
343 bool isTargetDarwin() const { return TargetTriple
.isOSDarwin(); }
344 bool isTargetIOS() const { return TargetTriple
.isiOS(); }
345 bool isTargetLinux() const { return TargetTriple
.isOSLinux(); }
346 bool isTargetNaCl() const { return TargetTriple
.isOSNaCl(); }
347 bool isTargetNetBSD() const { return TargetTriple
.isOSNetBSD(); }
348 bool isTargetWindows() const { return TargetTriple
.isOSWindows(); }
350 bool isTargetCOFF() const { return TargetTriple
.isOSBinFormatCOFF(); }
351 bool isTargetELF() const { return TargetTriple
.isOSBinFormatELF(); }
352 bool isTargetMachO() const { return TargetTriple
.isOSBinFormatMachO(); }
354 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
355 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
356 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
357 // even for GNUEABI, so we can make a distinction here and still conform to
358 // the EABI on GNU (and Android) mode. This requires change in Clang, too.
359 // FIXME: The Darwin exception is temporary, while we move users to
360 // "*-*-*-macho" triples as quickly as possible.
361 bool isTargetAEABI() const {
362 return (TargetTriple
.getEnvironment() == Triple::EABI
||
363 TargetTriple
.getEnvironment() == Triple::EABIHF
) &&
364 !isTargetDarwin() && !isTargetWindows();
367 // ARM Targets that support EHABI exception handling standard
368 // Darwin uses SjLj. Other targets might need more checks.
369 bool isTargetEHABICompatible() const {
370 return (TargetTriple
.getEnvironment() == Triple::EABI
||
371 TargetTriple
.getEnvironment() == Triple::GNUEABI
||
372 TargetTriple
.getEnvironment() == Triple::EABIHF
||
373 TargetTriple
.getEnvironment() == Triple::GNUEABIHF
||
374 TargetTriple
.getEnvironment() == Triple::Android
) &&
375 !isTargetDarwin() && !isTargetWindows();
378 bool isTargetHardFloat() const {
379 // FIXME: this is invalid for WindowsCE
380 return TargetTriple
.getEnvironment() == Triple::GNUEABIHF
||
381 TargetTriple
.getEnvironment() == Triple::EABIHF
||
384 bool isTargetAndroid() const {
385 return TargetTriple
.getEnvironment() == Triple::Android
;
388 bool isAPCS_ABI() const;
389 bool isAAPCS_ABI() const;
391 bool isThumb() const { return InThumbMode
; }
392 bool isThumb1Only() const { return InThumbMode
&& !HasThumb2
; }
393 bool isThumb2() const { return InThumbMode
&& HasThumb2
; }
394 bool hasThumb2() const { return HasThumb2
; }
395 bool isMClass() const { return ARMProcClass
== MClass
; }
396 bool isRClass() const { return ARMProcClass
== RClass
; }
397 bool isAClass() const { return ARMProcClass
== AClass
; }
400 return isThumb1Only() && isMClass();
403 bool isR9Reserved() const { return IsR9Reserved
; }
405 bool useMovt(const MachineFunction
&MF
) const;
407 bool supportsTailCall() const { return SupportsTailCall
; }
409 bool allowsUnalignedMem() const { return AllowsUnalignedMem
; }
411 bool restrictIT() const { return RestrictIT
; }
413 const std::string
& getCPUString() const { return CPUString
; }
415 bool isLittle() const { return IsLittle
; }
417 unsigned getMispredictionPenalty() const;
419 /// This function returns true if the target has sincos() routine in its
420 /// compiler runtime or math libraries.
421 bool hasSinCos() const;
423 /// True for some subtargets at > -O0.
424 bool enablePostMachineScheduler() const override
;
426 // enableAtomicExpand- True if we need to expand our atomics.
427 bool enableAtomicExpand() const override
;
429 /// getInstrItins - Return the instruction itineraries based on subtarget
431 const InstrItineraryData
*getInstrItineraryData() const override
{
435 /// getStackAlignment - Returns the minimum alignment known to hold of the
436 /// stack frame on entry to the function and which must be maintained by every
437 /// function for this subtarget.
438 unsigned getStackAlignment() const { return stackAlignment
; }
440 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
442 bool GVIsIndirectSymbol(const GlobalValue
*GV
, Reloc::Model RelocM
) const;
445 } // End llvm namespace
447 #endif // ARMSUBTARGET_H