src/llvm/lib/Target/Hexagon/HexagonInstrFormats.td

   1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 //===----------------------------------------------------------------------===//
  11 //                         Hexagon Instruction Flags +
  12 //
  13 //                    *** Must match HexagonBaseInfo.h ***
  14 //===----------------------------------------------------------------------===//
  15
  16 class IType<bits<5> t> {
  17   bits<5> Value = t;
  18 }
  19 def TypePSEUDO : IType<0>;
  20 def TypeALU32  : IType<1>;
  21 def TypeCR     : IType<2>;
  22 def TypeJR     : IType<3>;
  23 def TypeJ      : IType<4>;
  24 def TypeLD     : IType<5>;
  25 def TypeST     : IType<6>;
  26 def TypeSYSTEM : IType<7>;
  27 def TypeXTYPE  : IType<8>;
  28 def TypeENDLOOP: IType<31>;
  29
  30 // Maintain list of valid subtargets for each instruction.
  31 class SubTarget<bits<4> value> {
  32   bits<4> Value = value;
  33 }
  34
  35 def HasV2SubT     : SubTarget<0xf>;
  36 def HasV2SubTOnly : SubTarget<0x1>;
  37 def NoV2SubT      : SubTarget<0x0>;
  38 def HasV3SubT     : SubTarget<0xe>;
  39 def HasV3SubTOnly : SubTarget<0x2>;
  40 def NoV3SubT      : SubTarget<0x1>;
  41 def HasV4SubT     : SubTarget<0xc>;
  42 def NoV4SubT      : SubTarget<0x3>;
  43 def HasV5SubT     : SubTarget<0x8>;
  44 def NoV5SubT      : SubTarget<0x7>;
  45
  46 // Addressing modes for load/store instructions
  47 class AddrModeType<bits<3> value> {
  48   bits<3> Value = value;
  49 }
  50
  51 def NoAddrMode     : AddrModeType<0>;  // No addressing mode
  52 def Absolute       : AddrModeType<1>;  // Absolute addressing mode
  53 def AbsoluteSet    : AddrModeType<2>;  // Absolute set addressing mode
  54 def BaseImmOffset  : AddrModeType<3>;  // Indirect with offset
  55 def BaseLongOffset : AddrModeType<4>;  // Indirect with long offset
  56 def BaseRegOffset  : AddrModeType<5>;  // Indirect with register offset
  57 def PostInc        : AddrModeType<6>;  // Post increment addressing mode
  58
  59 class MemAccessSize<bits<3> value> {
  60   bits<3> Value = value;
  61 }
  62
  63 def NoMemAccess      : MemAccessSize<0>;// Not a memory acces instruction.
  64 def ByteAccess       : MemAccessSize<1>;// Byte access instruction (memb).
  65 def HalfWordAccess   : MemAccessSize<2>;// Half word access instruction (memh).
  66 def WordAccess       : MemAccessSize<3>;// Word access instruction (memw).
  67 def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
  68
  69
  70 //===----------------------------------------------------------------------===//
  71 //                         Instruction Class Declaration +
  72 //===----------------------------------------------------------------------===//
  73
  74 class OpcodeHexagon {
  75   field bits<32> Inst = ?; // Default to an invalid insn.
  76   bits<4> IClass = 0; // ICLASS
  77   bits<2> IParse = 0; // Parse bits.
  78
  79   let Inst{31-28} = IClass;
  80   let Inst{15-14} = IParse;
  81
  82   bits<1> zero = 0;
  83 }
  84
  85 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
  86                   string cstr, InstrItinClass itin, IType type>
  87   : Instruction, OpcodeHexagon {
  88   let Namespace = "Hexagon";
  89
  90   dag OutOperandList = outs;
  91   dag InOperandList = ins;
  92   let AsmString = asmstr;
  93   let Pattern = pattern;
  94   let Constraints = cstr;
  95   let Itinerary = itin;
  96   let Size = 4;
  97
  98   // SoftFail is a field the disassembler can use to provide a way for
  99   // instructions to not match without killing the whole decode process. It is
 100   // mainly used for ARM, but Tablegen expects this field to exist or it fails
 101   // to build the decode table.
 102   field bits<32> SoftFail = 0;
 103
 104   // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
 105
 106   // Instruction type according to the ISA.
 107   IType Type = type;
 108   let TSFlags{4-0} = Type.Value;
 109
 110   // Solo instructions, i.e., those that cannot be in a packet with others.
 111   bits<1> isSolo = 0;
 112   let TSFlags{5} = isSolo;
 113   // Packed only with A or X-type instructions.
 114   bits<1> isSoloAX = 0;
 115   let TSFlags{6} = isSoloAX;
 116   // Only A-type instruction in first slot or nothing.
 117   bits<1> isSoloAin1 = 0;
 118   let TSFlags{7} = isSoloAin1;
 119
 120   // Predicated instructions.
 121   bits<1> isPredicated = 0;
 122   let TSFlags{8} = isPredicated;
 123   bits<1> isPredicatedFalse = 0;
 124   let TSFlags{9} = isPredicatedFalse;
 125   bits<1> isPredicatedNew = 0;
 126   let TSFlags{10} = isPredicatedNew;
 127   bits<1> isPredicateLate = 0;
 128   let TSFlags{11} = isPredicateLate; // Late predicate producer insn.
 129
 130   // New-value insn helper fields.
 131   bits<1> isNewValue = 0;
 132   let TSFlags{12} = isNewValue; // New-value consumer insn.
 133   bits<1> hasNewValue = 0;
 134   let TSFlags{13} = hasNewValue; // New-value producer insn.
 135   bits<3> opNewValue = 0;
 136   let TSFlags{16-14} = opNewValue; // New-value produced operand.
 137   bits<1> isNVStorable = 0;
 138   let TSFlags{17} = isNVStorable; // Store that can become new-value store.
 139   bits<1> isNVStore = 0;
 140   let TSFlags{18} = isNVStore; // New-value store insn.
 141   bits<1> isCVLoadable = 0;
 142   let TSFlags{19} = isCVLoadable; // Load that can become cur-value load.
 143   bits<1> isCVLoad = 0;
 144   let TSFlags{20} = isCVLoad; // Cur-value load insn.
 145
 146   // Immediate extender helper fields.
 147   bits<1> isExtendable = 0;
 148   let TSFlags{21} = isExtendable; // Insn may be extended.
 149   bits<1> isExtended = 0;
 150   let TSFlags{22} = isExtended; // Insn must be extended.
 151   bits<3> opExtendable = 0;
 152   let TSFlags{25-23} = opExtendable; // Which operand may be extended.
 153   bits<1> isExtentSigned = 0;
 154   let TSFlags{26} = isExtentSigned; // Signed or unsigned range.
 155   bits<5> opExtentBits = 0;
 156   let TSFlags{31-27} = opExtentBits; //Number of bits of range before extending.
 157   bits<2> opExtentAlign = 0;
 158   let TSFlags{33-32} = opExtentAlign; // Alignment exponent before extending.
 159
 160   // If an instruction is valid on a subtarget (v2-v5), set the corresponding
 161   // bit from validSubTargets. v2 is the least significant bit.
 162   // By default, instruction is valid on all subtargets.
 163   SubTarget validSubTargets = HasV2SubT;
 164   let TSFlags{37-34} = validSubTargets.Value;
 165
 166   // Addressing mode for load/store instructions.
 167   AddrModeType addrMode = NoAddrMode;
 168   let TSFlags{42-40} = addrMode.Value;
 169
 170   // Memory access size for mem access instructions (load/store)
 171   MemAccessSize accessSize = NoMemAccess;
 172   let TSFlags{45-43} = accessSize.Value;
 173
 174   bits<1> isTaken = 0;
 175   let TSFlags {47} = isTaken; // Branch prediction.
 176
 177   bits<1> isFP = 0;
 178   let TSFlags {48} = isFP; // Floating-point.
 179
 180   // Fields used for relation models.
 181   string BaseOpcode = "";
 182   string CextOpcode = "";
 183   string PredSense = "";
 184   string PNewValue = "";
 185   string NValueST  = "";    // Set to "true" for new-value stores.
 186   string InputType = "";    // Input is "imm" or "reg" type.
 187   string isMEMri = "false"; // Set to "true" for load/store with MEMri operand.
 188   string isFloat = "false"; // Set to "true" for the floating-point load/store.
 189   string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions
 190
 191   let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
 192                                     "");
 193   let PNewValue = !if(isPredicatedNew, "new", "");
 194   let NValueST = !if(isNVStore, "true", "false");
 195   let isCodeGenOnly = 1;
 196
 197   // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
 198 }
 199
 200 //===----------------------------------------------------------------------===//
 201 //                         Instruction Classes Definitions +
 202 //===----------------------------------------------------------------------===//
 203
 204 // LD Instruction Class in V2/V3/V4.
 205 // Definition of the instruction class NOT CHANGED.
 206 let mayLoad = 1 in
 207 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 208              string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
 209   : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>;
 210
 211 let mayLoad = 1 in
 212 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 213               string cstr = "">
 214   : LDInst<outs, ins, asmstr, pattern, cstr>;
 215
 216 class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 217                   string cstr = "">
 218   : LDInst<outs, ins, asmstr, pattern, cstr>;
 219
 220 // LD Instruction Class in V2/V3/V4.
 221 // Definition of the instruction class NOT CHANGED.
 222 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 223                  string cstr = "">
 224   : LDInst<outs, ins, asmstr, pattern, cstr>;
 225
 226 let mayLoad = 1 in
 227 class LD0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 228               string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0>
 229   : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>;
 230
 231 // ST Instruction Class in V2/V3 can take SLOT0 only.
 232 // ST Instruction Class in V4    can take SLOT0 & SLOT1.
 233 // Definition of the instruction class CHANGED from V2/V3 to V4.
 234 let mayStore = 1 in
 235 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 236              string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
 237   : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>;
 238
 239 class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 240               string cstr = "">
 241   : STInst<outs, ins, asmstr, pattern, cstr>;
 242
 243 let mayStore = 1 in
 244 class ST0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 245               string cstr = "", InstrItinClass itin = ST_tc_ld_SLOT0>
 246   : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>;
 247
 248 // ST Instruction Class in V2/V3 can take SLOT0 only.
 249 // ST Instruction Class in V4    can take SLOT0 & SLOT1.
 250 // Definition of the instruction class CHANGED from V2/V3 to V4.
 251 class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 252                  string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
 253   : STInst<outs, ins, asmstr, pattern, cstr, itin>;
 254
 255 // SYSTEM Instruction Class in V4 can take SLOT0 only
 256 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
 257 class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 258               string cstr = "",  InstrItinClass itin = ST_tc_3stall_SLOT0>
 259   : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeSYSTEM>;
 260
 261 // ALU32 Instruction Class in V2/V3/V4.
 262 // Definition of the instruction class NOT CHANGED.
 263 class ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 264                 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
 265  : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32>;
 266
 267 // ALU64 Instruction Class in V2/V3.
 268 // XTYPE Instruction Class in V4.
 269 // Definition of the instruction class NOT CHANGED.
 270 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
 271 class ALU64Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 272                 string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
 273    : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
 274
 275 class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 276                 string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
 277   : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
 278
 279
 280 // M Instruction Class in V2/V3.
 281 // XTYPE Instruction Class in V4.
 282 // Definition of the instruction class NOT CHANGED.
 283 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
 284 class MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 285             string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23>
 286   : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
 287
 288 // M Instruction Class in V2/V3.
 289 // XTYPE Instruction Class in V4.
 290 // Definition of the instruction class NOT CHANGED.
 291 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
 292 class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 293                 string cstr = "", InstrItinClass itin = M_tc_2_SLOT23>
 294     : MInst<outs, ins, asmstr, pattern, cstr, itin>;
 295
 296 // S Instruction Class in V2/V3.
 297 // XTYPE Instruction Class in V4.
 298 // Definition of the instruction class NOT CHANGED.
 299 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
 300 class SInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 301             string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23>
 302   : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
 303
 304 // S Instruction Class in V2/V3.
 305 // XTYPE Instruction Class in V4.
 306 // Definition of the instruction class NOT CHANGED.
 307 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
 308 class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 309                 string cstr = "", InstrItinClass itin = S_3op_tc_1_SLOT23>
 310   : SInst<outs, ins, asmstr, pattern, cstr, itin>;
 311
 312 // J Instruction Class in V2/V3/V4.
 313 // Definition of the instruction class NOT CHANGED.
 314 class JInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 315             string cstr = "", InstrItinClass itin = J_tc_2early_SLOT23>
 316   : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>;
 317
 318 // JR Instruction Class in V2/V3/V4.
 319 // Definition of the instruction class NOT CHANGED.
 320 class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 321              string cstr = "", InstrItinClass itin = J_tc_2early_SLOT2>
 322   : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJR>;
 323
 324 // CR Instruction Class in V2/V3/V4.
 325 // Definition of the instruction class NOT CHANGED.
 326 class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 327              string cstr = "", InstrItinClass itin = CR_tc_2early_SLOT3>
 328   : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCR>;
 329
 330 let isCodeGenOnly = 1, isPseudo = 1 in
 331 class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 332               string cstr = "", InstrItinClass itin = J_tc_2early_SLOT0123>
 333   : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeENDLOOP>;
 334
 335 let isCodeGenOnly = 1, isPseudo = 1 in
 336 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 337              string cstr = "">
 338   : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDO, TypePSEUDO>;
 339
 340 let isCodeGenOnly = 1, isPseudo = 1 in
 341 class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 342               string cstr="">
 343   : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>;
 344
 345 //===----------------------------------------------------------------------===//
 346 //                         Instruction Classes Definitions -
 347 //===----------------------------------------------------------------------===//
 348
 349
 350 //
 351 // ALU32 patterns
 352 //.
 353 class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 354                string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
 355    : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
 356
 357 class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 358                string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
 359    : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
 360
 361 class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 362                string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
 363    : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
 364
 365 class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 366                string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
 367    : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
 368
 369
 370 //
 371 // ALU64 patterns.
 372 //
 373 class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 374                string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
 375    : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
 376
 377 class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 378                string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
 379    : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
 380
 381 // Post increment ST Instruction.
 382 class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 383                string cstr = "">
 384   : STInst<outs, ins, asmstr, pattern, cstr>;
 385
 386 let mayStore = 1 in
 387 class STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 388                 string cstr = "">
 389   : STInst<outs, ins, asmstr, pattern, cstr>;
 390
 391 // Post increment LD Instruction.
 392 class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 393                string cstr = "">
 394   : LDInst<outs, ins, asmstr, pattern, cstr>;
 395
 396 let mayLoad = 1 in
 397 class LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
 398                 string cstr = "">
 399   : LDInst<outs, ins, asmstr, pattern, cstr>;
 400
 401 //===----------------------------------------------------------------------===//
 402 // V4 Instruction Format Definitions +
 403 //===----------------------------------------------------------------------===//
 404
 405 include "HexagonInstrFormatsV4.td"
 406
 407 //===----------------------------------------------------------------------===//
 408 // V4 Instruction Format Definitions +
 409 //===----------------------------------------------------------------------===//