src/llvm/lib/Target/Hexagon/HexagonInstrFormatsV4.td

   1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the Hexagon V4 instruction classes in TableGen format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //----------------------------------------------------------------------------//
  15 //                         Hexagon Instruction Flags
  16 //
  17 //                        *** Must match BaseInfo.h ***
  18 //----------------------------------------------------------------------------//
  19
  20 def TypeMEMOP  : IType<9>;
  21 def TypeNV     : IType<10>;
  22 def TypeCOMPOUND : IType<12>;
  23 def TypePREFIX : IType<30>;
  24
  25 //----------------------------------------------------------------------------//
  26 //                         Instruction Classes Definitions
  27 //----------------------------------------------------------------------------//
  28
  29 //
  30 // NV type instructions.
  31 //
  32 class NVInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
  33              string cstr = "", InstrItinClass itin = NCJ_tc_3or4stall_SLOT0>
  34   : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeNV>;
  35
  36 class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
  37                 string cstr = "", InstrItinClass itin = NCJ_tc_3or4stall_SLOT0>
  38   : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
  39
  40 // Definition of Post increment new value store.
  41 class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
  42                string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0>
  43   : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
  44
  45 // Post increment ST Instruction.
  46 let mayStore = 1 in
  47 class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
  48                string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0>
  49   : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
  50
  51 // New-value conditional branch.
  52 class NCJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
  53               string cstr = "">
  54   : NVInst<outs, ins, asmstr, pattern, cstr>;
  55
  56 let mayLoad = 1, mayStore = 1 in
  57 class MEMInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
  58               string cstr = "", InstrItinClass itin = V4LDST_tc_st_SLOT0>
  59   : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeMEMOP>;
  60
  61 class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
  62                  string cstr = "", InstrItinClass itin = V4LDST_tc_st_SLOT0>
  63   : MEMInst<outs, ins, asmstr, pattern, cstr, itin>;
  64
  65 let isCodeGenOnly = 1 in
  66 class EXTENDERInst<dag outs, dag ins, string asmstr, list<dag> pattern = []>
  67   : InstHexagon<outs, ins, asmstr, pattern, "", EXTENDER_tc_1_SLOT0123,
  68                 TypePREFIX>;
  69
  70 class CJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
  71               string cstr = "">
  72   : InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND, TypeCOMPOUND>;