1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/raw_ostream.h"
32 #define DEBUG_TYPE "hexagon-instrinfo"
34 #define GET_INSTRINFO_CTOR_DTOR
35 #define GET_INSTRMAP_INFO
36 #include "HexagonGenInstrInfo.inc"
37 #include "HexagonGenDFAPacketizer.inc"
40 /// Constants for Hexagon instructions.
42 const int Hexagon_MEMW_OFFSET_MAX
= 4095;
43 const int Hexagon_MEMW_OFFSET_MIN
= -4096;
44 const int Hexagon_MEMD_OFFSET_MAX
= 8191;
45 const int Hexagon_MEMD_OFFSET_MIN
= -8192;
46 const int Hexagon_MEMH_OFFSET_MAX
= 2047;
47 const int Hexagon_MEMH_OFFSET_MIN
= -2048;
48 const int Hexagon_MEMB_OFFSET_MAX
= 1023;
49 const int Hexagon_MEMB_OFFSET_MIN
= -1024;
50 const int Hexagon_ADDI_OFFSET_MAX
= 32767;
51 const int Hexagon_ADDI_OFFSET_MIN
= -32768;
52 const int Hexagon_MEMD_AUTOINC_MAX
= 56;
53 const int Hexagon_MEMD_AUTOINC_MIN
= -64;
54 const int Hexagon_MEMW_AUTOINC_MAX
= 28;
55 const int Hexagon_MEMW_AUTOINC_MIN
= -32;
56 const int Hexagon_MEMH_AUTOINC_MAX
= 14;
57 const int Hexagon_MEMH_AUTOINC_MIN
= -16;
58 const int Hexagon_MEMB_AUTOINC_MAX
= 7;
59 const int Hexagon_MEMB_AUTOINC_MIN
= -8;
61 // Pin the vtable to this file.
62 void HexagonInstrInfo::anchor() {}
64 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget
&ST
)
65 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN
, Hexagon::ADJCALLSTACKUP
),
66 RI(ST
), Subtarget(ST
) {
70 /// isLoadFromStackSlot - If the specified machine instruction is a direct
71 /// load from a stack slot, return the virtual or physical register number of
72 /// the destination along with the FrameIndex of the loaded stack slot. If
73 /// not, return 0. This predicate must return 0 if the instruction has
74 /// any side effects other than loading from the stack slot.
75 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr
*MI
,
76 int &FrameIndex
) const {
79 switch (MI
->getOpcode()) {
81 case Hexagon::L2_loadri_io
:
82 case Hexagon::L2_loadrd_io
:
83 case Hexagon::L2_loadrh_io
:
84 case Hexagon::L2_loadrb_io
:
85 case Hexagon::L2_loadrub_io
:
86 if (MI
->getOperand(2).isFI() &&
87 MI
->getOperand(1).isImm() && (MI
->getOperand(1).getImm() == 0)) {
88 FrameIndex
= MI
->getOperand(2).getIndex();
89 return MI
->getOperand(0).getReg();
97 /// isStoreToStackSlot - If the specified machine instruction is a direct
98 /// store to a stack slot, return the virtual or physical register number of
99 /// the source reg along with the FrameIndex of the loaded stack slot. If
100 /// not, return 0. This predicate must return 0 if the instruction has
101 /// any side effects other than storing to the stack slot.
102 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr
*MI
,
103 int &FrameIndex
) const {
104 switch (MI
->getOpcode()) {
106 case Hexagon::S2_storeri_io
:
107 case Hexagon::S2_storerd_io
:
108 case Hexagon::S2_storerh_io
:
109 case Hexagon::S2_storerb_io
:
110 if (MI
->getOperand(2).isFI() &&
111 MI
->getOperand(1).isImm() && (MI
->getOperand(1).getImm() == 0)) {
112 FrameIndex
= MI
->getOperand(0).getIndex();
113 return MI
->getOperand(2).getReg();
122 HexagonInstrInfo::InsertBranch(MachineBasicBlock
&MBB
,MachineBasicBlock
*TBB
,
123 MachineBasicBlock
*FBB
,
124 const SmallVectorImpl
<MachineOperand
> &Cond
,
127 int BOpc
= Hexagon::J2_jump
;
128 int BccOpc
= Hexagon::J2_jumpt
;
130 assert(TBB
&& "InsertBranch must not be told to insert a fallthrough");
133 // Check if ReverseBranchCondition has asked to reverse this branch
134 // If we want to reverse the branch an odd number of times, we want
136 if (!Cond
.empty() && Cond
[0].isImm() && Cond
[0].getImm() == 0) {
137 BccOpc
= Hexagon::J2_jumpf
;
143 // Due to a bug in TailMerging/CFG Optimization, we need to add a
144 // special case handling of a predicated jump followed by an
145 // unconditional jump. If not, Tail Merging and CFG Optimization go
146 // into an infinite loop.
147 MachineBasicBlock
*NewTBB
, *NewFBB
;
148 SmallVector
<MachineOperand
, 4> Cond
;
149 MachineInstr
*Term
= MBB
.getFirstTerminator();
150 if (isPredicated(Term
) && !AnalyzeBranch(MBB
, NewTBB
, NewFBB
, Cond
,
152 MachineBasicBlock
*NextBB
=
153 std::next(MachineFunction::iterator(&MBB
));
154 if (NewTBB
== NextBB
) {
155 ReverseBranchCondition(Cond
);
157 return InsertBranch(MBB
, TBB
, nullptr, Cond
, DL
);
160 BuildMI(&MBB
, DL
, get(BOpc
)).addMBB(TBB
);
163 get(BccOpc
)).addReg(Cond
[regPos
].getReg()).addMBB(TBB
);
168 BuildMI(&MBB
, DL
, get(BccOpc
)).addReg(Cond
[regPos
].getReg()).addMBB(TBB
);
169 BuildMI(&MBB
, DL
, get(BOpc
)).addMBB(FBB
);
175 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock
&MBB
,
176 MachineBasicBlock
*&TBB
,
177 MachineBasicBlock
*&FBB
,
178 SmallVectorImpl
<MachineOperand
> &Cond
,
179 bool AllowModify
) const {
183 // If the block has no terminators, it just falls into the block after it.
184 MachineBasicBlock::instr_iterator I
= MBB
.instr_end();
185 if (I
== MBB
.instr_begin())
188 // A basic block may looks like this:
198 // It has two succs but does not have a terminator
199 // Don't know how to handle it.
204 } while (I
!= MBB
.instr_begin());
209 while (I
->isDebugValue()) {
210 if (I
== MBB
.instr_begin())
215 // Delete the JMP if it's equivalent to a fall-through.
216 if (AllowModify
&& I
->getOpcode() == Hexagon::J2_jump
&&
217 MBB
.isLayoutSuccessor(I
->getOperand(0).getMBB())) {
218 DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
219 I
->eraseFromParent();
221 if (I
== MBB
.instr_begin())
225 if (!isUnpredicatedTerminator(I
))
228 // Get the last instruction in the block.
229 MachineInstr
*LastInst
= I
;
230 MachineInstr
*SecondLastInst
= nullptr;
231 // Find one more terminator if present.
233 if (&*I
!= LastInst
&& !I
->isBundle() && isUnpredicatedTerminator(I
)) {
237 // This is a third branch.
240 if (I
== MBB
.instr_begin())
245 int LastOpcode
= LastInst
->getOpcode();
247 bool LastOpcodeHasJMP_c
= PredOpcodeHasJMP_c(LastOpcode
);
248 bool LastOpcodeHasNot
= PredOpcodeHasNot(LastOpcode
);
250 // If there is only one terminator instruction, process it.
251 if (LastInst
&& !SecondLastInst
) {
252 if (LastOpcode
== Hexagon::J2_jump
) {
253 TBB
= LastInst
->getOperand(0).getMBB();
256 if (LastOpcode
== Hexagon::ENDLOOP0
) {
257 TBB
= LastInst
->getOperand(0).getMBB();
258 Cond
.push_back(LastInst
->getOperand(0));
261 if (LastOpcodeHasJMP_c
) {
262 TBB
= LastInst
->getOperand(1).getMBB();
263 if (LastOpcodeHasNot
) {
264 Cond
.push_back(MachineOperand::CreateImm(0));
266 Cond
.push_back(LastInst
->getOperand(0));
269 // Otherwise, don't know what this is.
273 int SecLastOpcode
= SecondLastInst
->getOpcode();
275 bool SecLastOpcodeHasJMP_c
= PredOpcodeHasJMP_c(SecLastOpcode
);
276 bool SecLastOpcodeHasNot
= PredOpcodeHasNot(SecLastOpcode
);
277 if (SecLastOpcodeHasJMP_c
&& (LastOpcode
== Hexagon::J2_jump
)) {
278 TBB
= SecondLastInst
->getOperand(1).getMBB();
279 if (SecLastOpcodeHasNot
)
280 Cond
.push_back(MachineOperand::CreateImm(0));
281 Cond
.push_back(SecondLastInst
->getOperand(0));
282 FBB
= LastInst
->getOperand(0).getMBB();
286 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
287 // executed, so remove it.
288 if (SecLastOpcode
== Hexagon::J2_jump
&& LastOpcode
== Hexagon::J2_jump
) {
289 TBB
= SecondLastInst
->getOperand(0).getMBB();
292 I
->eraseFromParent();
296 // If the block ends with an ENDLOOP, and JMP, handle it.
297 if (SecLastOpcode
== Hexagon::ENDLOOP0
&&
298 LastOpcode
== Hexagon::J2_jump
) {
299 TBB
= SecondLastInst
->getOperand(0).getMBB();
300 Cond
.push_back(SecondLastInst
->getOperand(0));
301 FBB
= LastInst
->getOperand(0).getMBB();
305 // Otherwise, can't handle this.
310 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock
&MBB
) const {
311 int BOpc
= Hexagon::J2_jump
;
312 int BccOpc
= Hexagon::J2_jumpt
;
313 int BccOpcNot
= Hexagon::J2_jumpf
;
315 MachineBasicBlock::iterator I
= MBB
.end();
316 if (I
== MBB
.begin()) return 0;
318 if (I
->getOpcode() != BOpc
&& I
->getOpcode() != BccOpc
&&
319 I
->getOpcode() != BccOpcNot
)
322 // Remove the branch.
323 I
->eraseFromParent();
327 if (I
== MBB
.begin()) return 1;
329 if (I
->getOpcode() != BccOpc
&& I
->getOpcode() != BccOpcNot
)
332 // Remove the branch.
333 I
->eraseFromParent();
338 /// \brief For a comparison instruction, return the source registers in
339 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
340 /// compares against in CmpValue. Return true if the comparison instruction
342 bool HexagonInstrInfo::analyzeCompare(const MachineInstr
*MI
,
343 unsigned &SrcReg
, unsigned &SrcReg2
,
344 int &Mask
, int &Value
) const {
345 unsigned Opc
= MI
->getOpcode();
347 // Set mask and the first source register.
349 case Hexagon::C2_cmpeqp
:
350 case Hexagon::C2_cmpeqi
:
351 case Hexagon::C2_cmpeq
:
352 case Hexagon::C2_cmpgtp
:
353 case Hexagon::C2_cmpgtup
:
354 case Hexagon::C2_cmpgtui
:
355 case Hexagon::C2_cmpgtu
:
356 case Hexagon::C2_cmpgti
:
357 case Hexagon::C2_cmpgt
:
358 SrcReg
= MI
->getOperand(1).getReg();
361 case Hexagon::CMPbEQri_V4
:
362 case Hexagon::CMPbEQrr_sbsb_V4
:
363 case Hexagon::CMPbEQrr_ubub_V4
:
364 case Hexagon::CMPbGTUri_V4
:
365 case Hexagon::CMPbGTUrr_V4
:
366 case Hexagon::CMPbGTrr_V4
:
367 SrcReg
= MI
->getOperand(1).getReg();
370 case Hexagon::CMPhEQri_V4
:
371 case Hexagon::CMPhEQrr_shl_V4
:
372 case Hexagon::CMPhEQrr_xor_V4
:
373 case Hexagon::CMPhGTUri_V4
:
374 case Hexagon::CMPhGTUrr_V4
:
375 case Hexagon::CMPhGTrr_shl_V4
:
376 SrcReg
= MI
->getOperand(1).getReg();
381 // Set the value/second source register.
383 case Hexagon::C2_cmpeqp
:
384 case Hexagon::C2_cmpeq
:
385 case Hexagon::C2_cmpgtp
:
386 case Hexagon::C2_cmpgtup
:
387 case Hexagon::C2_cmpgtu
:
388 case Hexagon::C2_cmpgt
:
389 case Hexagon::CMPbEQrr_sbsb_V4
:
390 case Hexagon::CMPbEQrr_ubub_V4
:
391 case Hexagon::CMPbGTUrr_V4
:
392 case Hexagon::CMPbGTrr_V4
:
393 case Hexagon::CMPhEQrr_shl_V4
:
394 case Hexagon::CMPhEQrr_xor_V4
:
395 case Hexagon::CMPhGTUrr_V4
:
396 case Hexagon::CMPhGTrr_shl_V4
:
397 SrcReg2
= MI
->getOperand(2).getReg();
400 case Hexagon::C2_cmpeqi
:
401 case Hexagon::C2_cmpgtui
:
402 case Hexagon::C2_cmpgti
:
403 case Hexagon::CMPbEQri_V4
:
404 case Hexagon::CMPbGTUri_V4
:
405 case Hexagon::CMPhEQri_V4
:
406 case Hexagon::CMPhGTUri_V4
:
408 Value
= MI
->getOperand(2).getImm();
416 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock
&MBB
,
417 MachineBasicBlock::iterator I
, DebugLoc DL
,
418 unsigned DestReg
, unsigned SrcReg
,
419 bool KillSrc
) const {
420 if (Hexagon::IntRegsRegClass
.contains(SrcReg
, DestReg
)) {
421 BuildMI(MBB
, I
, DL
, get(Hexagon::A2_tfr
), DestReg
).addReg(SrcReg
);
424 if (Hexagon::DoubleRegsRegClass
.contains(SrcReg
, DestReg
)) {
425 BuildMI(MBB
, I
, DL
, get(Hexagon::A2_tfrp
), DestReg
).addReg(SrcReg
);
428 if (Hexagon::PredRegsRegClass
.contains(SrcReg
, DestReg
)) {
429 // Map Pd = Ps to Pd = or(Ps, Ps).
430 BuildMI(MBB
, I
, DL
, get(Hexagon::C2_or
),
431 DestReg
).addReg(SrcReg
).addReg(SrcReg
);
434 if (Hexagon::DoubleRegsRegClass
.contains(DestReg
) &&
435 Hexagon::IntRegsRegClass
.contains(SrcReg
)) {
436 // We can have an overlap between single and double reg: r1:0 = r0.
437 if(SrcReg
== RI
.getSubReg(DestReg
, Hexagon::subreg_loreg
)) {
439 BuildMI(MBB
, I
, DL
, get(Hexagon::A2_tfrsi
), (RI
.getSubReg(DestReg
,
440 Hexagon::subreg_hireg
))).addImm(0);
442 // r1:0 = r1 or no overlap.
443 BuildMI(MBB
, I
, DL
, get(Hexagon::A2_tfr
), (RI
.getSubReg(DestReg
,
444 Hexagon::subreg_loreg
))).addReg(SrcReg
);
445 BuildMI(MBB
, I
, DL
, get(Hexagon::A2_tfrsi
), (RI
.getSubReg(DestReg
,
446 Hexagon::subreg_hireg
))).addImm(0);
450 if (Hexagon::CtrRegsRegClass
.contains(DestReg
) &&
451 Hexagon::IntRegsRegClass
.contains(SrcReg
)) {
452 BuildMI(MBB
, I
, DL
, get(Hexagon::A2_tfrrcr
), DestReg
).addReg(SrcReg
);
455 if (Hexagon::PredRegsRegClass
.contains(SrcReg
) &&
456 Hexagon::IntRegsRegClass
.contains(DestReg
)) {
457 BuildMI(MBB
, I
, DL
, get(Hexagon::C2_tfrpr
), DestReg
).
458 addReg(SrcReg
, getKillRegState(KillSrc
));
461 if (Hexagon::IntRegsRegClass
.contains(SrcReg
) &&
462 Hexagon::PredRegsRegClass
.contains(DestReg
)) {
463 BuildMI(MBB
, I
, DL
, get(Hexagon::C2_tfrrp
), DestReg
).
464 addReg(SrcReg
, getKillRegState(KillSrc
));
468 llvm_unreachable("Unimplemented");
472 void HexagonInstrInfo::
473 storeRegToStackSlot(MachineBasicBlock
&MBB
, MachineBasicBlock::iterator I
,
474 unsigned SrcReg
, bool isKill
, int FI
,
475 const TargetRegisterClass
*RC
,
476 const TargetRegisterInfo
*TRI
) const {
478 DebugLoc DL
= MBB
.findDebugLoc(I
);
479 MachineFunction
&MF
= *MBB
.getParent();
480 MachineFrameInfo
&MFI
= *MF
.getFrameInfo();
481 unsigned Align
= MFI
.getObjectAlignment(FI
);
483 MachineMemOperand
*MMO
=
484 MF
.getMachineMemOperand(
485 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI
)),
486 MachineMemOperand::MOStore
,
487 MFI
.getObjectSize(FI
),
490 if (Hexagon::IntRegsRegClass
.hasSubClassEq(RC
)) {
491 BuildMI(MBB
, I
, DL
, get(Hexagon::S2_storeri_io
))
492 .addFrameIndex(FI
).addImm(0)
493 .addReg(SrcReg
, getKillRegState(isKill
)).addMemOperand(MMO
);
494 } else if (Hexagon::DoubleRegsRegClass
.hasSubClassEq(RC
)) {
495 BuildMI(MBB
, I
, DL
, get(Hexagon::S2_storerd_io
))
496 .addFrameIndex(FI
).addImm(0)
497 .addReg(SrcReg
, getKillRegState(isKill
)).addMemOperand(MMO
);
498 } else if (Hexagon::PredRegsRegClass
.hasSubClassEq(RC
)) {
499 BuildMI(MBB
, I
, DL
, get(Hexagon::STriw_pred
))
500 .addFrameIndex(FI
).addImm(0)
501 .addReg(SrcReg
, getKillRegState(isKill
)).addMemOperand(MMO
);
503 llvm_unreachable("Unimplemented");
508 void HexagonInstrInfo::storeRegToAddr(
509 MachineFunction
&MF
, unsigned SrcReg
,
511 SmallVectorImpl
<MachineOperand
> &Addr
,
512 const TargetRegisterClass
*RC
,
513 SmallVectorImpl
<MachineInstr
*> &NewMIs
) const
515 llvm_unreachable("Unimplemented");
519 void HexagonInstrInfo::
520 loadRegFromStackSlot(MachineBasicBlock
&MBB
, MachineBasicBlock::iterator I
,
521 unsigned DestReg
, int FI
,
522 const TargetRegisterClass
*RC
,
523 const TargetRegisterInfo
*TRI
) const {
524 DebugLoc DL
= MBB
.findDebugLoc(I
);
525 MachineFunction
&MF
= *MBB
.getParent();
526 MachineFrameInfo
&MFI
= *MF
.getFrameInfo();
527 unsigned Align
= MFI
.getObjectAlignment(FI
);
529 MachineMemOperand
*MMO
=
530 MF
.getMachineMemOperand(
531 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI
)),
532 MachineMemOperand::MOLoad
,
533 MFI
.getObjectSize(FI
),
535 if (RC
== &Hexagon::IntRegsRegClass
) {
536 BuildMI(MBB
, I
, DL
, get(Hexagon::L2_loadri_io
), DestReg
)
537 .addFrameIndex(FI
).addImm(0).addMemOperand(MMO
);
538 } else if (RC
== &Hexagon::DoubleRegsRegClass
) {
539 BuildMI(MBB
, I
, DL
, get(Hexagon::L2_loadrd_io
), DestReg
)
540 .addFrameIndex(FI
).addImm(0).addMemOperand(MMO
);
541 } else if (RC
== &Hexagon::PredRegsRegClass
) {
542 BuildMI(MBB
, I
, DL
, get(Hexagon::LDriw_pred
), DestReg
)
543 .addFrameIndex(FI
).addImm(0).addMemOperand(MMO
);
545 llvm_unreachable("Can't store this register to stack slot");
550 void HexagonInstrInfo::loadRegFromAddr(MachineFunction
&MF
, unsigned DestReg
,
551 SmallVectorImpl
<MachineOperand
> &Addr
,
552 const TargetRegisterClass
*RC
,
553 SmallVectorImpl
<MachineInstr
*> &NewMIs
) const {
554 llvm_unreachable("Unimplemented");
558 MachineInstr
*HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction
&MF
,
560 const SmallVectorImpl
<unsigned> &Ops
,
562 // Hexagon_TODO: Implement.
566 unsigned HexagonInstrInfo::createVR(MachineFunction
* MF
, MVT VT
) const {
568 MachineRegisterInfo
&RegInfo
= MF
->getRegInfo();
569 const TargetRegisterClass
*TRC
;
571 TRC
= &Hexagon::PredRegsRegClass
;
572 } else if (VT
== MVT::i32
|| VT
== MVT::f32
) {
573 TRC
= &Hexagon::IntRegsRegClass
;
574 } else if (VT
== MVT::i64
|| VT
== MVT::f64
) {
575 TRC
= &Hexagon::DoubleRegsRegClass
;
577 llvm_unreachable("Cannot handle this register class");
580 unsigned NewReg
= RegInfo
.createVirtualRegister(TRC
);
584 bool HexagonInstrInfo::isExtendable(const MachineInstr
*MI
) const {
585 // Constant extenders are allowed only for V4 and above.
586 if (!Subtarget
.hasV4TOps())
589 const MCInstrDesc
&MID
= MI
->getDesc();
590 const uint64_t F
= MID
.TSFlags
;
591 if ((F
>> HexagonII::ExtendablePos
) & HexagonII::ExtendableMask
)
594 // TODO: This is largely obsolete now. Will need to be removed
595 // in consecutive patches.
596 switch(MI
->getOpcode()) {
597 // TFR_FI Remains a special case.
598 case Hexagon::TFR_FI
:
606 // This returns true in two cases:
607 // - The OP code itself indicates that this is an extended instruction.
608 // - One of MOs has been marked with HMOTF_ConstExtended flag.
609 bool HexagonInstrInfo::isExtended(const MachineInstr
*MI
) const {
610 // First check if this is permanently extended op code.
611 const uint64_t F
= MI
->getDesc().TSFlags
;
612 if ((F
>> HexagonII::ExtendedPos
) & HexagonII::ExtendedMask
)
614 // Use MO operand flags to determine if one of MI's operands
615 // has HMOTF_ConstExtended flag set.
616 for (MachineInstr::const_mop_iterator I
= MI
->operands_begin(),
617 E
= MI
->operands_end(); I
!= E
; ++I
) {
618 if (I
->getTargetFlags() && HexagonII::HMOTF_ConstExtended
)
624 bool HexagonInstrInfo::isBranch (const MachineInstr
*MI
) const {
625 return MI
->getDesc().isBranch();
628 bool HexagonInstrInfo::isNewValueInst(const MachineInstr
*MI
) const {
629 if (isNewValueJump(MI
))
632 if (isNewValueStore(MI
))
638 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr
*MI
) const {
639 return MI
->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4
;
642 bool HexagonInstrInfo::isPredicable(MachineInstr
*MI
) const {
643 bool isPred
= MI
->getDesc().isPredicable();
648 const int Opc
= MI
->getOpcode();
651 case Hexagon::A2_tfrsi
:
652 return isInt
<12>(MI
->getOperand(1).getImm());
654 case Hexagon::S2_storerd_io
:
655 return isShiftedUInt
<6,3>(MI
->getOperand(1).getImm());
657 case Hexagon::S2_storeri_io
:
658 case Hexagon::S2_storerinew_io
:
659 return isShiftedUInt
<6,2>(MI
->getOperand(1).getImm());
661 case Hexagon::S2_storerh_io
:
662 case Hexagon::S2_storerhnew_io
:
663 return isShiftedUInt
<6,1>(MI
->getOperand(1).getImm());
665 case Hexagon::S2_storerb_io
:
666 case Hexagon::S2_storerbnew_io
:
667 return isUInt
<6>(MI
->getOperand(1).getImm());
669 case Hexagon::L2_loadrd_io
:
670 return isShiftedUInt
<6,3>(MI
->getOperand(2).getImm());
672 case Hexagon::L2_loadri_io
:
673 return isShiftedUInt
<6,2>(MI
->getOperand(2).getImm());
675 case Hexagon::L2_loadrh_io
:
676 case Hexagon::L2_loadruh_io
:
677 return isShiftedUInt
<6,1>(MI
->getOperand(2).getImm());
679 case Hexagon::L2_loadrb_io
:
680 case Hexagon::L2_loadrub_io
:
681 return isUInt
<6>(MI
->getOperand(2).getImm());
683 case Hexagon::L2_loadrd_pi
:
684 return isShiftedInt
<4,3>(MI
->getOperand(3).getImm());
686 case Hexagon::L2_loadri_pi
:
687 return isShiftedInt
<4,2>(MI
->getOperand(3).getImm());
689 case Hexagon::L2_loadrh_pi
:
690 case Hexagon::L2_loadruh_pi
:
691 return isShiftedInt
<4,1>(MI
->getOperand(3).getImm());
693 case Hexagon::L2_loadrb_pi
:
694 case Hexagon::L2_loadrub_pi
:
695 return isInt
<4>(MI
->getOperand(3).getImm());
697 case Hexagon::S4_storeirb_io
:
698 case Hexagon::S4_storeirh_io
:
699 case Hexagon::S4_storeiri_io
:
700 return (isUInt
<6>(MI
->getOperand(1).getImm()) &&
701 isInt
<6>(MI
->getOperand(2).getImm()));
703 case Hexagon::ADD_ri
:
704 return isInt
<8>(MI
->getOperand(2).getImm());
706 case Hexagon::A2_aslh
:
707 case Hexagon::A2_asrh
:
708 case Hexagon::A2_sxtb
:
709 case Hexagon::A2_sxth
:
710 case Hexagon::A2_zxtb
:
711 case Hexagon::A2_zxth
:
712 return Subtarget
.hasV4TOps();
718 // This function performs the following inversiones:
723 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc
) const {
725 InvPredOpcode
= isPredicatedTrue(Opc
) ? Hexagon::getFalsePredOpcode(Opc
)
726 : Hexagon::getTruePredOpcode(Opc
);
727 if (InvPredOpcode
>= 0) // Valid instruction with the inverted predicate.
728 return InvPredOpcode
;
731 default: llvm_unreachable("Unexpected predicated instruction");
732 case Hexagon::C2_ccombinewt
:
733 return Hexagon::C2_ccombinewf
;
734 case Hexagon::C2_ccombinewf
:
735 return Hexagon::C2_ccombinewt
;
738 case Hexagon::L4_return_t
:
739 return Hexagon::L4_return_f
;
740 case Hexagon::L4_return_f
:
741 return Hexagon::L4_return_t
;
745 // New Value Store instructions.
746 bool HexagonInstrInfo::isNewValueStore(const MachineInstr
*MI
) const {
747 const uint64_t F
= MI
->getDesc().TSFlags
;
749 return ((F
>> HexagonII::NVStorePos
) & HexagonII::NVStoreMask
);
752 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode
) const {
753 const uint64_t F
= get(Opcode
).TSFlags
;
755 return ((F
>> HexagonII::NVStorePos
) & HexagonII::NVStoreMask
);
758 int HexagonInstrInfo::
759 getMatchingCondBranchOpcode(int Opc
, bool invertPredicate
) const {
760 enum Hexagon::PredSense inPredSense
;
761 inPredSense
= invertPredicate
? Hexagon::PredSense_false
:
762 Hexagon::PredSense_true
;
763 int CondOpcode
= Hexagon::getPredOpcode(Opc
, inPredSense
);
764 if (CondOpcode
>= 0) // Valid Conditional opcode/instruction
767 // This switch case will be removed once all the instructions have been
768 // modified to use relation maps.
770 case Hexagon::TFRI_f
:
771 return !invertPredicate
? Hexagon::TFRI_cPt_f
:
772 Hexagon::TFRI_cNotPt_f
;
773 case Hexagon::A2_combinew
:
774 return !invertPredicate
? Hexagon::C2_ccombinewt
:
775 Hexagon::C2_ccombinewf
;
778 case Hexagon::STriw_f
:
779 return !invertPredicate
? Hexagon::S2_pstorerit_io
:
780 Hexagon::S2_pstorerif_io
;
781 case Hexagon::STriw_indexed_f
:
782 return !invertPredicate
? Hexagon::S2_pstorerit_io
:
783 Hexagon::S2_pstorerif_io
;
786 case Hexagon::L4_return
:
787 return !invertPredicate
? Hexagon::L4_return_t
:
788 Hexagon::L4_return_f
;
790 llvm_unreachable("Unexpected predicable instruction");
794 bool HexagonInstrInfo::
795 PredicateInstruction(MachineInstr
*MI
,
796 const SmallVectorImpl
<MachineOperand
> &Cond
) const {
797 int Opc
= MI
->getOpcode();
798 assert (isPredicable(MI
) && "Expected predicable instruction");
799 bool invertJump
= (!Cond
.empty() && Cond
[0].isImm() &&
800 (Cond
[0].getImm() == 0));
802 // This will change MI's opcode to its predicate version.
803 // However, its operand list is still the old one, i.e. the
804 // non-predicate one.
805 MI
->setDesc(get(getMatchingCondBranchOpcode(Opc
, invertJump
)));
808 unsigned int GAIdx
= 0;
810 // Indicates whether the current MI has a GlobalAddress operand
811 bool hasGAOpnd
= false;
812 std::vector
<MachineOperand
> tmpOpnds
;
814 // Indicates whether we need to shift operands to right.
815 bool needShift
= true;
817 // The predicate is ALWAYS the FIRST input operand !!!
818 if (MI
->getNumOperands() == 0) {
819 // The non-predicate version of MI does not take any operands,
820 // i.e. no outs and no ins. In this condition, the predicate
821 // operand will be directly placed at Operands[0]. No operand
827 else if ( MI
->getOperand(MI
->getNumOperands()-1).isReg()
828 && MI
->getOperand(MI
->getNumOperands()-1).isDef()
829 && !MI
->getOperand(MI
->getNumOperands()-1).isImplicit()) {
830 // The non-predicate version of MI does not have any input operands.
831 // In this condition, we extend the length of Operands[] by one and
832 // copy the original last operand to the newly allocated slot.
833 // At this moment, it is just a place holder. Later, we will put
834 // predicate operand directly into it. No operand shift is needed.
835 // Example: r0=BARRIER (this is a faked insn used here for illustration)
836 MI
->addOperand(MI
->getOperand(MI
->getNumOperands()-1));
838 oper
= MI
->getNumOperands() - 2;
841 // We need to right shift all input operands by one. Duplicate the
842 // last operand into the newly allocated slot.
843 MI
->addOperand(MI
->getOperand(MI
->getNumOperands()-1));
848 // Operands[ MI->getNumOperands() - 2 ] has been copied into
849 // Operands[ MI->getNumOperands() - 1 ], so we start from
850 // Operands[ MI->getNumOperands() - 3 ].
851 // oper is a signed int.
852 // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
853 for (oper
= MI
->getNumOperands() - 3; oper
>= 0; --oper
)
855 MachineOperand
&MO
= MI
->getOperand(oper
);
857 // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4] Opnd[5] Opnd[6] Opnd[7]
858 // <Def0> <Def1> <Use0> <Use1> <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
862 // Predicate Operand here
863 if (MO
.isReg() && !MO
.isUse() && !MO
.isImplicit()) {
867 MI
->getOperand(oper
+1).ChangeToRegister(MO
.getReg(), MO
.isDef(),
868 MO
.isImplicit(), MO
.isKill(),
869 MO
.isDead(), MO
.isUndef(),
872 else if (MO
.isImm()) {
873 MI
->getOperand(oper
+1).ChangeToImmediate(MO
.getImm());
875 else if (MO
.isGlobal()) {
876 // MI can not have more than one GlobalAddress operand.
877 assert(hasGAOpnd
== false && "MI can only have one GlobalAddress opnd");
879 // There is no member function called "ChangeToGlobalAddress" in the
880 // MachineOperand class (not like "ChangeToRegister" and
881 // "ChangeToImmediate"). So we have to remove them from Operands[] list
882 // first, and then add them back after we have inserted the predicate
883 // operand. tmpOpnds[] is to remember these operands before we remove
885 tmpOpnds
.push_back(MO
);
887 // Operands[oper] is a GlobalAddress operand;
888 // Operands[oper+1] has been copied into Operands[oper+2];
894 llvm_unreachable("Unexpected operand type");
899 int regPos
= invertJump
? 1 : 0;
900 MachineOperand PredMO
= Cond
[regPos
];
902 // [oper] now points to the last explicit Def. Predicate operand must be
903 // located at [oper+1]. See diagram above.
904 // This assumes that the predicate is always the first operand,
905 // i.e. Operands[0+numResults], in the set of inputs
906 // It is better to have an assert here to check this. But I don't know how
907 // to write this assert because findFirstPredOperandIdx() would return -1
908 if (oper
< -1) oper
= -1;
910 MI
->getOperand(oper
+1).ChangeToRegister(PredMO
.getReg(), PredMO
.isDef(),
911 PredMO
.isImplicit(), false,
912 PredMO
.isDead(), PredMO
.isUndef(),
915 MachineRegisterInfo
&RegInfo
= MI
->getParent()->getParent()->getRegInfo();
916 RegInfo
.clearKillFlags(PredMO
.getReg());
922 // Operands[GAIdx] is the original GlobalAddress operand, which is
923 // already copied into tmpOpnds[0].
924 // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
925 // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
926 // so we start from [GAIdx+2]
927 for (i
= GAIdx
+ 2; i
< MI
->getNumOperands(); ++i
)
928 tmpOpnds
.push_back(MI
->getOperand(i
));
930 // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
931 // It is very important that we always remove from the end of Operands[]
932 // MI->getNumOperands() is at least 2 if program goes to here.
933 for (i
= MI
->getNumOperands() - 1; i
> GAIdx
; --i
)
934 MI
->RemoveOperand(i
);
936 for (i
= 0; i
< tmpOpnds
.size(); ++i
)
937 MI
->addOperand(tmpOpnds
[i
]);
946 isProfitableToIfCvt(MachineBasicBlock
&MBB
,
948 unsigned ExtraPredCycles
,
949 const BranchProbability
&Probability
) const {
956 isProfitableToIfCvt(MachineBasicBlock
&TMBB
,
958 unsigned ExtraTCycles
,
959 MachineBasicBlock
&FMBB
,
961 unsigned ExtraFCycles
,
962 const BranchProbability
&Probability
) const {
966 // Returns true if an instruction is predicated irrespective of the predicate
967 // sense. For example, all of the following will return true.
968 // if (p0) R1 = add(R2, R3)
969 // if (!p0) R1 = add(R2, R3)
970 // if (p0.new) R1 = add(R2, R3)
971 // if (!p0.new) R1 = add(R2, R3)
972 bool HexagonInstrInfo::isPredicated(const MachineInstr
*MI
) const {
973 const uint64_t F
= MI
->getDesc().TSFlags
;
975 return ((F
>> HexagonII::PredicatedPos
) & HexagonII::PredicatedMask
);
978 bool HexagonInstrInfo::isPredicated(unsigned Opcode
) const {
979 const uint64_t F
= get(Opcode
).TSFlags
;
981 return ((F
>> HexagonII::PredicatedPos
) & HexagonII::PredicatedMask
);
984 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr
*MI
) const {
985 const uint64_t F
= MI
->getDesc().TSFlags
;
987 assert(isPredicated(MI
));
988 return (!((F
>> HexagonII::PredicatedFalsePos
) &
989 HexagonII::PredicatedFalseMask
));
992 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode
) const {
993 const uint64_t F
= get(Opcode
).TSFlags
;
995 // Make sure that the instruction is predicated.
996 assert((F
>> HexagonII::PredicatedPos
) & HexagonII::PredicatedMask
);
997 return (!((F
>> HexagonII::PredicatedFalsePos
) &
998 HexagonII::PredicatedFalseMask
));
1001 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr
*MI
) const {
1002 const uint64_t F
= MI
->getDesc().TSFlags
;
1004 assert(isPredicated(MI
));
1005 return ((F
>> HexagonII::PredicatedNewPos
) & HexagonII::PredicatedNewMask
);
1008 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode
) const {
1009 const uint64_t F
= get(Opcode
).TSFlags
;
1011 assert(isPredicated(Opcode
));
1012 return ((F
>> HexagonII::PredicatedNewPos
) & HexagonII::PredicatedNewMask
);
1015 // Returns true, if a ST insn can be promoted to a new-value store.
1016 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr
*MI
) const {
1017 const HexagonRegisterInfo
& QRI
= getRegisterInfo();
1018 const uint64_t F
= MI
->getDesc().TSFlags
;
1020 return ((F
>> HexagonII::mayNVStorePos
) &
1021 HexagonII::mayNVStoreMask
&
1022 QRI
.Subtarget
.hasV4TOps());
1026 HexagonInstrInfo::DefinesPredicate(MachineInstr
*MI
,
1027 std::vector
<MachineOperand
> &Pred
) const {
1028 for (unsigned oper
= 0; oper
< MI
->getNumOperands(); ++oper
) {
1029 MachineOperand MO
= MI
->getOperand(oper
);
1030 if (MO
.isReg() && MO
.isDef()) {
1031 const TargetRegisterClass
* RC
= RI
.getMinimalPhysRegClass(MO
.getReg());
1032 if (RC
== &Hexagon::PredRegsRegClass
) {
1044 SubsumesPredicate(const SmallVectorImpl
<MachineOperand
> &Pred1
,
1045 const SmallVectorImpl
<MachineOperand
> &Pred2
) const {
1052 // We indicate that we want to reverse the branch by
1053 // inserting a 0 at the beginning of the Cond vector.
1055 bool HexagonInstrInfo::
1056 ReverseBranchCondition(SmallVectorImpl
<MachineOperand
> &Cond
) const {
1057 if (!Cond
.empty() && Cond
[0].isImm() && Cond
[0].getImm() == 0) {
1058 Cond
.erase(Cond
.begin());
1060 Cond
.insert(Cond
.begin(), MachineOperand::CreateImm(0));
1066 bool HexagonInstrInfo::
1067 isProfitableToDupForIfCvt(MachineBasicBlock
&MBB
,unsigned NumInstrs
,
1068 const BranchProbability
&Probability
) const {
1069 return (NumInstrs
<= 4);
1072 bool HexagonInstrInfo::isDeallocRet(const MachineInstr
*MI
) const {
1073 switch (MI
->getOpcode()) {
1074 default: return false;
1075 case Hexagon::L4_return
:
1076 case Hexagon::L4_return_t
:
1077 case Hexagon::L4_return_f
:
1078 case Hexagon::L4_return_tnew_pnt
:
1079 case Hexagon::L4_return_fnew_pnt
:
1080 case Hexagon::L4_return_tnew_pt
:
1081 case Hexagon::L4_return_fnew_pt
:
1087 bool HexagonInstrInfo::
1088 isValidOffset(const int Opcode
, const int Offset
) const {
1089 // This function is to check whether the "Offset" is in the correct range of
1090 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
1091 // inserted to calculate the final address. Due to this reason, the function
1092 // assumes that the "Offset" has correct alignment.
1093 // We used to assert if the offset was not properly aligned, however,
1094 // there are cases where a misaligned pointer recast can cause this
1095 // problem, and we need to allow for it. The front end warns of such
1096 // misaligns with respect to load size.
1100 case Hexagon::L2_loadri_io
:
1101 case Hexagon::LDriw_f
:
1102 case Hexagon::S2_storeri_io
:
1103 case Hexagon::STriw_f
:
1104 return (Offset
>= Hexagon_MEMW_OFFSET_MIN
) &&
1105 (Offset
<= Hexagon_MEMW_OFFSET_MAX
);
1107 case Hexagon::L2_loadrd_io
:
1108 case Hexagon::LDrid_f
:
1109 case Hexagon::S2_storerd_io
:
1110 case Hexagon::STrid_f
:
1111 return (Offset
>= Hexagon_MEMD_OFFSET_MIN
) &&
1112 (Offset
<= Hexagon_MEMD_OFFSET_MAX
);
1114 case Hexagon::L2_loadrh_io
:
1115 case Hexagon::L2_loadruh_io
:
1116 case Hexagon::S2_storerh_io
:
1117 return (Offset
>= Hexagon_MEMH_OFFSET_MIN
) &&
1118 (Offset
<= Hexagon_MEMH_OFFSET_MAX
);
1120 case Hexagon::L2_loadrb_io
:
1121 case Hexagon::S2_storerb_io
:
1122 case Hexagon::L2_loadrub_io
:
1123 return (Offset
>= Hexagon_MEMB_OFFSET_MIN
) &&
1124 (Offset
<= Hexagon_MEMB_OFFSET_MAX
);
1126 case Hexagon::ADD_ri
:
1127 case Hexagon::TFR_FI
:
1128 return (Offset
>= Hexagon_ADDI_OFFSET_MIN
) &&
1129 (Offset
<= Hexagon_ADDI_OFFSET_MAX
);
1131 case Hexagon::L4_iadd_memopw_io
:
1132 case Hexagon::L4_isub_memopw_io
:
1133 case Hexagon::L4_add_memopw_io
:
1134 case Hexagon::L4_sub_memopw_io
:
1135 case Hexagon::L4_and_memopw_io
:
1136 case Hexagon::L4_or_memopw_io
:
1137 return (0 <= Offset
&& Offset
<= 255);
1139 case Hexagon::L4_iadd_memoph_io
:
1140 case Hexagon::L4_isub_memoph_io
:
1141 case Hexagon::L4_add_memoph_io
:
1142 case Hexagon::L4_sub_memoph_io
:
1143 case Hexagon::L4_and_memoph_io
:
1144 case Hexagon::L4_or_memoph_io
:
1145 return (0 <= Offset
&& Offset
<= 127);
1147 case Hexagon::L4_iadd_memopb_io
:
1148 case Hexagon::L4_isub_memopb_io
:
1149 case Hexagon::L4_add_memopb_io
:
1150 case Hexagon::L4_sub_memopb_io
:
1151 case Hexagon::L4_and_memopb_io
:
1152 case Hexagon::L4_or_memopb_io
:
1153 return (0 <= Offset
&& Offset
<= 63);
1155 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
1156 // any size. Later pass knows how to handle it.
1157 case Hexagon::STriw_pred
:
1158 case Hexagon::LDriw_pred
:
1161 case Hexagon::J2_loop0i
:
1162 return isUInt
<10>(Offset
);
1164 // INLINEASM is very special.
1165 case Hexagon::INLINEASM
:
1169 llvm_unreachable("No offset range is defined for this opcode. "
1170 "Please define it in the above switch statement!");
1175 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
1177 bool HexagonInstrInfo::
1178 isValidAutoIncImm(const EVT VT
, const int Offset
) const {
1180 if (VT
== MVT::i64
) {
1181 return (Offset
>= Hexagon_MEMD_AUTOINC_MIN
&&
1182 Offset
<= Hexagon_MEMD_AUTOINC_MAX
&&
1183 (Offset
& 0x7) == 0);
1185 if (VT
== MVT::i32
) {
1186 return (Offset
>= Hexagon_MEMW_AUTOINC_MIN
&&
1187 Offset
<= Hexagon_MEMW_AUTOINC_MAX
&&
1188 (Offset
& 0x3) == 0);
1190 if (VT
== MVT::i16
) {
1191 return (Offset
>= Hexagon_MEMH_AUTOINC_MIN
&&
1192 Offset
<= Hexagon_MEMH_AUTOINC_MAX
&&
1193 (Offset
& 0x1) == 0);
1195 if (VT
== MVT::i8
) {
1196 return (Offset
>= Hexagon_MEMB_AUTOINC_MIN
&&
1197 Offset
<= Hexagon_MEMB_AUTOINC_MAX
);
1199 llvm_unreachable("Not an auto-inc opc!");
1203 bool HexagonInstrInfo::
1204 isMemOp(const MachineInstr
*MI
) const {
1205 // return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
1207 switch (MI
->getOpcode())
1209 default: return false;
1210 case Hexagon::L4_iadd_memopw_io
:
1211 case Hexagon::L4_isub_memopw_io
:
1212 case Hexagon::L4_add_memopw_io
:
1213 case Hexagon::L4_sub_memopw_io
:
1214 case Hexagon::L4_and_memopw_io
:
1215 case Hexagon::L4_or_memopw_io
:
1216 case Hexagon::L4_iadd_memoph_io
:
1217 case Hexagon::L4_isub_memoph_io
:
1218 case Hexagon::L4_add_memoph_io
:
1219 case Hexagon::L4_sub_memoph_io
:
1220 case Hexagon::L4_and_memoph_io
:
1221 case Hexagon::L4_or_memoph_io
:
1222 case Hexagon::L4_iadd_memopb_io
:
1223 case Hexagon::L4_isub_memopb_io
:
1224 case Hexagon::L4_add_memopb_io
:
1225 case Hexagon::L4_sub_memopb_io
:
1226 case Hexagon::L4_and_memopb_io
:
1227 case Hexagon::L4_or_memopb_io
:
1228 case Hexagon::L4_ior_memopb_io
:
1229 case Hexagon::L4_ior_memoph_io
:
1230 case Hexagon::L4_ior_memopw_io
:
1231 case Hexagon::L4_iand_memopb_io
:
1232 case Hexagon::L4_iand_memoph_io
:
1233 case Hexagon::L4_iand_memopw_io
:
1240 bool HexagonInstrInfo::
1241 isSpillPredRegOp(const MachineInstr
*MI
) const {
1242 switch (MI
->getOpcode()) {
1243 default: return false;
1244 case Hexagon::STriw_pred
:
1245 case Hexagon::LDriw_pred
:
1250 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr
*MI
) const {
1251 switch (MI
->getOpcode()) {
1252 default: return false;
1253 case Hexagon::C2_cmpeq
:
1254 case Hexagon::C2_cmpeqi
:
1255 case Hexagon::C2_cmpgt
:
1256 case Hexagon::C2_cmpgti
:
1257 case Hexagon::C2_cmpgtu
:
1258 case Hexagon::C2_cmpgtui
:
1263 bool HexagonInstrInfo::
1264 isConditionalTransfer (const MachineInstr
*MI
) const {
1265 switch (MI
->getOpcode()) {
1266 default: return false;
1267 case Hexagon::A2_tfrt
:
1268 case Hexagon::A2_tfrf
:
1269 case Hexagon::C2_cmoveit
:
1270 case Hexagon::C2_cmoveif
:
1271 case Hexagon::A2_tfrtnew
:
1272 case Hexagon::A2_tfrfnew
:
1273 case Hexagon::C2_cmovenewit
:
1274 case Hexagon::C2_cmovenewif
:
1279 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr
* MI
) const {
1280 switch (MI
->getOpcode())
1282 default: return false;
1283 case Hexagon::A2_paddf
:
1284 case Hexagon::A2_paddfnew
:
1285 case Hexagon::A2_paddt
:
1286 case Hexagon::A2_paddtnew
:
1287 case Hexagon::A2_pandf
:
1288 case Hexagon::A2_pandfnew
:
1289 case Hexagon::A2_pandt
:
1290 case Hexagon::A2_pandtnew
:
1291 case Hexagon::A4_paslhf
:
1292 case Hexagon::A4_paslhfnew
:
1293 case Hexagon::A4_paslht
:
1294 case Hexagon::A4_paslhtnew
:
1295 case Hexagon::A4_pasrhf
:
1296 case Hexagon::A4_pasrhfnew
:
1297 case Hexagon::A4_pasrht
:
1298 case Hexagon::A4_pasrhtnew
:
1299 case Hexagon::A2_porf
:
1300 case Hexagon::A2_porfnew
:
1301 case Hexagon::A2_port
:
1302 case Hexagon::A2_portnew
:
1303 case Hexagon::A2_psubf
:
1304 case Hexagon::A2_psubfnew
:
1305 case Hexagon::A2_psubt
:
1306 case Hexagon::A2_psubtnew
:
1307 case Hexagon::A2_pxorf
:
1308 case Hexagon::A2_pxorfnew
:
1309 case Hexagon::A2_pxort
:
1310 case Hexagon::A2_pxortnew
:
1311 case Hexagon::A4_psxthf
:
1312 case Hexagon::A4_psxthfnew
:
1313 case Hexagon::A4_psxtht
:
1314 case Hexagon::A4_psxthtnew
:
1315 case Hexagon::A4_psxtbf
:
1316 case Hexagon::A4_psxtbfnew
:
1317 case Hexagon::A4_psxtbt
:
1318 case Hexagon::A4_psxtbtnew
:
1319 case Hexagon::A4_pzxtbf
:
1320 case Hexagon::A4_pzxtbfnew
:
1321 case Hexagon::A4_pzxtbt
:
1322 case Hexagon::A4_pzxtbtnew
:
1323 case Hexagon::A4_pzxthf
:
1324 case Hexagon::A4_pzxthfnew
:
1325 case Hexagon::A4_pzxtht
:
1326 case Hexagon::A4_pzxthtnew
:
1327 case Hexagon::ADD_ri_cPt
:
1328 case Hexagon::ADD_ri_cNotPt
:
1329 case Hexagon::C2_ccombinewt
:
1330 case Hexagon::C2_ccombinewf
:
1335 bool HexagonInstrInfo::
1336 isConditionalLoad (const MachineInstr
* MI
) const {
1337 const HexagonRegisterInfo
& QRI
= getRegisterInfo();
1338 switch (MI
->getOpcode())
1340 default: return false;
1341 case Hexagon::L2_ploadrdt_io
:
1342 case Hexagon::L2_ploadrdf_io
:
1343 case Hexagon::L2_ploadrit_io
:
1344 case Hexagon::L2_ploadrif_io
:
1345 case Hexagon::L2_ploadrht_io
:
1346 case Hexagon::L2_ploadrhf_io
:
1347 case Hexagon::L2_ploadrbt_io
:
1348 case Hexagon::L2_ploadrbf_io
:
1349 case Hexagon::L2_ploadruht_io
:
1350 case Hexagon::L2_ploadruhf_io
:
1351 case Hexagon::L2_ploadrubt_io
:
1352 case Hexagon::L2_ploadrubf_io
:
1354 case Hexagon::L2_ploadrdt_pi
:
1355 case Hexagon::L2_ploadrdf_pi
:
1356 case Hexagon::L2_ploadrit_pi
:
1357 case Hexagon::L2_ploadrif_pi
:
1358 case Hexagon::L2_ploadrht_pi
:
1359 case Hexagon::L2_ploadrhf_pi
:
1360 case Hexagon::L2_ploadrbt_pi
:
1361 case Hexagon::L2_ploadrbf_pi
:
1362 case Hexagon::L2_ploadruht_pi
:
1363 case Hexagon::L2_ploadruhf_pi
:
1364 case Hexagon::L2_ploadrubt_pi
:
1365 case Hexagon::L2_ploadrubf_pi
:
1366 return QRI
.Subtarget
.hasV4TOps();
1367 case Hexagon::L4_ploadrdt_rr
:
1368 case Hexagon::L4_ploadrdf_rr
:
1369 case Hexagon::L4_ploadrbt_rr
:
1370 case Hexagon::L4_ploadrbf_rr
:
1371 case Hexagon::L4_ploadrubt_rr
:
1372 case Hexagon::L4_ploadrubf_rr
:
1373 case Hexagon::L4_ploadrht_rr
:
1374 case Hexagon::L4_ploadrhf_rr
:
1375 case Hexagon::L4_ploadruht_rr
:
1376 case Hexagon::L4_ploadruhf_rr
:
1377 case Hexagon::L4_ploadrit_rr
:
1378 case Hexagon::L4_ploadrif_rr
:
1379 return QRI
.Subtarget
.hasV4TOps();
1383 // Returns true if an instruction is a conditional store.
1385 // Note: It doesn't include conditional new-value stores as they can't be
1386 // converted to .new predicate.
1388 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
1390 // / \ (not OK. it will cause new-value store to be
1391 // / X conditional on p0.new while R2 producer is
1394 // p.new store p.old NV store
1395 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
1401 // [if (p0)memw(R0+#0)=R2]
1403 // The above diagram shows the steps involoved in the conversion of a predicated
1404 // store instruction to its .new predicated new-value form.
1406 // The following set of instructions further explains the scenario where
1407 // conditional new-value store becomes invalid when promoted to .new predicate
1410 // { 1) if (p0) r0 = add(r1, r2)
1411 // 2) p0 = cmp.eq(r3, #0) }
1413 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
1414 // the first two instructions because in instr 1, r0 is conditional on old value
1415 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
1416 // is not valid for new-value stores.
1417 bool HexagonInstrInfo::
1418 isConditionalStore (const MachineInstr
* MI
) const {
1419 const HexagonRegisterInfo
& QRI
= getRegisterInfo();
1420 switch (MI
->getOpcode())
1422 default: return false;
1423 case Hexagon::S4_storeirbt_io
:
1424 case Hexagon::S4_storeirbf_io
:
1425 case Hexagon::S4_pstorerbt_rr
:
1426 case Hexagon::S4_pstorerbf_rr
:
1427 case Hexagon::S2_pstorerbt_io
:
1428 case Hexagon::S2_pstorerbf_io
:
1429 case Hexagon::S2_pstorerbt_pi
:
1430 case Hexagon::S2_pstorerbf_pi
:
1431 case Hexagon::S2_pstorerdt_io
:
1432 case Hexagon::S2_pstorerdf_io
:
1433 case Hexagon::S4_pstorerdt_rr
:
1434 case Hexagon::S4_pstorerdf_rr
:
1435 case Hexagon::S2_pstorerdt_pi
:
1436 case Hexagon::S2_pstorerdf_pi
:
1437 case Hexagon::S2_pstorerht_io
:
1438 case Hexagon::S2_pstorerhf_io
:
1439 case Hexagon::S4_storeirht_io
:
1440 case Hexagon::S4_storeirhf_io
:
1441 case Hexagon::S4_pstorerht_rr
:
1442 case Hexagon::S4_pstorerhf_rr
:
1443 case Hexagon::S2_pstorerht_pi
:
1444 case Hexagon::S2_pstorerhf_pi
:
1445 case Hexagon::S2_pstorerit_io
:
1446 case Hexagon::S2_pstorerif_io
:
1447 case Hexagon::S4_storeirit_io
:
1448 case Hexagon::S4_storeirif_io
:
1449 case Hexagon::S4_pstorerit_rr
:
1450 case Hexagon::S4_pstorerif_rr
:
1451 case Hexagon::S2_pstorerit_pi
:
1452 case Hexagon::S2_pstorerif_pi
:
1453 return QRI
.Subtarget
.hasV4TOps();
1455 // V4 global address store before promoting to dot new.
1456 case Hexagon::S4_pstorerdt_abs
:
1457 case Hexagon::S4_pstorerdf_abs
:
1458 case Hexagon::S4_pstorerbt_abs
:
1459 case Hexagon::S4_pstorerbf_abs
:
1460 case Hexagon::S4_pstorerht_abs
:
1461 case Hexagon::S4_pstorerhf_abs
:
1462 case Hexagon::S4_pstorerit_abs
:
1463 case Hexagon::S4_pstorerif_abs
:
1464 return QRI
.Subtarget
.hasV4TOps();
1466 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
1467 // from the "Conditional Store" list. Because a predicated new value store
1468 // would NOT be promoted to a double dot new store. See diagram below:
1469 // This function returns yes for those stores that are predicated but not
1470 // yet promoted to predicate dot new instructions.
1472 // +---------------------+
1473 // /-----| if (p0) memw(..)=r0 |---------\~
1474 // || +---------------------+ ||
1475 // promote || /\ /\ || promote
1477 // \||/ demote || \||/
1479 // +-------------------------+ || +-------------------------+
1480 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
1481 // +-------------------------+ || +-------------------------+
1484 // promote || \/ NOT possible
1488 // +-----------------------------+
1489 // | if (p0.new) memw(..)=r0.new |
1490 // +-----------------------------+
1491 // Double Dot New Store
1497 bool HexagonInstrInfo::isNewValueJump(const MachineInstr
*MI
) const {
1498 if (isNewValue(MI
) && isBranch(MI
))
1503 bool HexagonInstrInfo::isPostIncrement (const MachineInstr
* MI
) const {
1504 return (getAddrMode(MI
) == HexagonII::PostInc
);
1507 bool HexagonInstrInfo::isNewValue(const MachineInstr
* MI
) const {
1508 const uint64_t F
= MI
->getDesc().TSFlags
;
1509 return ((F
>> HexagonII::NewValuePos
) & HexagonII::NewValueMask
);
1512 // Returns true, if any one of the operands is a dot new
1513 // insn, whether it is predicated dot new or register dot new.
1514 bool HexagonInstrInfo::isDotNewInst (const MachineInstr
* MI
) const {
1515 return (isNewValueInst(MI
) ||
1516 (isPredicated(MI
) && isPredicatedNew(MI
)));
1519 // Returns the most basic instruction for the .new predicated instructions and
1520 // new-value stores.
1521 // For example, all of the following instructions will be converted back to the
1522 // same instruction:
1523 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1524 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1525 // 3) if (p0.new) memw(R0+#0) = R1 --->
1528 int HexagonInstrInfo::GetDotOldOp(const int opc
) const {
1530 if (isPredicated(NewOp
) && isPredicatedNew(NewOp
)) { // Get predicate old form
1531 NewOp
= Hexagon::getPredOldOpcode(NewOp
);
1532 assert(NewOp
>= 0 &&
1533 "Couldn't change predicate new instruction to its old form.");
1536 if (isNewValueStore(NewOp
)) { // Convert into non-new-value format
1537 NewOp
= Hexagon::getNonNVStore(NewOp
);
1538 assert(NewOp
>= 0 && "Couldn't change new-value store to its old form.");
1543 // Return the new value instruction for a given store.
1544 int HexagonInstrInfo::GetDotNewOp(const MachineInstr
* MI
) const {
1545 int NVOpcode
= Hexagon::getNewValueOpcode(MI
->getOpcode());
1546 if (NVOpcode
>= 0) // Valid new-value store instruction.
1549 switch (MI
->getOpcode()) {
1550 default: llvm_unreachable("Unknown .new type");
1551 // store new value byte
1552 case Hexagon::STrib_shl_V4
:
1553 return Hexagon::STrib_shl_nv_V4
;
1555 case Hexagon::STrih_shl_V4
:
1556 return Hexagon::STrih_shl_nv_V4
;
1558 case Hexagon::STriw_f
:
1559 return Hexagon::S2_storerinew_io
;
1561 case Hexagon::STriw_indexed_f
:
1562 return Hexagon::S4_storerinew_rr
;
1564 case Hexagon::STriw_shl_V4
:
1565 return Hexagon::STriw_shl_nv_V4
;
1571 // Return .new predicate version for an instruction.
1572 int HexagonInstrInfo::GetDotNewPredOp(MachineInstr
*MI
,
1573 const MachineBranchProbabilityInfo
1576 int NewOpcode
= Hexagon::getPredNewOpcode(MI
->getOpcode());
1577 if (NewOpcode
>= 0) // Valid predicate new instruction
1580 switch (MI
->getOpcode()) {
1581 default: llvm_unreachable("Unknown .new type");
1583 case Hexagon::J2_jumpt
:
1584 case Hexagon::J2_jumpf
:
1585 return getDotNewPredJumpOp(MI
, MBPI
);
1587 case Hexagon::J2_jumprt
:
1588 return Hexagon::J2_jumptnewpt
;
1590 case Hexagon::J2_jumprf
:
1591 return Hexagon::J2_jumprfnewpt
;
1593 case Hexagon::JMPrett
:
1594 return Hexagon::J2_jumprtnewpt
;
1596 case Hexagon::JMPretf
:
1597 return Hexagon::J2_jumprfnewpt
;
1600 // Conditional combine
1601 case Hexagon::C2_ccombinewt
:
1602 return Hexagon::C2_ccombinewnewt
;
1603 case Hexagon::C2_ccombinewf
:
1604 return Hexagon::C2_ccombinewnewf
;
1609 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr
* MI
) const {
1610 const uint64_t F
= MI
->getDesc().TSFlags
;
1612 return((F
>> HexagonII::AddrModePos
) & HexagonII::AddrModeMask
);
1615 /// immediateExtend - Changes the instruction in place to one using an immediate
1617 void HexagonInstrInfo::immediateExtend(MachineInstr
*MI
) const {
1618 assert((isExtendable(MI
)||isConstExtended(MI
)) &&
1619 "Instruction must be extendable");
1620 // Find which operand is extendable.
1621 short ExtOpNum
= getCExtOpNum(MI
);
1622 MachineOperand
&MO
= MI
->getOperand(ExtOpNum
);
1623 // This needs to be something we understand.
1624 assert((MO
.isMBB() || MO
.isImm()) &&
1625 "Branch with unknown extendable field type");
1626 // Mark given operand as extended.
1627 MO
.addTargetFlag(HexagonII::HMOTF_ConstExtended
);
1630 DFAPacketizer
*HexagonInstrInfo::CreateTargetScheduleState(
1631 const TargetSubtargetInfo
&STI
) const {
1632 const InstrItineraryData
*II
= STI
.getInstrItineraryData();
1633 return static_cast<const HexagonSubtarget
&>(STI
).createDFAPacketizer(II
);
1636 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr
*MI
,
1637 const MachineBasicBlock
*MBB
,
1638 const MachineFunction
&MF
) const {
1639 // Debug info is never a scheduling boundary. It's necessary to be explicit
1640 // due to the special treatment of IT instructions below, otherwise a
1641 // dbg_value followed by an IT will result in the IT instruction being
1642 // considered a scheduling hazard, which is wrong. It should be the actual
1643 // instruction preceding the dbg_value instruction(s), just like it is
1644 // when debug info is not present.
1645 if (MI
->isDebugValue())
1648 // Terminators and labels can't be scheduled around.
1649 if (MI
->getDesc().isTerminator() || MI
->isPosition() || MI
->isInlineAsm())
1655 bool HexagonInstrInfo::isConstExtended(MachineInstr
*MI
) const {
1657 // Constant extenders are allowed only for V4 and above.
1658 if (!Subtarget
.hasV4TOps())
1661 const uint64_t F
= MI
->getDesc().TSFlags
;
1662 unsigned isExtended
= (F
>> HexagonII::ExtendedPos
) & HexagonII::ExtendedMask
;
1663 if (isExtended
) // Instruction must be extended.
1666 unsigned isExtendable
= (F
>> HexagonII::ExtendablePos
)
1667 & HexagonII::ExtendableMask
;
1671 short ExtOpNum
= getCExtOpNum(MI
);
1672 const MachineOperand
&MO
= MI
->getOperand(ExtOpNum
);
1673 // Use MO operand flags to determine if MO
1674 // has the HMOTF_ConstExtended flag set.
1675 if (MO
.getTargetFlags() && HexagonII::HMOTF_ConstExtended
)
1677 // If this is a Machine BB address we are talking about, and it is
1678 // not marked as extended, say so.
1682 // We could be using an instruction with an extendable immediate and shoehorn
1683 // a global address into it. If it is a global address it will be constant
1684 // extended. We do this for COMBINE.
1685 // We currently only handle isGlobal() because it is the only kind of
1686 // object we are going to end up with here for now.
1687 // In the future we probably should add isSymbol(), etc.
1688 if (MO
.isGlobal() || MO
.isSymbol())
1691 // If the extendable operand is not 'Immediate' type, the instruction should
1692 // have 'isExtended' flag set.
1693 assert(MO
.isImm() && "Extendable operand must be Immediate type");
1695 int MinValue
= getMinValue(MI
);
1696 int MaxValue
= getMaxValue(MI
);
1697 int ImmValue
= MO
.getImm();
1699 return (ImmValue
< MinValue
|| ImmValue
> MaxValue
);
1702 // Returns the opcode to use when converting MI, which is a conditional jump,
1703 // into a conditional instruction which uses the .new value of the predicate.
1704 // We also use branch probabilities to add a hint to the jump.
1706 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr
*MI
,
1708 MachineBranchProbabilityInfo
*MBPI
) const {
1710 // We assume that block can have at most two successors.
1712 MachineBasicBlock
*Src
= MI
->getParent();
1713 MachineOperand
*BrTarget
= &MI
->getOperand(1);
1714 MachineBasicBlock
*Dst
= BrTarget
->getMBB();
1716 const BranchProbability Prediction
= MBPI
->getEdgeProbability(Src
, Dst
);
1717 if (Prediction
>= BranchProbability(1,2))
1720 switch (MI
->getOpcode()) {
1721 case Hexagon::J2_jumpt
:
1722 return taken
? Hexagon::J2_jumptnewpt
: Hexagon::J2_jumptnew
;
1723 case Hexagon::J2_jumpf
:
1724 return taken
? Hexagon::J2_jumpfnewpt
: Hexagon::J2_jumpfnew
;
1727 llvm_unreachable("Unexpected jump instruction.");
1730 // Returns true if a particular operand is extendable for an instruction.
1731 bool HexagonInstrInfo::isOperandExtended(const MachineInstr
*MI
,
1732 unsigned short OperandNum
) const {
1733 // Constant extenders are allowed only for V4 and above.
1734 if (!Subtarget
.hasV4TOps())
1737 const uint64_t F
= MI
->getDesc().TSFlags
;
1739 return ((F
>> HexagonII::ExtendableOpPos
) & HexagonII::ExtendableOpMask
)
1743 // Returns Operand Index for the constant extended instruction.
1744 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr
*MI
) const {
1745 const uint64_t F
= MI
->getDesc().TSFlags
;
1746 return ((F
>> HexagonII::ExtendableOpPos
) & HexagonII::ExtendableOpMask
);
1749 // Returns the min value that doesn't need to be extended.
1750 int HexagonInstrInfo::getMinValue(const MachineInstr
*MI
) const {
1751 const uint64_t F
= MI
->getDesc().TSFlags
;
1752 unsigned isSigned
= (F
>> HexagonII::ExtentSignedPos
)
1753 & HexagonII::ExtentSignedMask
;
1754 unsigned bits
= (F
>> HexagonII::ExtentBitsPos
)
1755 & HexagonII::ExtentBitsMask
;
1757 if (isSigned
) // if value is signed
1758 return -1U << (bits
- 1);
1763 // Returns the max value that doesn't need to be extended.
1764 int HexagonInstrInfo::getMaxValue(const MachineInstr
*MI
) const {
1765 const uint64_t F
= MI
->getDesc().TSFlags
;
1766 unsigned isSigned
= (F
>> HexagonII::ExtentSignedPos
)
1767 & HexagonII::ExtentSignedMask
;
1768 unsigned bits
= (F
>> HexagonII::ExtentBitsPos
)
1769 & HexagonII::ExtentBitsMask
;
1771 if (isSigned
) // if value is signed
1772 return ~(-1U << (bits
- 1));
1774 return ~(-1U << bits
);
1777 // Returns true if an instruction can be converted into a non-extended
1778 // equivalent instruction.
1779 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr
*MI
) const {
1782 // Check if the instruction has a register form that uses register in place
1783 // of the extended operand, if so return that as the non-extended form.
1784 if (Hexagon::getRegForm(MI
->getOpcode()) >= 0)
1787 if (MI
->getDesc().mayLoad() || MI
->getDesc().mayStore()) {
1788 // Check addressing mode and retrieve non-ext equivalent instruction.
1790 switch (getAddrMode(MI
)) {
1791 case HexagonII::Absolute
:
1792 // Load/store with absolute addressing mode can be converted into
1793 // base+offset mode.
1794 NonExtOpcode
= Hexagon::getBasedWithImmOffset(MI
->getOpcode());
1796 case HexagonII::BaseImmOffset
:
1797 // Load/store with base+offset addressing mode can be converted into
1798 // base+register offset addressing mode. However left shift operand should
1800 NonExtOpcode
= Hexagon::getBaseWithRegOffset(MI
->getOpcode());
1805 if (NonExtOpcode
< 0)
1812 // Returns opcode of the non-extended equivalent instruction.
1813 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr
*MI
) const {
1815 // Check if the instruction has a register form that uses register in place
1816 // of the extended operand, if so return that as the non-extended form.
1817 short NonExtOpcode
= Hexagon::getRegForm(MI
->getOpcode());
1818 if (NonExtOpcode
>= 0)
1819 return NonExtOpcode
;
1821 if (MI
->getDesc().mayLoad() || MI
->getDesc().mayStore()) {
1822 // Check addressing mode and retrieve non-ext equivalent instruction.
1823 switch (getAddrMode(MI
)) {
1824 case HexagonII::Absolute
:
1825 return Hexagon::getBasedWithImmOffset(MI
->getOpcode());
1826 case HexagonII::BaseImmOffset
:
1827 return Hexagon::getBaseWithRegOffset(MI
->getOpcode());
1835 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode
) const {
1836 return (Opcode
== Hexagon::J2_jumpt
) ||
1837 (Opcode
== Hexagon::J2_jumpf
) ||
1838 (Opcode
== Hexagon::J2_jumptnewpt
) ||
1839 (Opcode
== Hexagon::J2_jumpfnewpt
) ||
1840 (Opcode
== Hexagon::J2_jumpt
) ||
1841 (Opcode
== Hexagon::J2_jumpf
);
1844 bool HexagonInstrInfo::PredOpcodeHasNot(Opcode_t Opcode
) const {
1845 return (Opcode
== Hexagon::J2_jumpf
) ||
1846 (Opcode
== Hexagon::J2_jumpfnewpt
) ||
1847 (Opcode
== Hexagon::J2_jumpfnew
);