1 //=- HexagonInstrInfoV3.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V3 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 def callv3 : SDNode<"HexagonISD::CALLv3", SDT_SPCall,
15 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
17 def callv3nr : SDNode<"HexagonISD::CALLv3nr", SDT_SPCall,
18 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
20 //===----------------------------------------------------------------------===//
22 //===----------------------------------------------------------------------===//
24 let isCall = 1, hasSideEffects = 1, validSubTargets = HasV3SubT,
25 Defs = VolatileV3.Regs, isPredicable = 1,
26 isExtended = 0, isExtendable = 1, opExtendable = 0,
27 isExtentSigned = 1, opExtentBits = 24, opExtentAlign = 2 in
28 class T_Call<string ExtStr>
29 : JInst<(outs), (ins calltarget:$dst),
30 "call " # ExtStr # "$dst", [], "", J_tc_2early_SLOT23> {
31 let BaseOpcode = "call";
35 let Inst{27-25} = 0b101;
36 let Inst{24-16,13-1} = dst{23-2};
40 let isCall = 1, hasSideEffects = 1, validSubTargets = HasV3SubT,
41 Defs = VolatileV3.Regs, isPredicated = 1,
42 isExtended = 0, isExtendable = 1, opExtendable = 1,
43 isExtentSigned = 1, opExtentBits = 17, opExtentAlign = 2 in
44 class T_CallPred<bit IfTrue, string ExtStr>
45 : JInst<(outs), (ins PredRegs:$Pu, calltarget:$dst),
46 CondStr<"$Pu", IfTrue, 0>.S # "call " # ExtStr # "$dst",
47 [], "", J_tc_2early_SLOT23> {
48 let BaseOpcode = "call";
49 let isPredicatedFalse = !if(IfTrue,0,1);
54 let Inst{27-24} = 0b1101;
55 let Inst{23-22,20-16,13,7-1} = dst{16-2};
56 let Inst{21} = !if(IfTrue,0,1);
61 multiclass T_Calls<string ExtStr> {
62 def NAME : T_Call<ExtStr>;
63 def t : T_CallPred<1, ExtStr>;
64 def f : T_CallPred<0, ExtStr>;
67 let isCodeGenOnly = 0 in
68 defm J2_call: T_Calls<"">, PredRel;
70 //===----------------------------------------------------------------------===//
72 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 //===----------------------------------------------------------------------===//
78 // Call subroutine from register.
79 let isCall = 1, hasSideEffects = 0,
80 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31,
81 P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
82 def CALLRv3 : JRInst<(outs), (ins IntRegs:$dst),
84 []>, Requires<[HasV3TOnly]>;
87 //===----------------------------------------------------------------------===//
89 //===----------------------------------------------------------------------===//
91 //===----------------------------------------------------------------------===//
93 //===----------------------------------------------------------------------===//
96 let Defs = [USR_OVF], Itinerary = ALU64_tc_2_SLOT23,
97 validSubTargets = HasV3SubT, isCodeGenOnly = 0 in
98 def A2_addpsat : T_ALU64_arith<"add", 0b011, 0b101, 1, 0, 1>;
100 class T_ALU64_addsp_hl<string suffix, bits<3> MinOp>
101 : T_ALU64_rr<"add", suffix, 0b0011, 0b011, MinOp, 0, 0, "">;
103 let isCodeGenOnly = 0 in {
104 def A2_addspl : T_ALU64_addsp_hl<":raw:lo", 0b110>;
105 def A2_addsph : T_ALU64_addsp_hl<":raw:hi", 0b111>;
108 let hasSideEffects = 0, isCodeGenOnly = 0 in
109 def A2_addsp : ALU64_rr<(outs DoubleRegs:$Rd),
110 (ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)",
111 [(set (i64 DoubleRegs:$Rd), (i64 (add (i64 (sext (i32 IntRegs:$Rs))),
112 (i64 DoubleRegs:$Rt))))],
113 "", ALU64_tc_1_SLOT23>;
116 let hasSideEffects = 0 in
117 class T_XTYPE_MIN_MAX_P<bit isMax, bit isUnsigned>
118 : ALU64Inst<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rt, DoubleRegs:$Rs),
119 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
120 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
127 let Inst{27-23} = 0b00111;
128 let Inst{22-21} = !if(isMax, 0b10, 0b01);
129 let Inst{20-16} = !if(isMax, Rt, Rs);
130 let Inst{12-8} = !if(isMax, Rs, Rt);
132 let Inst{6} = !if(isMax, 0b0, 0b1);
133 let Inst{5} = isUnsigned;
137 let isCodeGenOnly = 0 in {
138 def A2_minp : T_XTYPE_MIN_MAX_P<0, 0>;
139 def A2_minup : T_XTYPE_MIN_MAX_P<0, 1>;
140 def A2_maxp : T_XTYPE_MIN_MAX_P<1, 0>;
141 def A2_maxup : T_XTYPE_MIN_MAX_P<1, 1>;
144 multiclass MinMax_pats_p<PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
145 defm: T_MinMax_pats<Op, DoubleRegs, i64, Inst, SwapInst>;
148 let AddedComplexity = 200 in {
149 defm: MinMax_pats_p<setge, A2_maxp, A2_minp>;
150 defm: MinMax_pats_p<setgt, A2_maxp, A2_minp>;
151 defm: MinMax_pats_p<setle, A2_minp, A2_maxp>;
152 defm: MinMax_pats_p<setlt, A2_minp, A2_maxp>;
153 defm: MinMax_pats_p<setuge, A2_maxup, A2_minup>;
154 defm: MinMax_pats_p<setugt, A2_maxup, A2_minup>;
155 defm: MinMax_pats_p<setule, A2_minup, A2_maxup>;
156 defm: MinMax_pats_p<setult, A2_minup, A2_maxup>;
159 //===----------------------------------------------------------------------===//
161 //===----------------------------------------------------------------------===//
166 //def : Pat <(brcond (i1 (seteq (i32 IntRegs:$src1), 0)), bb:$offset),
167 // (JMP_RegEzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
169 //def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), 0)), bb:$offset),
170 // (JMP_RegNzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
172 //def : Pat <(brcond (i1 (setle (i32 IntRegs:$src1), 0)), bb:$offset),
173 // (JMP_RegLezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
175 //def : Pat <(brcond (i1 (setge (i32 IntRegs:$src1), 0)), bb:$offset),
176 // (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
178 //def : Pat <(brcond (i1 (setgt (i32 IntRegs:$src1), -1)), bb:$offset),
179 // (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
182 // Map call instruction
183 def : Pat<(call (i32 IntRegs:$dst)),
184 (J2_call (i32 IntRegs:$dst))>, Requires<[HasV3T]>;
185 def : Pat<(call tglobaladdr:$dst),
186 (J2_call tglobaladdr:$dst)>, Requires<[HasV3T]>;
187 def : Pat<(call texternalsym:$dst),
188 (J2_call texternalsym:$dst)>, Requires<[HasV3T]>;