src/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp

   1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "MipsSEISelDAGToDAG.h"
  15 #include "MCTargetDesc/MipsBaseInfo.h"
  16 #include "Mips.h"
  17 #include "MipsAnalyzeImmediate.h"
  18 #include "MipsMachineFunction.h"
  19 #include "MipsRegisterInfo.h"
  20 #include "llvm/CodeGen/MachineConstantPool.h"
  21 #include "llvm/CodeGen/MachineFrameInfo.h"
  22 #include "llvm/CodeGen/MachineFunction.h"
  23 #include "llvm/CodeGen/MachineInstrBuilder.h"
  24 #include "llvm/CodeGen/MachineRegisterInfo.h"
  25 #include "llvm/CodeGen/SelectionDAGNodes.h"
  26 #include "llvm/IR/CFG.h"
  27 #include "llvm/IR/GlobalValue.h"
  28 #include "llvm/IR/Instructions.h"
  29 #include "llvm/IR/Intrinsics.h"
  30 #include "llvm/IR/Type.h"
  31 #include "llvm/Support/Debug.h"
  32 #include "llvm/Support/ErrorHandling.h"
  33 #include "llvm/Support/raw_ostream.h"
  34 #include "llvm/Target/TargetMachine.h"
  35 using namespace llvm;
  36
  37 #define DEBUG_TYPE "mips-isel"
  38
  39 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
  40   Subtarget = &TM.getSubtarget<MipsSubtarget>();
  41   if (Subtarget->inMips16Mode())
  42     return false;
  43   return MipsDAGToDAGISel::runOnMachineFunction(MF);
  44 }
  45
  46 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
  47                                                MachineFunction &MF) {
  48   MachineInstrBuilder MIB(MF, &MI);
  49   unsigned Mask = MI.getOperand(1).getImm();
  50   unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
  51
  52   if (Mask & 1)
  53     MIB.addReg(Mips::DSPPos, Flag);
  54
  55   if (Mask & 2)
  56     MIB.addReg(Mips::DSPSCount, Flag);
  57
  58   if (Mask & 4)
  59     MIB.addReg(Mips::DSPCarry, Flag);
  60
  61   if (Mask & 8)
  62     MIB.addReg(Mips::DSPOutFlag, Flag);
  63
  64   if (Mask & 16)
  65     MIB.addReg(Mips::DSPCCond, Flag);
  66
  67   if (Mask & 32)
  68     MIB.addReg(Mips::DSPEFI, Flag);
  69 }
  70
  71 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
  72   switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
  73   default:
  74     llvm_unreachable("Could not map int to register");
  75   case 0: return Mips::MSAIR;
  76   case 1: return Mips::MSACSR;
  77   case 2: return Mips::MSAAccess;
  78   case 3: return Mips::MSASave;
  79   case 4: return Mips::MSAModify;
  80   case 5: return Mips::MSARequest;
  81   case 6: return Mips::MSAMap;
  82   case 7: return Mips::MSAUnmap;
  83   }
  84 }
  85
  86 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
  87                                                 const MachineInstr& MI) {
  88   unsigned DstReg = 0, ZeroReg = 0;
  89
  90   // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
  91   if ((MI.getOpcode() == Mips::ADDiu) &&
  92       (MI.getOperand(1).getReg() == Mips::ZERO) &&
  93       (MI.getOperand(2).getImm() == 0)) {
  94     DstReg = MI.getOperand(0).getReg();
  95     ZeroReg = Mips::ZERO;
  96   } else if ((MI.getOpcode() == Mips::DADDiu) &&
  97              (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
  98              (MI.getOperand(2).getImm() == 0)) {
  99     DstReg = MI.getOperand(0).getReg();
 100     ZeroReg = Mips::ZERO_64;
 101   }
 102
 103   if (!DstReg)
 104     return false;
 105
 106   // Replace uses with ZeroReg.
 107   for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
 108        E = MRI->use_end(); U != E;) {
 109     MachineOperand &MO = *U;
 110     unsigned OpNo = U.getOperandNo();
 111     MachineInstr *MI = MO.getParent();
 112     ++U;
 113
 114     // Do not replace if it is a phi's operand or is tied to def operand.
 115     if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
 116       continue;
 117
 118     MO.setReg(ZeroReg);
 119   }
 120
 121   return true;
 122 }
 123
 124 void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
 125   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 126
 127   if (!MipsFI->globalBaseRegSet())
 128     return;
 129
 130   MachineBasicBlock &MBB = MF.front();
 131   MachineBasicBlock::iterator I = MBB.begin();
 132   MachineRegisterInfo &RegInfo = MF.getRegInfo();
 133   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
 134   DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
 135   unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
 136   const TargetRegisterClass *RC;
 137
 138   RC = (Subtarget->isABI_N64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
 139
 140   V0 = RegInfo.createVirtualRegister(RC);
 141   V1 = RegInfo.createVirtualRegister(RC);
 142
 143   if (Subtarget->isABI_N64()) {
 144     MF.getRegInfo().addLiveIn(Mips::T9_64);
 145     MBB.addLiveIn(Mips::T9_64);
 146
 147     // lui $v0, %hi(%neg(%gp_rel(fname)))
 148     // daddu $v1, $v0, $t9
 149     // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
 150     const GlobalValue *FName = MF.getFunction();
 151     BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
 152       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
 153     BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
 154       .addReg(Mips::T9_64);
 155     BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
 156       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
 157     return;
 158   }
 159
 160   if (MF.getTarget().getRelocationModel() == Reloc::Static) {
 161     // Set global register to __gnu_local_gp.
 162     //
 163     // lui   $v0, %hi(__gnu_local_gp)
 164     // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
 165     BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
 166       .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
 167     BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
 168       .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
 169     return;
 170   }
 171
 172   MF.getRegInfo().addLiveIn(Mips::T9);
 173   MBB.addLiveIn(Mips::T9);
 174
 175   if (Subtarget->isABI_N32()) {
 176     // lui $v0, %hi(%neg(%gp_rel(fname)))
 177     // addu $v1, $v0, $t9
 178     // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
 179     const GlobalValue *FName = MF.getFunction();
 180     BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
 181       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
 182     BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
 183     BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
 184       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
 185     return;
 186   }
 187
 188   assert(Subtarget->isABI_O32());
 189
 190   // For O32 ABI, the following instruction sequence is emitted to initialize
 191   // the global base register:
 192   //
 193   //  0. lui   $2, %hi(_gp_disp)
 194   //  1. addiu $2, $2, %lo(_gp_disp)
 195   //  2. addu  $globalbasereg, $2, $t9
 196   //
 197   // We emit only the last instruction here.
 198   //
 199   // GNU linker requires that the first two instructions appear at the beginning
 200   // of a function and no instructions be inserted before or between them.
 201   // The two instructions are emitted during lowering to MC layer in order to
 202   // avoid any reordering.
 203   //
 204   // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
 205   // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
 206   // reads it.
 207   MF.getRegInfo().addLiveIn(Mips::V0);
 208   MBB.addLiveIn(Mips::V0);
 209   BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
 210     .addReg(Mips::V0).addReg(Mips::T9);
 211 }
 212
 213 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
 214   initGlobalBaseReg(MF);
 215
 216   MachineRegisterInfo *MRI = &MF.getRegInfo();
 217
 218   for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
 219        ++MFI)
 220     for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
 221       if (I->getOpcode() == Mips::RDDSP)
 222         addDSPCtrlRegOperands(false, *I, MF);
 223       else if (I->getOpcode() == Mips::WRDSP)
 224         addDSPCtrlRegOperands(true, *I, MF);
 225       else
 226         replaceUsesWithZeroReg(MRI, *I);
 227     }
 228 }
 229
 230 SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
 231                                            SDValue CmpLHS, SDLoc DL,
 232                                            SDNode *Node) const {
 233   unsigned Opc = InFlag.getOpcode(); (void)Opc;
 234
 235   assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
 236           (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
 237          "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
 238
 239   SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
 240   SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
 241   EVT VT = LHS.getValueType();
 242
 243   SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);
 244   SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
 245                                             SDValue(Carry, 0), RHS);
 246   return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
 247                               SDValue(AddCarry, 0));
 248 }
 249
 250 /// Match frameindex
 251 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
 252                                               SDValue &Offset) const {
 253   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
 254     EVT ValTy = Addr.getValueType();
 255
 256     Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
 257     Offset = CurDAG->getTargetConstant(0, ValTy);
 258     return true;
 259   }
 260   return false;
 261 }
 262
 263 /// Match frameindex+offset and frameindex|offset
 264 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base,
 265                                                     SDValue &Offset,
 266                                                     unsigned OffsetBits) const {
 267   if (CurDAG->isBaseWithConstantOffset(Addr)) {
 268     ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
 269     if (isIntN(OffsetBits, CN->getSExtValue())) {
 270       EVT ValTy = Addr.getValueType();
 271
 272       // If the first operand is a FI, get the TargetFI Node
 273       if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
 274                                   (Addr.getOperand(0)))
 275         Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
 276       else
 277         Base = Addr.getOperand(0);
 278
 279       Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
 280       return true;
 281     }
 282   }
 283   return false;
 284 }
 285
 286 /// ComplexPattern used on MipsInstrInfo
 287 /// Used on Mips Load/Store instructions
 288 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
 289                                           SDValue &Offset) const {
 290   // if Address is FI, get the TargetFrameIndex.
 291   if (selectAddrFrameIndex(Addr, Base, Offset))
 292     return true;
 293
 294   // on PIC code Load GA
 295   if (Addr.getOpcode() == MipsISD::Wrapper) {
 296     Base   = Addr.getOperand(0);
 297     Offset = Addr.getOperand(1);
 298     return true;
 299   }
 300
 301   if (TM.getRelocationModel() != Reloc::PIC_) {
 302     if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
 303         Addr.getOpcode() == ISD::TargetGlobalAddress))
 304       return false;
 305   }
 306
 307   // Addresses of the form FI+const or FI|const
 308   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
 309     return true;
 310
 311   // Operand is a result from an ADD.
 312   if (Addr.getOpcode() == ISD::ADD) {
 313     // When loading from constant pools, load the lower address part in
 314     // the instruction itself. Example, instead of:
 315     //  lui $2, %hi($CPI1_0)
 316     //  addiu $2, $2, %lo($CPI1_0)
 317     //  lwc1 $f0, 0($2)
 318     // Generate:
 319     //  lui $2, %hi($CPI1_0)
 320     //  lwc1 $f0, %lo($CPI1_0)($2)
 321     if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
 322         Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
 323       SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
 324       if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
 325           isa<JumpTableSDNode>(Opnd0)) {
 326         Base = Addr.getOperand(0);
 327         Offset = Opnd0;
 328         return true;
 329       }
 330     }
 331   }
 332
 333   return false;
 334 }
 335
 336 /// ComplexPattern used on MipsInstrInfo
 337 /// Used on Mips Load/Store instructions
 338 bool MipsSEDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base,
 339                                           SDValue &Offset) const {
 340   // Operand is a result from an ADD.
 341   if (Addr.getOpcode() == ISD::ADD) {
 342     Base = Addr.getOperand(0);
 343     Offset = Addr.getOperand(1);
 344     return true;
 345   }
 346
 347   return false;
 348 }
 349
 350 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
 351                                            SDValue &Offset) const {
 352   Base = Addr;
 353   Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
 354   return true;
 355 }
 356
 357 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
 358                                        SDValue &Offset) const {
 359   return selectAddrRegImm(Addr, Base, Offset) ||
 360     selectAddrDefault(Addr, Base, Offset);
 361 }
 362
 363 bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base,
 364                                             SDValue &Offset) const {
 365   if (selectAddrFrameIndex(Addr, Base, Offset))
 366     return true;
 367
 368   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
 369     return true;
 370
 371   return false;
 372 }
 373
 374 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
 375 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
 376                                             SDValue &Offset) const {
 377   if (selectAddrFrameIndex(Addr, Base, Offset))
 378     return true;
 379
 380   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
 381     return true;
 382
 383   return false;
 384 }
 385
 386 bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
 387                                          SDValue &Offset) const {
 388   return selectAddrRegImm12(Addr, Base, Offset) ||
 389     selectAddrDefault(Addr, Base, Offset);
 390 }
 391
 392 bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
 393                                           SDValue &Offset) const {
 394   if (selectAddrRegImm10(Addr, Base, Offset))
 395     return true;
 396
 397   if (selectAddrDefault(Addr, Base, Offset))
 398     return true;
 399
 400   return false;
 401 }
 402
 403 // Select constant vector splats.
 404 //
 405 // Returns true and sets Imm if:
 406 // * MSA is enabled
 407 // * N is a ISD::BUILD_VECTOR representing a constant splat
 408 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
 409   if (!Subtarget->hasMSA())
 410     return false;
 411
 412   BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
 413
 414   if (!Node)
 415     return false;
 416
 417   APInt SplatValue, SplatUndef;
 418   unsigned SplatBitSize;
 419   bool HasAnyUndefs;
 420
 421   if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
 422                              HasAnyUndefs, 8,
 423                              !Subtarget->isLittle()))
 424     return false;
 425
 426   Imm = SplatValue;
 427
 428   return true;
 429 }
 430
 431 // Select constant vector splats.
 432 //
 433 // In addition to the requirements of selectVSplat(), this function returns
 434 // true and sets Imm if:
 435 // * The splat value is the same width as the elements of the vector
 436 // * The splat value fits in an integer with the specified signed-ness and
 437 //   width.
 438 //
 439 // This function looks through ISD::BITCAST nodes.
 440 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
 441 //       sometimes a shuffle in big-endian mode.
 442 //
 443 // It's worth noting that this function is not used as part of the selection
 444 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
 445 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
 446 // MipsSEDAGToDAGISel::selectNode.
 447 bool MipsSEDAGToDAGISel::
 448 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
 449                    unsigned ImmBitSize) const {
 450   APInt ImmValue;
 451   EVT EltTy = N->getValueType(0).getVectorElementType();
 452
 453   if (N->getOpcode() == ISD::BITCAST)
 454     N = N->getOperand(0);
 455
 456   if (selectVSplat (N.getNode(), ImmValue) &&
 457       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
 458     if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
 459         (!Signed && ImmValue.isIntN(ImmBitSize))) {
 460       Imm = CurDAG->getTargetConstant(ImmValue, EltTy);
 461       return true;
 462     }
 463   }
 464
 465   return false;
 466 }
 467
 468 // Select constant vector splats.
 469 bool MipsSEDAGToDAGISel::
 470 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
 471   return selectVSplatCommon(N, Imm, false, 1);
 472 }
 473
 474 bool MipsSEDAGToDAGISel::
 475 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
 476   return selectVSplatCommon(N, Imm, false, 2);
 477 }
 478
 479 bool MipsSEDAGToDAGISel::
 480 selectVSplatUimm3(SDValue N, SDValue &Imm) const {
 481   return selectVSplatCommon(N, Imm, false, 3);
 482 }
 483
 484 // Select constant vector splats.
 485 bool MipsSEDAGToDAGISel::
 486 selectVSplatUimm4(SDValue N, SDValue &Imm) const {
 487   return selectVSplatCommon(N, Imm, false, 4);
 488 }
 489
 490 // Select constant vector splats.
 491 bool MipsSEDAGToDAGISel::
 492 selectVSplatUimm5(SDValue N, SDValue &Imm) const {
 493   return selectVSplatCommon(N, Imm, false, 5);
 494 }
 495
 496 // Select constant vector splats.
 497 bool MipsSEDAGToDAGISel::
 498 selectVSplatUimm6(SDValue N, SDValue &Imm) const {
 499   return selectVSplatCommon(N, Imm, false, 6);
 500 }
 501
 502 // Select constant vector splats.
 503 bool MipsSEDAGToDAGISel::
 504 selectVSplatUimm8(SDValue N, SDValue &Imm) const {
 505   return selectVSplatCommon(N, Imm, false, 8);
 506 }
 507
 508 // Select constant vector splats.
 509 bool MipsSEDAGToDAGISel::
 510 selectVSplatSimm5(SDValue N, SDValue &Imm) const {
 511   return selectVSplatCommon(N, Imm, true, 5);
 512 }
 513
 514 // Select constant vector splats whose value is a power of 2.
 515 //
 516 // In addition to the requirements of selectVSplat(), this function returns
 517 // true and sets Imm if:
 518 // * The splat value is the same width as the elements of the vector
 519 // * The splat value is a power of two.
 520 //
 521 // This function looks through ISD::BITCAST nodes.
 522 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
 523 //       sometimes a shuffle in big-endian mode.
 524 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
 525   APInt ImmValue;
 526   EVT EltTy = N->getValueType(0).getVectorElementType();
 527
 528   if (N->getOpcode() == ISD::BITCAST)
 529     N = N->getOperand(0);
 530
 531   if (selectVSplat (N.getNode(), ImmValue) &&
 532       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
 533     int32_t Log2 = ImmValue.exactLogBase2();
 534
 535     if (Log2 != -1) {
 536       Imm = CurDAG->getTargetConstant(Log2, EltTy);
 537       return true;
 538     }
 539   }
 540
 541   return false;
 542 }
 543
 544 // Select constant vector splats whose value only has a consecutive sequence
 545 // of left-most bits set (e.g. 0b11...1100...00).
 546 //
 547 // In addition to the requirements of selectVSplat(), this function returns
 548 // true and sets Imm if:
 549 // * The splat value is the same width as the elements of the vector
 550 // * The splat value is a consecutive sequence of left-most bits.
 551 //
 552 // This function looks through ISD::BITCAST nodes.
 553 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
 554 //       sometimes a shuffle in big-endian mode.
 555 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
 556   APInt ImmValue;
 557   EVT EltTy = N->getValueType(0).getVectorElementType();
 558
 559   if (N->getOpcode() == ISD::BITCAST)
 560     N = N->getOperand(0);
 561
 562   if (selectVSplat(N.getNode(), ImmValue) &&
 563       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
 564     // Extract the run of set bits starting with bit zero from the bitwise
 565     // inverse of ImmValue, and test that the inverse of this is the same
 566     // as the original value.
 567     if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
 568
 569       Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
 570       return true;
 571     }
 572   }
 573
 574   return false;
 575 }
 576
 577 // Select constant vector splats whose value only has a consecutive sequence
 578 // of right-most bits set (e.g. 0b00...0011...11).
 579 //
 580 // In addition to the requirements of selectVSplat(), this function returns
 581 // true and sets Imm if:
 582 // * The splat value is the same width as the elements of the vector
 583 // * The splat value is a consecutive sequence of right-most bits.
 584 //
 585 // This function looks through ISD::BITCAST nodes.
 586 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
 587 //       sometimes a shuffle in big-endian mode.
 588 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
 589   APInt ImmValue;
 590   EVT EltTy = N->getValueType(0).getVectorElementType();
 591
 592   if (N->getOpcode() == ISD::BITCAST)
 593     N = N->getOperand(0);
 594
 595   if (selectVSplat(N.getNode(), ImmValue) &&
 596       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
 597     // Extract the run of set bits starting with bit zero, and test that the
 598     // result is the same as the original value
 599     if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
 600       Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
 601       return true;
 602     }
 603   }
 604
 605   return false;
 606 }
 607
 608 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
 609                                                  SDValue &Imm) const {
 610   APInt ImmValue;
 611   EVT EltTy = N->getValueType(0).getVectorElementType();
 612
 613   if (N->getOpcode() == ISD::BITCAST)
 614     N = N->getOperand(0);
 615
 616   if (selectVSplat(N.getNode(), ImmValue) &&
 617       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
 618     int32_t Log2 = (~ImmValue).exactLogBase2();
 619
 620     if (Log2 != -1) {
 621       Imm = CurDAG->getTargetConstant(Log2, EltTy);
 622       return true;
 623     }
 624   }
 625
 626   return false;
 627 }
 628
 629 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
 630   unsigned Opcode = Node->getOpcode();
 631   SDLoc DL(Node);
 632
 633   ///
 634   // Instruction Selection not handled by the auto-generated
 635   // tablegen selection should be handled here.
 636   ///
 637   SDNode *Result;
 638
 639   switch(Opcode) {
 640   default: break;
 641
 642   case ISD::SUBE: {
 643     SDValue InFlag = Node->getOperand(2);
 644     Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node);
 645     return std::make_pair(true, Result);
 646   }
 647
 648   case ISD::ADDE: {
 649     if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
 650       break;
 651     SDValue InFlag = Node->getOperand(2);
 652     Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
 653     return std::make_pair(true, Result);
 654   }
 655
 656   case ISD::ConstantFP: {
 657     ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
 658     if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
 659       if (Subtarget->isGP64bit()) {
 660         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
 661                                               Mips::ZERO_64, MVT::i64);
 662         Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
 663       } else if (Subtarget->isFP64bit()) {
 664         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
 665                                               Mips::ZERO, MVT::i32);
 666         Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64,
 667                                         Zero, Zero);
 668       } else {
 669         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
 670                                               Mips::ZERO, MVT::i32);
 671         Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
 672                                         Zero);
 673       }
 674
 675       return std::make_pair(true, Result);
 676     }
 677     break;
 678   }
 679
 680   case ISD::Constant: {
 681     const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
 682     unsigned Size = CN->getValueSizeInBits(0);
 683
 684     if (Size == 32)
 685       break;
 686
 687     MipsAnalyzeImmediate AnalyzeImm;
 688     int64_t Imm = CN->getSExtValue();
 689
 690     const MipsAnalyzeImmediate::InstSeq &Seq =
 691       AnalyzeImm.Analyze(Imm, Size, false);
 692
 693     MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
 694     SDLoc DL(CN);
 695     SDNode *RegOpnd;
 696     SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
 697                                                 MVT::i64);
 698
 699     // The first instruction can be a LUi which is different from other
 700     // instructions (ADDiu, ORI and SLL) in that it does not have a register
 701     // operand.
 702     if (Inst->Opc == Mips::LUi64)
 703       RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
 704     else
 705       RegOpnd =
 706         CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
 707                                CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
 708                                ImmOpnd);
 709
 710     // The remaining instructions in the sequence are handled here.
 711     for (++Inst; Inst != Seq.end(); ++Inst) {
 712       ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
 713                                           MVT::i64);
 714       RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
 715                                        SDValue(RegOpnd, 0), ImmOpnd);
 716     }
 717
 718     return std::make_pair(true, RegOpnd);
 719   }
 720
 721   case ISD::INTRINSIC_W_CHAIN: {
 722     switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
 723     default:
 724       break;
 725
 726     case Intrinsic::mips_cfcmsa: {
 727       SDValue ChainIn = Node->getOperand(0);
 728       SDValue RegIdx = Node->getOperand(2);
 729       SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
 730                                            getMSACtrlReg(RegIdx), MVT::i32);
 731       return std::make_pair(true, Reg.getNode());
 732     }
 733     }
 734     break;
 735   }
 736
 737   case ISD::INTRINSIC_WO_CHAIN: {
 738     switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
 739     default:
 740       break;
 741
 742     case Intrinsic::mips_move_v:
 743       // Like an assignment but will always produce a move.v even if
 744       // unnecessary.
 745       return std::make_pair(true,
 746                             CurDAG->getMachineNode(Mips::MOVE_V, DL,
 747                                                    Node->getValueType(0),
 748                                                    Node->getOperand(1)));
 749     }
 750     break;
 751   }
 752
 753   case ISD::INTRINSIC_VOID: {
 754     switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
 755     default:
 756       break;
 757
 758     case Intrinsic::mips_ctcmsa: {
 759       SDValue ChainIn = Node->getOperand(0);
 760       SDValue RegIdx  = Node->getOperand(2);
 761       SDValue Value   = Node->getOperand(3);
 762       SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
 763                                               getMSACtrlReg(RegIdx), Value);
 764       return std::make_pair(true, ChainOut.getNode());
 765     }
 766     }
 767     break;
 768   }
 769
 770   case MipsISD::ThreadPointer: {
 771     EVT PtrVT = getTargetLowering()->getPointerTy();
 772     unsigned RdhwrOpc, DestReg;
 773
 774     if (PtrVT == MVT::i32) {
 775       RdhwrOpc = Mips::RDHWR;
 776       DestReg = Mips::V1;
 777     } else {
 778       RdhwrOpc = Mips::RDHWR64;
 779       DestReg = Mips::V1_64;
 780     }
 781
 782     SDNode *Rdhwr =
 783       CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node),
 784                              Node->getValueType(0),
 785                              CurDAG->getRegister(Mips::HWR29, MVT::i32));
 786     SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
 787                                          SDValue(Rdhwr, 0));
 788     SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
 789     ReplaceUses(SDValue(Node, 0), ResNode);
 790     return std::make_pair(true, ResNode.getNode());
 791   }
 792
 793   case ISD::BUILD_VECTOR: {
 794     // Select appropriate ldi.[bhwd] instructions for constant splats of
 795     // 128-bit when MSA is enabled. Fixup any register class mismatches that
 796     // occur as a result.
 797     //
 798     // This allows the compiler to use a wider range of immediates than would
 799     // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
 800     // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
 801     // 0x01010101 } without using a constant pool. This would be sub-optimal
 802     // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
 803     // same set/ of registers. Similarly, ldi.h isn't capable of producing {
 804     // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
 805
 806     BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
 807     APInt SplatValue, SplatUndef;
 808     unsigned SplatBitSize;
 809     bool HasAnyUndefs;
 810     unsigned LdiOp;
 811     EVT ResVecTy = BVN->getValueType(0);
 812     EVT ViaVecTy;
 813
 814     if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
 815       return std::make_pair(false, nullptr);
 816
 817     if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
 818                               HasAnyUndefs, 8,
 819                               !Subtarget->isLittle()))
 820       return std::make_pair(false, nullptr);
 821
 822     switch (SplatBitSize) {
 823     default:
 824       return std::make_pair(false, nullptr);
 825     case 8:
 826       LdiOp = Mips::LDI_B;
 827       ViaVecTy = MVT::v16i8;
 828       break;
 829     case 16:
 830       LdiOp = Mips::LDI_H;
 831       ViaVecTy = MVT::v8i16;
 832       break;
 833     case 32:
 834       LdiOp = Mips::LDI_W;
 835       ViaVecTy = MVT::v4i32;
 836       break;
 837     case 64:
 838       LdiOp = Mips::LDI_D;
 839       ViaVecTy = MVT::v2i64;
 840       break;
 841     }
 842
 843     if (!SplatValue.isSignedIntN(10))
 844       return std::make_pair(false, nullptr);
 845
 846     SDValue Imm = CurDAG->getTargetConstant(SplatValue,
 847                                             ViaVecTy.getVectorElementType());
 848
 849     SDNode *Res = CurDAG->getMachineNode(LdiOp, SDLoc(Node), ViaVecTy, Imm);
 850
 851     if (ResVecTy != ViaVecTy) {
 852       // If LdiOp is writing to a different register class to ResVecTy, then
 853       // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
 854       // since the source and destination register sets contain the same
 855       // registers.
 856       const TargetLowering *TLI = getTargetLowering();
 857       MVT ResVecTySimple = ResVecTy.getSimpleVT();
 858       const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
 859       Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, SDLoc(Node),
 860                                    ResVecTy, SDValue(Res, 0),
 861                                    CurDAG->getTargetConstant(RC->getID(),
 862                                                              MVT::i32));
 863     }
 864
 865     return std::make_pair(true, Res);
 866   }
 867
 868   }
 869
 870   return std::make_pair(false, nullptr);
 871 }
 872
 873 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
 874   return new MipsSEDAGToDAGISel(TM);
 875 }