src/llvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp

   1 //=======- NVPTXFrameLowering.cpp - NVPTX Frame Information ---*- C++ -*-=====//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the NVPTX implementation of TargetFrameLowering class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "NVPTXFrameLowering.h"
  15 #include "NVPTX.h"
  16 #include "NVPTXRegisterInfo.h"
  17 #include "NVPTXSubtarget.h"
  18 #include "NVPTXTargetMachine.h"
  19 #include "llvm/ADT/BitVector.h"
  20 #include "llvm/CodeGen/MachineFrameInfo.h"
  21 #include "llvm/CodeGen/MachineFunction.h"
  22 #include "llvm/CodeGen/MachineInstrBuilder.h"
  23 #include "llvm/CodeGen/MachineRegisterInfo.h"
  24 #include "llvm/MC/MachineLocation.h"
  25 #include "llvm/Target/TargetInstrInfo.h"
  26
  27 using namespace llvm;
  28
  29 NVPTXFrameLowering::NVPTXFrameLowering(NVPTXSubtarget &STI)
  30     : TargetFrameLowering(TargetFrameLowering::StackGrowsUp, 8, 0),
  31       is64bit(STI.is64Bit()) {}
  32
  33 bool NVPTXFrameLowering::hasFP(const MachineFunction &MF) const { return true; }
  34
  35 void NVPTXFrameLowering::emitPrologue(MachineFunction &MF) const {
  36   if (MF.getFrameInfo()->hasStackObjects()) {
  37     MachineBasicBlock &MBB = MF.front();
  38     // Insert "mov.u32 %SP, %Depot"
  39     MachineBasicBlock::iterator MBBI = MBB.begin();
  40     // This instruction really occurs before first instruction
  41     // in the BB, so giving it no debug location.
  42     DebugLoc dl = DebugLoc();
  43
  44     MachineRegisterInfo &MRI = MF.getRegInfo();
  45
  46     // mov %SPL, %depot;
  47     // cvta.local %SP, %SPL;
  48     if (is64bit) {
  49       unsigned LocalReg = MRI.createVirtualRegister(&NVPTX::Int64RegsRegClass);
  50       MachineInstr *MI =
  51           BuildMI(MBB, MBBI, dl, MF.getSubtarget().getInstrInfo()->get(
  52                                      NVPTX::cvta_local_yes_64),
  53                   NVPTX::VRFrame).addReg(LocalReg);
  54       BuildMI(MBB, MI, dl,
  55               MF.getSubtarget().getInstrInfo()->get(NVPTX::MOV_DEPOT_ADDR_64),
  56               LocalReg).addImm(MF.getFunctionNumber());
  57     } else {
  58       unsigned LocalReg = MRI.createVirtualRegister(&NVPTX::Int32RegsRegClass);
  59       MachineInstr *MI =
  60           BuildMI(MBB, MBBI, dl,
  61                   MF.getSubtarget().getInstrInfo()->get(NVPTX::cvta_local_yes),
  62                   NVPTX::VRFrame).addReg(LocalReg);
  63       BuildMI(MBB, MI, dl,
  64               MF.getSubtarget().getInstrInfo()->get(NVPTX::MOV_DEPOT_ADDR),
  65               LocalReg).addImm(MF.getFunctionNumber());
  66     }
  67   }
  68 }
  69
  70 void NVPTXFrameLowering::emitEpilogue(MachineFunction &MF,
  71                                       MachineBasicBlock &MBB) const {}
  72
  73 // This function eliminates ADJCALLSTACKDOWN,
  74 // ADJCALLSTACKUP pseudo instructions
  75 void NVPTXFrameLowering::eliminateCallFramePseudoInstr(
  76     MachineFunction &MF, MachineBasicBlock &MBB,
  77     MachineBasicBlock::iterator I) const {
  78   // Simply discard ADJCALLSTACKDOWN,
  79   // ADJCALLSTACKUP instructions.
  80   MBB.erase(I);
  81 }