src/llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp

   1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This class prints an PPC MCInst to a .s file.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "PPCInstPrinter.h"
  15 #include "MCTargetDesc/PPCMCTargetDesc.h"
  16 #include "MCTargetDesc/PPCPredicates.h"
  17 #include "llvm/MC/MCExpr.h"
  18 #include "llvm/MC/MCInst.h"
  19 #include "llvm/MC/MCInstrInfo.h"
  20 #include "llvm/MC/MCSymbol.h"
  21 #include "llvm/Support/CommandLine.h"
  22 #include "llvm/Support/raw_ostream.h"
  23 #include "llvm/Target/TargetOpcodes.h"
  24 using namespace llvm;
  25
  26 #define DEBUG_TYPE "asm-printer"
  27
  28 // FIXME: Once the integrated assembler supports full register names, tie this
  29 // to the verbose-asm setting.
  30 static cl::opt<bool>
  31 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
  32              cl::desc("Use full register names when printing assembly"));
  33
  34 #include "PPCGenAsmWriter.inc"
  35
  36 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
  37   OS << getRegisterName(RegNo);
  38 }
  39
  40 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
  41                                StringRef Annot) {
  42   // Check for slwi/srwi mnemonics.
  43   if (MI->getOpcode() == PPC::RLWINM) {
  44     unsigned char SH = MI->getOperand(2).getImm();
  45     unsigned char MB = MI->getOperand(3).getImm();
  46     unsigned char ME = MI->getOperand(4).getImm();
  47     bool useSubstituteMnemonic = false;
  48     if (SH <= 31 && MB == 0 && ME == (31-SH)) {
  49       O << "\tslwi "; useSubstituteMnemonic = true;
  50     }
  51     if (SH <= 31 && MB == (32-SH) && ME == 31) {
  52       O << "\tsrwi "; useSubstituteMnemonic = true;
  53       SH = 32-SH;
  54     }
  55     if (useSubstituteMnemonic) {
  56       printOperand(MI, 0, O);
  57       O << ", ";
  58       printOperand(MI, 1, O);
  59       O << ", " << (unsigned int)SH;
  60
  61       printAnnotation(O, Annot);
  62       return;
  63     }
  64   }
  65
  66   if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
  67       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
  68     O << "\tmr ";
  69     printOperand(MI, 0, O);
  70     O << ", ";
  71     printOperand(MI, 1, O);
  72     printAnnotation(O, Annot);
  73     return;
  74   }
  75
  76   if (MI->getOpcode() == PPC::RLDICR) {
  77     unsigned char SH = MI->getOperand(2).getImm();
  78     unsigned char ME = MI->getOperand(3).getImm();
  79     // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
  80     if (63-SH == ME) {
  81       O << "\tsldi ";
  82       printOperand(MI, 0, O);
  83       O << ", ";
  84       printOperand(MI, 1, O);
  85       O << ", " << (unsigned int)SH;
  86       printAnnotation(O, Annot);
  87       return;
  88     }
  89   }
  90
  91   // For fast-isel, a COPY_TO_REGCLASS may survive this long.  This is
  92   // used when converting a 32-bit float to a 64-bit float as part of
  93   // conversion to an integer (see PPCFastISel.cpp:SelectFPToI()),
  94   // as otherwise we have problems with incorrect register classes
  95   // in machine instruction verification.  For now, just avoid trying
  96   // to print it as such an instruction has no effect (a 32-bit float
  97   // in a register is already in 64-bit form, just with lower
  98   // precision).  FIXME: Is there a better solution?
  99   if (MI->getOpcode() == TargetOpcode::COPY_TO_REGCLASS)
 100     return;
 101
 102   printInstruction(MI, O);
 103   printAnnotation(O, Annot);
 104 }
 105
 106
 107 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
 108                                            raw_ostream &O,
 109                                            const char *Modifier) {
 110   unsigned Code = MI->getOperand(OpNo).getImm();
 111
 112   if (StringRef(Modifier) == "cc") {
 113     switch ((PPC::Predicate)Code) {
 114     case PPC::PRED_LT_MINUS:
 115     case PPC::PRED_LT_PLUS:
 116     case PPC::PRED_LT:
 117       O << "lt";
 118       return;
 119     case PPC::PRED_LE_MINUS:
 120     case PPC::PRED_LE_PLUS:
 121     case PPC::PRED_LE:
 122       O << "le";
 123       return;
 124     case PPC::PRED_EQ_MINUS:
 125     case PPC::PRED_EQ_PLUS:
 126     case PPC::PRED_EQ:
 127       O << "eq";
 128       return;
 129     case PPC::PRED_GE_MINUS:
 130     case PPC::PRED_GE_PLUS:
 131     case PPC::PRED_GE:
 132       O << "ge";
 133       return;
 134     case PPC::PRED_GT_MINUS:
 135     case PPC::PRED_GT_PLUS:
 136     case PPC::PRED_GT:
 137       O << "gt";
 138       return;
 139     case PPC::PRED_NE_MINUS:
 140     case PPC::PRED_NE_PLUS:
 141     case PPC::PRED_NE:
 142       O << "ne";
 143       return;
 144     case PPC::PRED_UN_MINUS:
 145     case PPC::PRED_UN_PLUS:
 146     case PPC::PRED_UN:
 147       O << "un";
 148       return;
 149     case PPC::PRED_NU_MINUS:
 150     case PPC::PRED_NU_PLUS:
 151     case PPC::PRED_NU:
 152       O << "nu";
 153       return;
 154     case PPC::PRED_BIT_SET:
 155     case PPC::PRED_BIT_UNSET:
 156       llvm_unreachable("Invalid use of bit predicate code");
 157     }
 158     llvm_unreachable("Invalid predicate code");
 159   }
 160
 161   if (StringRef(Modifier) == "pm") {
 162     switch ((PPC::Predicate)Code) {
 163     case PPC::PRED_LT:
 164     case PPC::PRED_LE:
 165     case PPC::PRED_EQ:
 166     case PPC::PRED_GE:
 167     case PPC::PRED_GT:
 168     case PPC::PRED_NE:
 169     case PPC::PRED_UN:
 170     case PPC::PRED_NU:
 171       return;
 172     case PPC::PRED_LT_MINUS:
 173     case PPC::PRED_LE_MINUS:
 174     case PPC::PRED_EQ_MINUS:
 175     case PPC::PRED_GE_MINUS:
 176     case PPC::PRED_GT_MINUS:
 177     case PPC::PRED_NE_MINUS:
 178     case PPC::PRED_UN_MINUS:
 179     case PPC::PRED_NU_MINUS:
 180       O << "-";
 181       return;
 182     case PPC::PRED_LT_PLUS:
 183     case PPC::PRED_LE_PLUS:
 184     case PPC::PRED_EQ_PLUS:
 185     case PPC::PRED_GE_PLUS:
 186     case PPC::PRED_GT_PLUS:
 187     case PPC::PRED_NE_PLUS:
 188     case PPC::PRED_UN_PLUS:
 189     case PPC::PRED_NU_PLUS:
 190       O << "+";
 191       return;
 192     case PPC::PRED_BIT_SET:
 193     case PPC::PRED_BIT_UNSET:
 194       llvm_unreachable("Invalid use of bit predicate code");
 195     }
 196     llvm_unreachable("Invalid predicate code");
 197   }
 198
 199   assert(StringRef(Modifier) == "reg" &&
 200          "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
 201   printOperand(MI, OpNo+1, O);
 202 }
 203
 204 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
 205                                        raw_ostream &O) {
 206   unsigned int Value = MI->getOperand(OpNo).getImm();
 207   assert(Value <= 3 && "Invalid u2imm argument!");
 208   O << (unsigned int)Value;
 209 }
 210
 211 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
 212                                        raw_ostream &O) {
 213   unsigned int Value = MI->getOperand(OpNo).getImm();
 214   assert(Value <= 15 && "Invalid u4imm argument!");
 215   O << (unsigned int)Value;
 216 }
 217
 218 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
 219                                        raw_ostream &O) {
 220   int Value = MI->getOperand(OpNo).getImm();
 221   Value = SignExtend32<5>(Value);
 222   O << (int)Value;
 223 }
 224
 225 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
 226                                        raw_ostream &O) {
 227   unsigned int Value = MI->getOperand(OpNo).getImm();
 228   assert(Value <= 31 && "Invalid u5imm argument!");
 229   O << (unsigned int)Value;
 230 }
 231
 232 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
 233                                        raw_ostream &O) {
 234   unsigned int Value = MI->getOperand(OpNo).getImm();
 235   assert(Value <= 63 && "Invalid u6imm argument!");
 236   O << (unsigned int)Value;
 237 }
 238
 239 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
 240                                         raw_ostream &O) {
 241   if (MI->getOperand(OpNo).isImm())
 242     O << (short)MI->getOperand(OpNo).getImm();
 243   else
 244     printOperand(MI, OpNo, O);
 245 }
 246
 247 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
 248                                         raw_ostream &O) {
 249   if (MI->getOperand(OpNo).isImm())
 250     O << (unsigned short)MI->getOperand(OpNo).getImm();
 251   else
 252     printOperand(MI, OpNo, O);
 253 }
 254
 255 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
 256                                         raw_ostream &O) {
 257   if (!MI->getOperand(OpNo).isImm())
 258     return printOperand(MI, OpNo, O);
 259
 260   // Branches can take an immediate operand.  This is used by the branch
 261   // selection pass to print .+8, an eight byte displacement from the PC.
 262   O << ".+";
 263   printAbsBranchOperand(MI, OpNo, O);
 264 }
 265
 266 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
 267                                            raw_ostream &O) {
 268   if (!MI->getOperand(OpNo).isImm())
 269     return printOperand(MI, OpNo, O);
 270
 271   O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
 272 }
 273
 274
 275 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
 276                                  raw_ostream &O) {
 277   unsigned CCReg = MI->getOperand(OpNo).getReg();
 278   unsigned RegNo;
 279   switch (CCReg) {
 280   default: llvm_unreachable("Unknown CR register");
 281   case PPC::CR0: RegNo = 0; break;
 282   case PPC::CR1: RegNo = 1; break;
 283   case PPC::CR2: RegNo = 2; break;
 284   case PPC::CR3: RegNo = 3; break;
 285   case PPC::CR4: RegNo = 4; break;
 286   case PPC::CR5: RegNo = 5; break;
 287   case PPC::CR6: RegNo = 6; break;
 288   case PPC::CR7: RegNo = 7; break;
 289   }
 290   O << (0x80 >> RegNo);
 291 }
 292
 293 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
 294                                     raw_ostream &O) {
 295   printS16ImmOperand(MI, OpNo, O);
 296   O << '(';
 297   if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
 298     O << "0";
 299   else
 300     printOperand(MI, OpNo+1, O);
 301   O << ')';
 302 }
 303
 304 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
 305                                     raw_ostream &O) {
 306   // When used as the base register, r0 reads constant zero rather than
 307   // the value contained in the register.  For this reason, the darwin
 308   // assembler requires that we print r0 as 0 (no r) when used as the base.
 309   if (MI->getOperand(OpNo).getReg() == PPC::R0)
 310     O << "0";
 311   else
 312     printOperand(MI, OpNo, O);
 313   O << ", ";
 314   printOperand(MI, OpNo+1, O);
 315 }
 316
 317 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
 318                                   raw_ostream &O) {
 319   // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
 320   // come at the _end_ of the expression.
 321   const MCOperand &Op = MI->getOperand(OpNo);
 322   const MCSymbolRefExpr &refExp = cast<MCSymbolRefExpr>(*Op.getExpr());
 323   O << refExp.getSymbol().getName();
 324   O << '(';
 325   printOperand(MI, OpNo+1, O);
 326   O << ')';
 327   if (refExp.getKind() != MCSymbolRefExpr::VK_None)
 328     O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
 329 }
 330
 331
 332 /// stripRegisterPrefix - This method strips the character prefix from a
 333 /// register name so that only the number is left.  Used by for linux asm.
 334 static const char *stripRegisterPrefix(const char *RegName) {
 335   if (FullRegNames)
 336     return RegName;
 337
 338   switch (RegName[0]) {
 339   case 'r':
 340   case 'f':
 341   case 'v':
 342     if (RegName[1] == 's')
 343       return RegName + 2;
 344     return RegName + 1;
 345   case 'c': if (RegName[1] == 'r') return RegName + 2;
 346   }
 347
 348   return RegName;
 349 }
 350
 351 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
 352                                   raw_ostream &O) {
 353   const MCOperand &Op = MI->getOperand(OpNo);
 354   if (Op.isReg()) {
 355     const char *RegName = getRegisterName(Op.getReg());
 356     // The linux and AIX assembler does not take register prefixes.
 357     if (!isDarwinSyntax())
 358       RegName = stripRegisterPrefix(RegName);
 359
 360     O << RegName;
 361     return;
 362   }
 363
 364   if (Op.isImm()) {
 365     O << Op.getImm();
 366     return;
 367   }
 368
 369   assert(Op.isExpr() && "unknown operand kind in printOperand");
 370   O << *Op.getExpr();
 371 }
 372