src/llvm/lib/Target/PowerPC/PPCCallingConv.td

   1 //===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This describes the calling conventions for the PowerPC 32- and 64-bit
  11 // architectures.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
  16 class CCIfSubtarget<string F, CCAction A>
  17     : CCIf<!strconcat("static_cast<const PPCSubtarget&>"
  18                        "(State.getMachineFunction().getSubtarget()).",
  19                      F),
  20           A>;
  21 class CCIfNotSubtarget<string F, CCAction A>
  22     : CCIf<!strconcat("!static_cast<const PPCSubtarget&>"
  23                        "(State.getMachineFunction().getSubtarget()).",
  24                      F),
  25           A>;
  26
  27 //===----------------------------------------------------------------------===//
  28 // Return Value Calling Convention
  29 //===----------------------------------------------------------------------===//
  30
  31 // PPC64 AnyReg return-value convention. No explicit register is specified for
  32 // the return-value. The register allocator is allowed and expected to choose
  33 // any free register.
  34 //
  35 // This calling convention is currently only supported by the stackmap and
  36 // patchpoint intrinsics. All other uses will result in an assert on Debug
  37 // builds. On Release builds we fallback to the PPC C calling convention.
  38 def RetCC_PPC64_AnyReg : CallingConv<[
  39   CCCustom<"CC_PPC_AnyReg_Error">
  40 ]>;
  41
  42 // Return-value convention for PowerPC
  43 def RetCC_PPC : CallingConv<[
  44   CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>,
  45
  46   // On PPC64, integer return values are always promoted to i64
  47   CCIfType<[i32, i1], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,
  48   CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>,
  49
  50   CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
  51   CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
  52   CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
  53
  54   // Floating point types returned as "direct" go into F1 .. F8; note that
  55   // only the ELFv2 ABI fully utilizes all these registers.
  56   CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
  57   CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
  58
  59   // Vector types returned as "direct" go into V2 .. V9; note that only the
  60   // ELFv2 ABI fully utilizes all these registers.
  61   CCIfType<[v16i8, v8i16, v4i32, v4f32],
  62            CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>,
  63   CCIfType<[v2f64, v2i64],
  64            CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9]>>
  65 ]>;
  66
  67 // No explicit register is specified for the AnyReg calling convention. The
  68 // register allocator may assign the arguments to any free register.
  69 //
  70 // This calling convention is currently only supported by the stackmap and
  71 // patchpoint intrinsics. All other uses will result in an assert on Debug
  72 // builds. On Release builds we fallback to the PPC C calling convention.
  73 def CC_PPC64_AnyReg : CallingConv<[
  74   CCCustom<"CC_PPC_AnyReg_Error">
  75 ]>;
  76
  77 // Note that we don't currently have calling conventions for 64-bit
  78 // PowerPC, but handle all the complexities of the ABI in the lowering
  79 // logic.  FIXME: See if the logic can be simplified with use of CCs.
  80 // This may require some extensions to current table generation.
  81
  82 // Simple calling convention for 64-bit ELF PowerPC fast isel.
  83 // Only handle ints and floats.  All ints are promoted to i64.
  84 // Vector types and quadword ints are not handled.
  85 def CC_PPC64_ELF_FIS : CallingConv<[
  86   CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_PPC64_AnyReg>>,
  87
  88   CCIfType<[i1],  CCPromoteToType<i64>>,
  89   CCIfType<[i8],  CCPromoteToType<i64>>,
  90   CCIfType<[i16], CCPromoteToType<i64>>,
  91   CCIfType<[i32], CCPromoteToType<i64>>,
  92   CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
  93   CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>
  94 ]>;
  95
  96 // Simple return-value convention for 64-bit ELF PowerPC fast isel.
  97 // All small ints are promoted to i64.  Vector types, quadword ints,
  98 // and multiple register returns are "supported" to avoid compile
  99 // errors, but none are handled by the fast selector.
 100 def RetCC_PPC64_ELF_FIS : CallingConv<[
 101   CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>,
 102
 103   CCIfType<[i1],   CCPromoteToType<i64>>,
 104   CCIfType<[i8],   CCPromoteToType<i64>>,
 105   CCIfType<[i16],  CCPromoteToType<i64>>,
 106   CCIfType<[i32],  CCPromoteToType<i64>>,
 107   CCIfType<[i64],  CCAssignToReg<[X3, X4]>>,
 108   CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
 109   CCIfType<[f32],  CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
 110   CCIfType<[f64],  CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
 111   CCIfType<[v16i8, v8i16, v4i32, v4f32],
 112            CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>,
 113   CCIfType<[v2f64, v2i64],
 114            CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9]>>
 115 ]>;
 116
 117 //===----------------------------------------------------------------------===//
 118 // PowerPC System V Release 4 32-bit ABI
 119 //===----------------------------------------------------------------------===//
 120
 121 def CC_PPC32_SVR4_Common : CallingConv<[
 122   CCIfType<[i1], CCPromoteToType<i32>>,
 123
 124   // The ABI requires i64 to be passed in two adjacent registers with the first
 125   // register having an odd register number.
 126   CCIfType<[i32], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>,
 127
 128   // The first 8 integer arguments are passed in integer registers.
 129   CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
 130
 131   // Make sure the i64 words from a long double are either both passed in
 132   // registers or both passed on the stack.
 133   CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>,
 134
 135   // FP values are passed in F1 - F8.
 136   CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
 137
 138   // Split arguments have an alignment of 8 bytes on the stack.
 139   CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>,
 140
 141   CCIfType<[i32], CCAssignToStack<4, 4>>,
 142
 143   // Floats are stored in double precision format, thus they have the same
 144   // alignment and size as doubles.
 145   CCIfType<[f32,f64], CCAssignToStack<8, 8>>,
 146
 147   // Vectors get 16-byte stack slots that are 16-byte aligned.
 148   CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>
 149 ]>;
 150
 151 // This calling convention puts vector arguments always on the stack. It is used
 152 // to assign vector arguments which belong to the variable portion of the
 153 // parameter list of a variable argument function.
 154 def CC_PPC32_SVR4_VarArg : CallingConv<[
 155   CCDelegateTo<CC_PPC32_SVR4_Common>
 156 ]>;
 157
 158 // In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to
 159 // put vector arguments in vector registers before putting them on the stack.
 160 def CC_PPC32_SVR4 : CallingConv<[
 161   // The first 12 Vector arguments are passed in AltiVec registers.
 162   CCIfType<[v16i8, v8i16, v4i32, v4f32],
 163            CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>,
 164   CCIfType<[v2f64, v2i64],
 165            CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9,
 166                           VSH10, VSH11, VSH12, VSH13]>>,
 167
 168   CCDelegateTo<CC_PPC32_SVR4_Common>
 169 ]>;
 170
 171 // Helper "calling convention" to handle aggregate by value arguments.
 172 // Aggregate by value arguments are always placed in the local variable space
 173 // of the caller. This calling convention is only used to assign those stack
 174 // offsets in the callers stack frame.
 175 //
 176 // Still, the address of the aggregate copy in the callers stack frame is passed
 177 // in a GPR (or in the parameter list area if all GPRs are allocated) from the
 178 // caller to the callee. The location for the address argument is assigned by
 179 // the CC_PPC32_SVR4 calling convention.
 180 //
 181 // The only purpose of CC_PPC32_SVR4_Custom_Dummy is to skip arguments which are
 182 // not passed by value.
 183
 184 def CC_PPC32_SVR4_ByVal : CallingConv<[
 185   CCIfByVal<CCPassByVal<4, 4>>,
 186
 187   CCCustom<"CC_PPC32_SVR4_Custom_Dummy">
 188 ]>;
 189
 190 def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
 191                                        V28, V29, V30, V31)>;
 192
 193 def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
 194                                         R21, R22, R23, R24, R25, R26, R27, R28,
 195                                         R29, R30, R31, F14, F15, F16, F17, F18,
 196                                         F19, F20, F21, F22, F23, F24, F25, F26,
 197                                         F27, F28, F29, F30, F31, CR2, CR3, CR4
 198                                    )>;
 199
 200 def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>;
 201
 202 def CSR_SVR432   : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
 203                                         R21, R22, R23, R24, R25, R26, R27, R28,
 204                                         R29, R30, R31, F14, F15, F16, F17, F18,
 205                                         F19, F20, F21, F22, F23, F24, F25, F26,
 206                                         F27, F28, F29, F30, F31, CR2, CR3, CR4
 207                                    )>;
 208
 209 def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
 210
 211 def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
 212                                         X21, X22, X23, X24, X25, X26, X27, X28,
 213                                         X29, X30, X31, F14, F15, F16, F17, F18,
 214                                         F19, F20, F21, F22, F23, F24, F25, F26,
 215                                         F27, F28, F29, F30, F31, CR2, CR3, CR4
 216                                    )>;
 217
 218 def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>;
 219
 220 def CSR_SVR464   : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
 221                                         X21, X22, X23, X24, X25, X26, X27, X28,
 222                                         X29, X30, X31, F14, F15, F16, F17, F18,
 223                                         F19, F20, F21, F22, F23, F24, F25, F26,
 224                                         F27, F28, F29, F30, F31, CR2, CR3, CR4
 225                                    )>;
 226
 227
 228 def CSR_SVR464_Altivec : CalleeSavedRegs<(add CSR_SVR464, CSR_Altivec)>;
 229
 230 def CSR_NoRegs : CalleeSavedRegs<(add)>;
 231
 232 def CSR_64_AllRegs: CalleeSavedRegs<(add X0, (sequence "X%u", 3, 10),
 233                                              (sequence "X%u", 14, 31),
 234                                              (sequence "F%u", 0, 31),
 235                                              (sequence "CR%u", 0, 7))>;
 236
 237 def CSR_64_AllRegs_Altivec : CalleeSavedRegs<(add CSR_64_AllRegs,
 238                                              (sequence "V%u", 0, 31))>;
 239
 240 def CSR_64_AllRegs_VSX : CalleeSavedRegs<(add CSR_64_AllRegs_Altivec,
 241                                          (sequence "VSL%u", 0, 31),
 242                                          (sequence "VSH%u", 0, 31))>;
 243