src/llvm/lib/Target/PowerPC/PPCInstrAltivec.td

   1 //===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the Altivec extension to the PowerPC instruction set.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // Altivec transformation functions and pattern fragments.
  16 //
  17
  18 // Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be
  19 // of that type.
  20 def vnot_ppc : PatFrag<(ops node:$in),
  21                        (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>;
  22
  23 def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
  24                               (vector_shuffle node:$lhs, node:$rhs), [{
  25   return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);
  26 }]>;
  27 def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
  28                               (vector_shuffle node:$lhs, node:$rhs), [{
  29   return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);
  30 }]>;
  31 def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
  32                                     (vector_shuffle node:$lhs, node:$rhs), [{
  33   return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
  34 }]>;
  35 def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
  36                                     (vector_shuffle node:$lhs, node:$rhs), [{
  37   return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
  38 }]>;
  39
  40 // These fragments are provided for little-endian, where the inputs must be
  41 // swapped for correct semantics.
  42 def vpkuhum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
  43                                       (vector_shuffle node:$lhs, node:$rhs), [{
  44   return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);
  45 }]>;
  46 def vpkuwum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
  47                                       (vector_shuffle node:$lhs, node:$rhs), [{
  48   return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);
  49 }]>;
  50
  51 def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
  52                              (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
  53   return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
  54 }]>;
  55 def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
  56                              (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
  57   return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
  58 }]>;
  59 def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
  60                              (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
  61   return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
  62 }]>;
  63 def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
  64                              (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
  65   return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
  66 }]>;
  67 def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
  68                              (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
  69   return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
  70 }]>;
  71 def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
  72                              (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
  73   return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
  74 }]>;
  75
  76
  77 def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
  78                                (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
  79   return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
  80 }]>;
  81 def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
  82                                    (vector_shuffle node:$lhs, node:$rhs), [{
  83   return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
  84 }]>;
  85 def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
  86                                    (vector_shuffle node:$lhs, node:$rhs), [{
  87   return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
  88 }]>;
  89 def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
  90                                    (vector_shuffle node:$lhs, node:$rhs), [{
  91   return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
  92 }]>;
  93 def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
  94                                    (vector_shuffle node:$lhs, node:$rhs), [{
  95   return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
  96 }]>;
  97 def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
  98                                    (vector_shuffle node:$lhs, node:$rhs), [{
  99   return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
 100 }]>;
 101
 102
 103 // These fragments are provided for little-endian, where the inputs must be
 104 // swapped for correct semantics.
 105 def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
 106                                (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
 107   return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
 108 }]>;
 109 def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
 110                                    (vector_shuffle node:$lhs, node:$rhs), [{
 111   return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
 112 }]>;
 113 def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
 114                                    (vector_shuffle node:$lhs, node:$rhs), [{
 115   return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
 116 }]>;
 117 def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
 118                                    (vector_shuffle node:$lhs, node:$rhs), [{
 119   return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
 120 }]>;
 121 def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
 122                                    (vector_shuffle node:$lhs, node:$rhs), [{
 123   return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
 124 }]>;
 125 def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
 126                                    (vector_shuffle node:$lhs, node:$rhs), [{
 127   return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
 128 }]>;
 129
 130
 131 def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{
 132   return getI32Imm(PPC::isVSLDOIShuffleMask(N, 0, *CurDAG));
 133 }]>;
 134 def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
 135                              (vector_shuffle node:$lhs, node:$rhs), [{
 136   return PPC::isVSLDOIShuffleMask(N, 0, *CurDAG) != -1;
 137 }], VSLDOI_get_imm>;
 138
 139
 140 /// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
 141 /// vector_shuffle(X,undef,mask) by the dag combiner.
 142 def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{
 143   return getI32Imm(PPC::isVSLDOIShuffleMask(N, 1, *CurDAG));
 144 }]>;
 145 def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
 146                                    (vector_shuffle node:$lhs, node:$rhs), [{
 147   return PPC::isVSLDOIShuffleMask(N, 1, *CurDAG) != -1;
 148 }], VSLDOI_unary_get_imm>;
 149
 150
 151 /// VSLDOI_swapped* - These fragments are provided for little-endian, where
 152 /// the inputs must be swapped for correct semantics.
 153 def VSLDOI_swapped_get_imm : SDNodeXForm<vector_shuffle, [{
 154   return getI32Imm(PPC::isVSLDOIShuffleMask(N, 2, *CurDAG));
 155 }]>;
 156 def vsldoi_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
 157                                      (vector_shuffle node:$lhs, node:$rhs), [{
 158   return PPC::isVSLDOIShuffleMask(N, 2, *CurDAG) != -1;
 159 }], VSLDOI_get_imm>;
 160
 161
 162 // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
 163 def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{
 164   return getI32Imm(PPC::getVSPLTImmediate(N, 1, *CurDAG));
 165 }]>;
 166 def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
 167                              (vector_shuffle node:$lhs, node:$rhs), [{
 168   return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
 169 }], VSPLTB_get_imm>;
 170 def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{
 171   return getI32Imm(PPC::getVSPLTImmediate(N, 2, *CurDAG));
 172 }]>;
 173 def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
 174                              (vector_shuffle node:$lhs, node:$rhs), [{
 175   return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
 176 }], VSPLTH_get_imm>;
 177 def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{
 178   return getI32Imm(PPC::getVSPLTImmediate(N, 4, *CurDAG));
 179 }]>;
 180 def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
 181                              (vector_shuffle node:$lhs, node:$rhs), [{
 182   return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);
 183 }], VSPLTW_get_imm>;
 184
 185
 186 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
 187 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
 188   return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
 189 }]>;
 190 def vecspltisb : PatLeaf<(build_vector), [{
 191   return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0;
 192 }], VSPLTISB_get_imm>;
 193
 194 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
 195 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
 196   return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
 197 }]>;
 198 def vecspltish : PatLeaf<(build_vector), [{
 199   return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0;
 200 }], VSPLTISH_get_imm>;
 201
 202 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
 203 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
 204   return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
 205 }]>;
 206 def vecspltisw : PatLeaf<(build_vector), [{
 207   return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0;
 208 }], VSPLTISW_get_imm>;
 209
 210 //===----------------------------------------------------------------------===//
 211 // Helpers for defining instructions that directly correspond to intrinsics.
 212
 213 // VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type.
 214 class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
 215   : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
 216               !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
 217                        [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>;
 218
 219 // VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the
 220 // inputs doesn't match the type of the output.
 221 class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
 222                    ValueType InTy>
 223   : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
 224               !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
 225                        [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>;
 226
 227 // VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two
 228 // input types and an output type.
 229 class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
 230                    ValueType In1Ty, ValueType In2Ty>
 231   : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
 232               !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
 233                        [(set OutTy:$vD,
 234                          (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>;
 235
 236 // VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type.
 237 class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
 238   : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 239              !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
 240              [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>;
 241
 242 // VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the
 243 // inputs doesn't match the type of the output.
 244 class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
 245                   ValueType InTy>
 246   : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 247              !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
 248              [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>;
 249
 250 // VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two
 251 // input types and an output type.
 252 class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
 253                   ValueType In1Ty, ValueType In2Ty>
 254   : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 255              !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
 256              [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>;
 257
 258 // VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type.
 259 class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID>
 260   : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
 261              !strconcat(opc, " $vD, $vB"), IIC_VecFP,
 262              [(set v4f32:$vD, (IntID v4f32:$vB))]>;
 263
 264 // VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the
 265 // inputs doesn't match the type of the output.
 266 class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
 267                   ValueType InTy>
 268   : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
 269              !strconcat(opc, " $vD, $vB"), IIC_VecFP,
 270              [(set OutTy:$vD, (IntID InTy:$vB))]>;
 271
 272 //===----------------------------------------------------------------------===//
 273 // Instruction Definitions.
 274
 275 def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">;
 276 let Predicates = [HasAltivec] in {
 277
 278 def DSS      : DSS_Form<0, 822, (outs), (ins u5imm:$STRM),
 279                         "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>,
 280                         Deprecated<DeprecatedDST> {
 281   let A = 0;
 282   let B = 0;
 283 }
 284
 285 def DSSALL   : DSS_Form<1, 822, (outs), (ins),
 286                         "dssall", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dssall)]>,
 287                         Deprecated<DeprecatedDST> {
 288   let STRM = 0;
 289   let A = 0;
 290   let B = 0;
 291 }
 292
 293 def DST      : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
 294                         "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
 295                         [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>,
 296                         Deprecated<DeprecatedDST>;
 297
 298 def DSTT     : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
 299                         "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
 300                         [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>,
 301                         Deprecated<DeprecatedDST>;
 302
 303 def DSTST    : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
 304                         "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
 305                         [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>,
 306                         Deprecated<DeprecatedDST>;
 307
 308 def DSTSTT   : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
 309                         "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
 310                         [(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>,
 311                         Deprecated<DeprecatedDST>;
 312
 313 let isCodeGenOnly = 1 in {
 314   // The very same instructions as above, but formally matching 64bit registers.
 315   def DST64    : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
 316                           "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
 317                           [(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>,
 318                           Deprecated<DeprecatedDST>;
 319
 320   def DSTT64   : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
 321                           "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
 322                           [(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>,
 323                           Deprecated<DeprecatedDST>;
 324
 325   def DSTST64  : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
 326                           "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
 327                           [(int_ppc_altivec_dstst i64:$rA, i32:$rB,
 328                                                   imm:$STRM)]>,
 329                           Deprecated<DeprecatedDST>;
 330
 331   def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
 332                           "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
 333                           [(int_ppc_altivec_dststt i64:$rA, i32:$rB,
 334                                                    imm:$STRM)]>,
 335                           Deprecated<DeprecatedDST>;
 336 }
 337
 338 def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins),
 339                       "mfvscr $vD", IIC_LdStStore,
 340                       [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>;
 341 def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB),
 342                       "mtvscr $vB", IIC_LdStLoad,
 343                       [(int_ppc_altivec_mtvscr v4i32:$vB)]>;
 344
 345 let canFoldAsLoad = 1, PPC970_Unit = 2 in {  // Loads.
 346 def LVEBX: XForm_1<31,   7, (outs vrrc:$vD), (ins memrr:$src),
 347                    "lvebx $vD, $src", IIC_LdStLoad,
 348                    [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
 349 def LVEHX: XForm_1<31,  39, (outs vrrc:$vD), (ins memrr:$src),
 350                    "lvehx $vD, $src", IIC_LdStLoad,
 351                    [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
 352 def LVEWX: XForm_1<31,  71, (outs vrrc:$vD), (ins memrr:$src),
 353                    "lvewx $vD, $src", IIC_LdStLoad,
 354                    [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
 355 def LVX  : XForm_1<31, 103, (outs vrrc:$vD), (ins memrr:$src),
 356                    "lvx $vD, $src", IIC_LdStLoad,
 357                    [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
 358 def LVXL : XForm_1<31, 359, (outs vrrc:$vD), (ins memrr:$src),
 359                    "lvxl $vD, $src", IIC_LdStLoad,
 360                    [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
 361 }
 362
 363 def LVSL : XForm_1<31,   6, (outs vrrc:$vD), (ins memrr:$src),
 364                    "lvsl $vD, $src", IIC_LdStLoad,
 365                    [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
 366                    PPC970_Unit_LSU;
 367 def LVSR : XForm_1<31,  38, (outs vrrc:$vD), (ins memrr:$src),
 368                    "lvsr $vD, $src", IIC_LdStLoad,
 369                    [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
 370                    PPC970_Unit_LSU;
 371
 372 let PPC970_Unit = 2 in {   // Stores.
 373 def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst),
 374                    "stvebx $rS, $dst", IIC_LdStStore,
 375                    [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>;
 376 def STVEHX: XForm_8<31, 167, (outs), (ins vrrc:$rS, memrr:$dst),
 377                    "stvehx $rS, $dst", IIC_LdStStore,
 378                    [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>;
 379 def STVEWX: XForm_8<31, 199, (outs), (ins vrrc:$rS, memrr:$dst),
 380                    "stvewx $rS, $dst", IIC_LdStStore,
 381                    [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>;
 382 def STVX  : XForm_8<31, 231, (outs), (ins vrrc:$rS, memrr:$dst),
 383                    "stvx $rS, $dst", IIC_LdStStore,
 384                    [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>;
 385 def STVXL : XForm_8<31, 487, (outs), (ins vrrc:$rS, memrr:$dst),
 386                    "stvxl $rS, $dst", IIC_LdStStore,
 387                    [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>;
 388 }
 389
 390 let PPC970_Unit = 5 in {  // VALU Operations.
 391 // VA-Form instructions.  3-input AltiVec ops.
 392 let isCommutable = 1 in {
 393 def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
 394                        "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP,
 395                        [(set v4f32:$vD,
 396                         (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>;
 397
 398 // FIXME: The fma+fneg pattern won't match because fneg is not legal.
 399 def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
 400                        "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP,
 401                        [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC,
 402                                                   (fneg v4f32:$vB))))]>;
 403
 404 def VMHADDSHS  : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>;
 405 def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs,
 406                              v8i16>;
 407 def VMLADDUHM  : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>;
 408 } // isCommutable
 409
 410 def VPERM      : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm,
 411                               v4i32, v4i32, v16i8>;
 412 def VSEL       : VA1a_Int_Ty<42, "vsel",  int_ppc_altivec_vsel, v4i32>;
 413
 414 // Shuffles.
 415 def VSLDOI  : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u5imm:$SH),
 416                        "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP,
 417                        [(set v16i8:$vD,
 418                          (vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>;
 419
 420 // VX-Form instructions.  AltiVec arithmetic ops.
 421 let isCommutable = 1 in {
 422 def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 423                       "vaddfp $vD, $vA, $vB", IIC_VecFP,
 424                       [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>;
 425
 426 def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 427                       "vaddubm $vD, $vA, $vB", IIC_VecGeneral,
 428                       [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>;
 429 def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 430                       "vadduhm $vD, $vA, $vB", IIC_VecGeneral,
 431                       [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>;
 432 def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 433                       "vadduwm $vD, $vA, $vB", IIC_VecGeneral,
 434                       [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>;
 435
 436 def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>;
 437 def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>;
 438 def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>;
 439 def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>;
 440 def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>;
 441 def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>;
 442 def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>;
 443 } // isCommutable
 444
 445 let isCommutable = 1 in
 446 def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 447                     "vand $vD, $vA, $vB", IIC_VecFP,
 448                     [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>;
 449 def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 450                      "vandc $vD, $vA, $vB", IIC_VecFP,
 451                      [(set v4i32:$vD, (and v4i32:$vA,
 452                                            (vnot_ppc v4i32:$vB)))]>;
 453
 454 def VCFSX  : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
 455                       "vcfsx $vD, $vB, $UIMM", IIC_VecFP,
 456                       [(set v4f32:$vD,
 457                              (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>;
 458 def VCFUX  : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
 459                       "vcfux $vD, $vB, $UIMM", IIC_VecFP,
 460                       [(set v4f32:$vD,
 461                              (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>;
 462 def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
 463                       "vctsxs $vD, $vB, $UIMM", IIC_VecFP,
 464                       [(set v4i32:$vD,
 465                              (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>;
 466 def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
 467                       "vctuxs $vD, $vB, $UIMM", IIC_VecFP,
 468                       [(set v4i32:$vD,
 469                              (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>;
 470
 471 // Defines with the UIM field set to 0 for floating-point
 472 // to integer (fp_to_sint/fp_to_uint) conversions and integer
 473 // to floating-point (sint_to_fp/uint_to_fp) conversions.
 474 let isCodeGenOnly = 1, VA = 0 in {
 475 def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB),
 476                        "vcfsx $vD, $vB, 0", IIC_VecFP,
 477                        [(set v4f32:$vD,
 478                              (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>;
 479 def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB),
 480                         "vctuxs $vD, $vB, 0", IIC_VecFP,
 481                         [(set v4i32:$vD,
 482                                (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>;
 483 def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB),
 484                        "vcfux $vD, $vB, 0", IIC_VecFP,
 485                        [(set v4f32:$vD,
 486                                (int_ppc_altivec_vcfux v4i32:$vB, 0))]>;
 487 def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB),
 488                       "vctsxs $vD, $vB, 0", IIC_VecFP,
 489                       [(set v4i32:$vD,
 490                              (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>;
 491 }
 492 def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>;
 493 def VLOGEFP  : VX2_Int_SP<458, "vlogefp",  int_ppc_altivec_vlogefp>;
 494
 495 let isCommutable = 1 in {
 496 def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>;
 497 def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>;
 498 def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>;
 499 def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>;
 500 def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>;
 501 def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>;
 502
 503 def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>;
 504 def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>;
 505 def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>;
 506 def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>;
 507 def VMAXUB : VX1_Int_Ty<   2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>;
 508 def VMAXUH : VX1_Int_Ty<  66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>;
 509 def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>;
 510 def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>;
 511 def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>;
 512 def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>;
 513 def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>;
 514 def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>;
 515 def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>;
 516 def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>;
 517 } // isCommutable
 518
 519 def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 520                       "vmrghb $vD, $vA, $vB", IIC_VecFP,
 521                       [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>;
 522 def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 523                       "vmrghh $vD, $vA, $vB", IIC_VecFP,
 524                       [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>;
 525 def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 526                       "vmrghw $vD, $vA, $vB", IIC_VecFP,
 527                       [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>;
 528 def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 529                       "vmrglb $vD, $vA, $vB", IIC_VecFP,
 530                       [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>;
 531 def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 532                       "vmrglh $vD, $vA, $vB", IIC_VecFP,
 533                       [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>;
 534 def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 535                       "vmrglw $vD, $vA, $vB", IIC_VecFP,
 536                       [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>;
 537
 538 def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm,
 539                             v4i32, v16i8, v4i32>;
 540 def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm,
 541                             v4i32, v8i16, v4i32>;
 542 def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs,
 543                             v4i32, v8i16, v4i32>;
 544 def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm,
 545                             v4i32, v16i8, v4i32>;
 546 def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm,
 547                             v4i32, v8i16, v4i32>;
 548 def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs,
 549                             v4i32, v8i16, v4i32>;
 550
 551 let isCommutable = 1 in {
 552 def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb,
 553                           v8i16, v16i8>;
 554 def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh,
 555                           v4i32, v8i16>;
 556 def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub,
 557                           v8i16, v16i8>;
 558 def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh,
 559                           v4i32, v8i16>;
 560 def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb,
 561                           v8i16, v16i8>;
 562 def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh,
 563                           v4i32, v8i16>;
 564 def VMULOUB : VX1_Int_Ty2<  8, "vmuloub", int_ppc_altivec_vmuloub,
 565                           v8i16, v16i8>;
 566 def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh,
 567                           v4i32, v8i16>;
 568 } // isCommutable
 569
 570 def VREFP     : VX2_Int_SP<266, "vrefp",     int_ppc_altivec_vrefp>;
 571 def VRFIM     : VX2_Int_SP<714, "vrfim",     int_ppc_altivec_vrfim>;
 572 def VRFIN     : VX2_Int_SP<522, "vrfin",     int_ppc_altivec_vrfin>;
 573 def VRFIP     : VX2_Int_SP<650, "vrfip",     int_ppc_altivec_vrfip>;
 574 def VRFIZ     : VX2_Int_SP<586, "vrfiz",     int_ppc_altivec_vrfiz>;
 575 def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
 576
 577 def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>;
 578
 579 def VSUBFP  : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 580                       "vsubfp $vD, $vA, $vB", IIC_VecGeneral,
 581                       [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>;
 582 def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 583                       "vsububm $vD, $vA, $vB", IIC_VecGeneral,
 584                       [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>;
 585 def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 586                       "vsubuhm $vD, $vA, $vB", IIC_VecGeneral,
 587                       [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>;
 588 def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 589                       "vsubuwm $vD, $vA, $vB", IIC_VecGeneral,
 590                       [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>;
 591
 592 def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>;
 593 def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>;
 594 def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>;
 595 def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>;
 596 def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>;
 597 def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>;
 598
 599 def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>;
 600 def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>;
 601
 602 def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs,
 603                           v4i32, v16i8, v4i32>;
 604 def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs,
 605                           v4i32, v8i16, v4i32>;
 606 def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs,
 607                           v4i32, v16i8, v4i32>;
 608
 609 def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 610                     "vnor $vD, $vA, $vB", IIC_VecFP,
 611                     [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA,
 612                                                    v4i32:$vB)))]>;
 613 let isCommutable = 1 in {
 614 def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 615                       "vor $vD, $vA, $vB", IIC_VecFP,
 616                       [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>;
 617 def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 618                       "vxor $vD, $vA, $vB", IIC_VecFP,
 619                       [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>;
 620 } // isCommutable
 621
 622 def VRLB   : VX1_Int_Ty<   4, "vrlb", int_ppc_altivec_vrlb, v16i8>;
 623 def VRLH   : VX1_Int_Ty<  68, "vrlh", int_ppc_altivec_vrlh, v8i16>;
 624 def VRLW   : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>;
 625
 626 def VSL    : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl,  v4i32 >;
 627 def VSLO   : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>;
 628
 629 def VSLB   : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>;
 630 def VSLH   : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>;
 631 def VSLW   : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>;
 632
 633 def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
 634                       "vspltb $vD, $vB, $UIMM", IIC_VecPerm,
 635                       [(set v16i8:$vD,
 636                         (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>;
 637 def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
 638                       "vsplth $vD, $vB, $UIMM", IIC_VecPerm,
 639                       [(set v16i8:$vD,
 640                         (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>;
 641 def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
 642                       "vspltw $vD, $vB, $UIMM", IIC_VecPerm,
 643                       [(set v16i8:$vD,
 644                         (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>;
 645
 646 def VSR    : VX1_Int_Ty< 708, "vsr"  , int_ppc_altivec_vsr,  v4i32>;
 647 def VSRO   : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>;
 648
 649 def VSRAB  : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>;
 650 def VSRAH  : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>;
 651 def VSRAW  : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>;
 652 def VSRB   : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>;
 653 def VSRH   : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>;
 654 def VSRW   : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>;
 655
 656
 657 def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM),
 658                        "vspltisb $vD, $SIMM", IIC_VecPerm,
 659                        [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>;
 660 def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM),
 661                        "vspltish $vD, $SIMM", IIC_VecPerm,
 662                        [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>;
 663 def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM),
 664                        "vspltisw $vD, $SIMM", IIC_VecPerm,
 665                        [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>;
 666
 667 // Vector Pack.
 668 def VPKPX   : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx,
 669                           v8i16, v4i32>;
 670 def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss,
 671                           v16i8, v8i16>;
 672 def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus,
 673                           v16i8, v8i16>;
 674 def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss,
 675                           v16i8, v4i32>;
 676 def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus,
 677                           v8i16, v4i32>;
 678 def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 679                        "vpkuhum $vD, $vA, $vB", IIC_VecFP,
 680                        [(set v16i8:$vD,
 681                          (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>;
 682 def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus,
 683                           v16i8, v8i16>;
 684 def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
 685                        "vpkuwum $vD, $vA, $vB", IIC_VecFP,
 686                        [(set v16i8:$vD,
 687                          (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>;
 688 def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus,
 689                           v8i16, v4i32>;
 690
 691 // Vector Unpack.
 692 def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx,
 693                           v4i32, v8i16>;
 694 def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb,
 695                           v8i16, v16i8>;
 696 def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh,
 697                           v4i32, v8i16>;
 698 def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx,
 699                           v4i32, v8i16>;
 700 def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb,
 701                           v8i16, v16i8>;
 702 def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh,
 703                           v4i32, v8i16>;
 704
 705
 706 // Altivec Comparisons.
 707
 708 class VCMP<bits<10> xo, string asmstr, ValueType Ty>
 709   : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
 710               IIC_VecFPCompare,
 711               [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>;
 712 class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
 713   : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
 714               IIC_VecFPCompare,
 715               [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> {
 716   let Defs = [CR6];
 717   let RC = 1;
 718 }
 719
 720 // f32 element comparisons.0
 721 def VCMPBFP   : VCMP <966, "vcmpbfp $vD, $vA, $vB"  , v4f32>;
 722 def VCMPBFPo  : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
 723 def VCMPEQFP  : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
 724 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
 725 def VCMPGEFP  : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
 726 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
 727 def VCMPGTFP  : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
 728 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
 729
 730 // i8 element comparisons.
 731 def VCMPEQUB  : VCMP <  6, "vcmpequb $vD, $vA, $vB" , v16i8>;
 732 def VCMPEQUBo : VCMPo<  6, "vcmpequb. $vD, $vA, $vB", v16i8>;
 733 def VCMPGTSB  : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
 734 def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
 735 def VCMPGTUB  : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
 736 def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
 737
 738 // i16 element comparisons.
 739 def VCMPEQUH  : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
 740 def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
 741 def VCMPGTSH  : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
 742 def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
 743 def VCMPGTUH  : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
 744 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
 745
 746 // i32 element comparisons.
 747 def VCMPEQUW  : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
 748 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
 749 def VCMPGTSW  : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
 750 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
 751 def VCMPGTUW  : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
 752 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
 753
 754 let isCodeGenOnly = 1 in {
 755 def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
 756                       "vxor $vD, $vD, $vD", IIC_VecFP,
 757                       [(set v16i8:$vD, (v16i8 immAllZerosV))]>;
 758 def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
 759                       "vxor $vD, $vD, $vD", IIC_VecFP,
 760                       [(set v8i16:$vD, (v8i16 immAllZerosV))]>;
 761 def V_SET0  : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
 762                       "vxor $vD, $vD, $vD", IIC_VecFP,
 763                       [(set v4i32:$vD, (v4i32 immAllZerosV))]>;
 764
 765 let IMM=-1 in {
 766 def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins),
 767                       "vspltisw $vD, -1", IIC_VecFP,
 768                       [(set v16i8:$vD, (v16i8 immAllOnesV))]>;
 769 def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins),
 770                       "vspltisw $vD, -1", IIC_VecFP,
 771                       [(set v8i16:$vD, (v8i16 immAllOnesV))]>;
 772 def V_SETALLONES  : VXForm_3<908, (outs vrrc:$vD), (ins),
 773                       "vspltisw $vD, -1", IIC_VecFP,
 774                       [(set v4i32:$vD, (v4i32 immAllOnesV))]>;
 775 }
 776 }
 777 } // VALU Operations.
 778
 779 //===----------------------------------------------------------------------===//
 780 // Additional Altivec Patterns
 781 //
 782
 783 // Loads.
 784 def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
 785
 786 // Stores.
 787 def : Pat<(store v4i32:$rS, xoaddr:$dst),
 788           (STVX $rS, xoaddr:$dst)>;
 789
 790 // Bit conversions.
 791 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
 792 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
 793 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
 794
 795 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
 796 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
 797 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
 798
 799 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
 800 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
 801 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
 802
 803 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
 804 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
 805 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
 806
 807 // Shuffles.
 808
 809 // Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)
 810 def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef),
 811         (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>;
 812 def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef),
 813         (VPKUWUM $vA, $vA)>;
 814 def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef),
 815         (VPKUHUM $vA, $vA)>;
 816
 817 // Match vsldoi(y,x), vpkuwum(y,x), vpkuhum(y,x), i.e., swapped operands.
 818 // These fragments are matched for little-endian, where the inputs must
 819 // be swapped for correct semantics.
 820 def:Pat<(vsldoi_swapped_shuffle:$in v16i8:$vA, v16i8:$vB),
 821         (VSLDOI $vB, $vA, (VSLDOI_swapped_get_imm $in))>;
 822 def:Pat<(vpkuwum_swapped_shuffle v16i8:$vA, v16i8:$vB),
 823         (VPKUWUM $vB, $vA)>;
 824 def:Pat<(vpkuhum_swapped_shuffle v16i8:$vA, v16i8:$vB),
 825         (VPKUHUM $vB, $vA)>;
 826
 827 // Match vmrg*(x,x)
 828 def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef),
 829         (VMRGLB $vA, $vA)>;
 830 def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef),
 831         (VMRGLH $vA, $vA)>;
 832 def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef),
 833         (VMRGLW $vA, $vA)>;
 834 def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef),
 835         (VMRGHB $vA, $vA)>;
 836 def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef),
 837         (VMRGHH $vA, $vA)>;
 838 def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef),
 839         (VMRGHW $vA, $vA)>;
 840
 841 // Match vmrg*(y,x), i.e., swapped operands.  These fragments
 842 // are matched for little-endian, where the inputs must be
 843 // swapped for correct semantics.
 844 def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB),
 845         (VMRGLB $vB, $vA)>;
 846 def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB),
 847         (VMRGLH $vB, $vA)>;
 848 def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB),
 849         (VMRGLW $vB, $vA)>;
 850 def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB),
 851         (VMRGHB $vB, $vA)>;
 852 def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB),
 853         (VMRGHH $vB, $vA)>;
 854 def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB),
 855         (VMRGHW $vB, $vA)>;
 856
 857 // Logical Operations
 858 def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>;
 859
 860 def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)),
 861           (VNOR $A, $B)>;
 862 def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)),
 863           (VANDC $A, $B)>;
 864
 865 def : Pat<(fmul v4f32:$vA, v4f32:$vB),
 866           (VMADDFP $vA, $vB,
 867              (v4i32 (VSLW (V_SETALLONES), (V_SETALLONES))))>;
 868
 869 // Fused multiply add and multiply sub for packed float.  These are represented
 870 // separately from the real instructions above, for operations that must have
 871 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
 872 def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
 873           (VMADDFP $A, $B, $C)>;
 874 def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
 875           (VNMSUBFP $A, $B, $C)>;
 876
 877 def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
 878           (VMADDFP $A, $B, $C)>;
 879 def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
 880           (VNMSUBFP $A, $B, $C)>;
 881
 882 def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC),
 883           (VPERM $vA, $vB, $vC)>;
 884
 885 def : Pat<(PPCfre v4f32:$A), (VREFP $A)>;
 886 def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>;
 887
 888 // Vector shifts
 889 def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)),
 890           (v16i8 (VSLB $vA, $vB))>;
 891 def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)),
 892           (v8i16 (VSLH $vA, $vB))>;
 893 def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)),
 894           (v4i32 (VSLW $vA, $vB))>;
 895
 896 def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)),
 897           (v16i8 (VSRB $vA, $vB))>;
 898 def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)),
 899           (v8i16 (VSRH $vA, $vB))>;
 900 def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)),
 901           (v4i32 (VSRW $vA, $vB))>;
 902
 903 def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)),
 904           (v16i8 (VSRAB $vA, $vB))>;
 905 def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)),
 906           (v8i16 (VSRAH $vA, $vB))>;
 907 def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)),
 908           (v4i32 (VSRAW $vA, $vB))>;
 909
 910 // Float to integer and integer to float conversions
 911 def : Pat<(v4i32 (fp_to_sint v4f32:$vA)),
 912            (VCTSXS_0 $vA)>;
 913 def : Pat<(v4i32 (fp_to_uint v4f32:$vA)),
 914            (VCTUXS_0 $vA)>;
 915 def : Pat<(v4f32 (sint_to_fp v4i32:$vA)),
 916            (VCFSX_0 $vA)>;
 917 def : Pat<(v4f32 (uint_to_fp v4i32:$vA)),
 918            (VCFUX_0 $vA)>;
 919
 920 // Floating-point rounding
 921 def : Pat<(v4f32 (ffloor v4f32:$vA)),
 922           (VRFIM $vA)>;
 923 def : Pat<(v4f32 (fceil v4f32:$vA)),
 924           (VRFIP $vA)>;
 925 def : Pat<(v4f32 (ftrunc v4f32:$vA)),
 926           (VRFIZ $vA)>;
 927 def : Pat<(v4f32 (fnearbyint v4f32:$vA)),
 928           (VRFIN $vA)>;
 929
 930 } // end HasAltivec
 931