src/llvm/lib/Target/R600/AMDGPUInstructions.td

   1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains instruction defs that are common to all hw codegen
  11 // targets.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
  16   field bit isRegisterLoad = 0;
  17   field bit isRegisterStore = 0;
  18
  19   let Namespace = "AMDGPU";
  20   let OutOperandList = outs;
  21   let InOperandList = ins;
  22   let AsmString = asm;
  23   let Pattern = pattern;
  24   let Itinerary = NullALU;
  25
  26   let isCodeGenOnly = 1;
  27
  28   let TSFlags{63} = isRegisterLoad;
  29   let TSFlags{62} = isRegisterStore;
  30 }
  31
  32 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
  33     : AMDGPUInst<outs, ins, asm, pattern> {
  34
  35   field bits<32> Inst = 0xffffffff;
  36
  37 }
  38
  39 def FP32Denormals : Predicate<"Subtarget.hasFP32Denormals()">;
  40 def FP64Denormals : Predicate<"Subtarget.hasFP64Denormals()">;
  41 def UnsafeFPMath : Predicate<"TM.Options.UnsafeFPMath">;
  42
  43 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
  44 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
  45
  46 let OperandType = "OPERAND_IMMEDIATE" in {
  47
  48 def u32imm : Operand<i32> {
  49   let PrintMethod = "printU32ImmOperand";
  50 }
  51
  52 def u16imm : Operand<i16> {
  53   let PrintMethod = "printU16ImmOperand";
  54 }
  55
  56 def u8imm : Operand<i8> {
  57   let PrintMethod = "printU8ImmOperand";
  58 }
  59
  60 } // End OperandType = "OPERAND_IMMEDIATE"
  61
  62 //===--------------------------------------------------------------------===//
  63 // Custom Operands
  64 //===--------------------------------------------------------------------===//
  65 def brtarget   : Operand<OtherVT>;
  66
  67 //===----------------------------------------------------------------------===//
  68 // PatLeafs for floating-point comparisons
  69 //===----------------------------------------------------------------------===//
  70
  71 def COND_OEQ : PatLeaf <
  72   (cond),
  73   [{return N->get() == ISD::SETOEQ || N->get() == ISD::SETEQ;}]
  74 >;
  75
  76 def COND_ONE : PatLeaf <
  77   (cond),
  78   [{return N->get() == ISD::SETONE || N->get() == ISD::SETNE;}]
  79 >;
  80
  81 def COND_OGT : PatLeaf <
  82   (cond),
  83   [{return N->get() == ISD::SETOGT || N->get() == ISD::SETGT;}]
  84 >;
  85
  86 def COND_OGE : PatLeaf <
  87   (cond),
  88   [{return N->get() == ISD::SETOGE || N->get() == ISD::SETGE;}]
  89 >;
  90
  91 def COND_OLT : PatLeaf <
  92   (cond),
  93   [{return N->get() == ISD::SETOLT || N->get() == ISD::SETLT;}]
  94 >;
  95
  96 def COND_OLE : PatLeaf <
  97   (cond),
  98   [{return N->get() == ISD::SETOLE || N->get() == ISD::SETLE;}]
  99 >;
 100
 101
 102 def COND_O : PatLeaf <(cond), [{return N->get() == ISD::SETO;}]>;
 103 def COND_UO : PatLeaf <(cond), [{return N->get() == ISD::SETUO;}]>;
 104
 105 //===----------------------------------------------------------------------===//
 106 // PatLeafs for unsigned / unordered comparisons
 107 //===----------------------------------------------------------------------===//
 108
 109 def COND_UEQ : PatLeaf <(cond), [{return N->get() == ISD::SETUEQ;}]>;
 110 def COND_UNE : PatLeaf <(cond), [{return N->get() == ISD::SETUNE;}]>;
 111 def COND_UGT : PatLeaf <(cond), [{return N->get() == ISD::SETUGT;}]>;
 112 def COND_UGE : PatLeaf <(cond), [{return N->get() == ISD::SETUGE;}]>;
 113 def COND_ULT : PatLeaf <(cond), [{return N->get() == ISD::SETULT;}]>;
 114 def COND_ULE : PatLeaf <(cond), [{return N->get() == ISD::SETULE;}]>;
 115
 116 // XXX - For some reason R600 version is preferring to use unordered
 117 // for setne?
 118 def COND_UNE_NE : PatLeaf <
 119   (cond),
 120   [{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
 121 >;
 122
 123 //===----------------------------------------------------------------------===//
 124 // PatLeafs for signed comparisons
 125 //===----------------------------------------------------------------------===//
 126
 127 def COND_SGT : PatLeaf <(cond), [{return N->get() == ISD::SETGT;}]>;
 128 def COND_SGE : PatLeaf <(cond), [{return N->get() == ISD::SETGE;}]>;
 129 def COND_SLT : PatLeaf <(cond), [{return N->get() == ISD::SETLT;}]>;
 130 def COND_SLE : PatLeaf <(cond), [{return N->get() == ISD::SETLE;}]>;
 131
 132 //===----------------------------------------------------------------------===//
 133 // PatLeafs for integer equality
 134 //===----------------------------------------------------------------------===//
 135
 136 def COND_EQ : PatLeaf <
 137   (cond),
 138   [{return N->get() == ISD::SETEQ || N->get() == ISD::SETUEQ;}]
 139 >;
 140
 141 def COND_NE : PatLeaf <
 142   (cond),
 143   [{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}]
 144 >;
 145
 146 def COND_NULL : PatLeaf <
 147   (cond),
 148   [{(void)N; return false;}]
 149 >;
 150
 151 //===----------------------------------------------------------------------===//
 152 // Load/Store Pattern Fragments
 153 //===----------------------------------------------------------------------===//
 154
 155 class PrivateMemOp <dag ops, dag frag> : PatFrag <ops, frag, [{
 156   return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
 157 }]>;
 158
 159 class PrivateLoad <SDPatternOperator op> : PrivateMemOp <
 160   (ops node:$ptr), (op node:$ptr)
 161 >;
 162
 163 class PrivateStore <SDPatternOperator op> : PrivateMemOp <
 164   (ops node:$value, node:$ptr), (op node:$value, node:$ptr)
 165 >;
 166
 167 def extloadi8_private : PrivateLoad <extloadi8>;
 168 def sextloadi8_private : PrivateLoad <sextloadi8>;
 169 def extloadi16_private : PrivateLoad <extloadi16>;
 170 def sextloadi16_private : PrivateLoad <sextloadi16>;
 171 def load_private : PrivateLoad <load>;
 172
 173 def truncstorei8_private : PrivateStore <truncstorei8>;
 174 def truncstorei16_private : PrivateStore <truncstorei16>;
 175 def store_private : PrivateStore <store>;
 176
 177 def global_store : PatFrag<(ops node:$val, node:$ptr),
 178     (store node:$val, node:$ptr), [{
 179         return isGlobalStore(dyn_cast<StoreSDNode>(N));
 180 }]>;
 181
 182 // Global address space loads
 183 def global_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 184     return isGlobalLoad(dyn_cast<LoadSDNode>(N));
 185 }]>;
 186
 187 // Constant address space loads
 188 def constant_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 189     return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
 190 }]>;
 191
 192 def az_extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
 193   LoadSDNode *L = cast<LoadSDNode>(N);
 194   return L->getExtensionType() == ISD::ZEXTLOAD ||
 195          L->getExtensionType() == ISD::EXTLOAD;
 196 }]>;
 197
 198 def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
 199   return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
 200 }]>;
 201
 202 def az_extloadi8_global : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
 203     return isGlobalLoad(dyn_cast<LoadSDNode>(N));
 204 }]>;
 205
 206 def sextloadi8_global : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
 207     return isGlobalLoad(dyn_cast<LoadSDNode>(N));
 208 }]>;
 209
 210 def az_extloadi8_flat : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
 211     return isFlatLoad(dyn_cast<LoadSDNode>(N));
 212 }]>;
 213
 214 def sextloadi8_flat : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
 215     return isFlatLoad(dyn_cast<LoadSDNode>(N));
 216 }]>;
 217
 218 def az_extloadi8_constant : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
 219     return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
 220 }]>;
 221
 222 def sextloadi8_constant : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
 223     return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
 224 }]>;
 225
 226 def az_extloadi8_local : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
 227     return isLocalLoad(dyn_cast<LoadSDNode>(N));
 228 }]>;
 229
 230 def sextloadi8_local : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
 231     return isLocalLoad(dyn_cast<LoadSDNode>(N));
 232 }]>;
 233
 234 def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
 235   return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
 236 }]>;
 237
 238 def az_extloadi16_global : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
 239     return isGlobalLoad(dyn_cast<LoadSDNode>(N));
 240 }]>;
 241
 242 def sextloadi16_global : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
 243     return isGlobalLoad(dyn_cast<LoadSDNode>(N));
 244 }]>;
 245
 246 def az_extloadi16_flat : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
 247     return isFlatLoad(dyn_cast<LoadSDNode>(N));
 248 }]>;
 249
 250 def sextloadi16_flat : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
 251     return isFlatLoad(dyn_cast<LoadSDNode>(N));
 252 }]>;
 253
 254 def az_extloadi16_constant : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
 255     return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
 256 }]>;
 257
 258 def sextloadi16_constant : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
 259     return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
 260 }]>;
 261
 262 def az_extloadi16_local : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
 263     return isLocalLoad(dyn_cast<LoadSDNode>(N));
 264 }]>;
 265
 266 def sextloadi16_local : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
 267     return isLocalLoad(dyn_cast<LoadSDNode>(N));
 268 }]>;
 269
 270 def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
 271   return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
 272 }]>;
 273
 274 def az_extloadi32_global : PatFrag<(ops node:$ptr),
 275                                    (az_extloadi32 node:$ptr), [{
 276   return isGlobalLoad(dyn_cast<LoadSDNode>(N));
 277 }]>;
 278
 279 def az_extloadi32_flat : PatFrag<(ops node:$ptr),
 280                                    (az_extloadi32 node:$ptr), [{
 281   return isFlatLoad(dyn_cast<LoadSDNode>(N));
 282 }]>;
 283
 284 def az_extloadi32_constant : PatFrag<(ops node:$ptr),
 285                                      (az_extloadi32 node:$ptr), [{
 286   return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
 287 }]>;
 288
 289 def truncstorei8_global : PatFrag<(ops node:$val, node:$ptr),
 290                                   (truncstorei8 node:$val, node:$ptr), [{
 291   return isGlobalStore(dyn_cast<StoreSDNode>(N));
 292 }]>;
 293
 294 def truncstorei16_global : PatFrag<(ops node:$val, node:$ptr),
 295                                   (truncstorei16 node:$val, node:$ptr), [{
 296   return isGlobalStore(dyn_cast<StoreSDNode>(N));
 297 }]>;
 298
 299 def truncstorei8_flat : PatFrag<(ops node:$val, node:$ptr),
 300                                   (truncstorei8 node:$val, node:$ptr), [{
 301   return isFlatStore(dyn_cast<StoreSDNode>(N));
 302 }]>;
 303
 304 def truncstorei16_flat : PatFrag<(ops node:$val, node:$ptr),
 305                                   (truncstorei16 node:$val, node:$ptr), [{
 306   return isFlatStore(dyn_cast<StoreSDNode>(N));
 307 }]>;
 308
 309 def local_store : PatFrag<(ops node:$val, node:$ptr),
 310                              (store node:$val, node:$ptr), [{
 311   return isLocalStore(dyn_cast<StoreSDNode>(N));
 312 }]>;
 313
 314 def truncstorei8_local : PatFrag<(ops node:$val, node:$ptr),
 315                                   (truncstorei8 node:$val, node:$ptr), [{
 316   return isLocalStore(dyn_cast<StoreSDNode>(N));
 317 }]>;
 318
 319 def truncstorei16_local : PatFrag<(ops node:$val, node:$ptr),
 320                                   (truncstorei16 node:$val, node:$ptr), [{
 321   return isLocalStore(dyn_cast<StoreSDNode>(N));
 322 }]>;
 323
 324 def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 325     return isLocalLoad(dyn_cast<LoadSDNode>(N));
 326 }]>;
 327
 328 class Aligned8Bytes <dag ops, dag frag> : PatFrag <ops, frag, [{
 329     return cast<MemSDNode>(N)->getAlignment() % 8 == 0;
 330 }]>;
 331
 332 def local_load_aligned8bytes : Aligned8Bytes <
 333   (ops node:$ptr), (local_load node:$ptr)
 334 >;
 335
 336 def local_store_aligned8bytes : Aligned8Bytes <
 337   (ops node:$val, node:$ptr), (local_store node:$val, node:$ptr)
 338 >;
 339
 340 class local_binary_atomic_op<SDNode atomic_op> :
 341   PatFrag<(ops node:$ptr, node:$value),
 342     (atomic_op node:$ptr, node:$value), [{
 343   return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
 344 }]>;
 345
 346
 347 def atomic_swap_local : local_binary_atomic_op<atomic_swap>;
 348 def atomic_load_add_local : local_binary_atomic_op<atomic_load_add>;
 349 def atomic_load_sub_local : local_binary_atomic_op<atomic_load_sub>;
 350 def atomic_load_and_local : local_binary_atomic_op<atomic_load_and>;
 351 def atomic_load_or_local : local_binary_atomic_op<atomic_load_or>;
 352 def atomic_load_xor_local : local_binary_atomic_op<atomic_load_xor>;
 353 def atomic_load_nand_local : local_binary_atomic_op<atomic_load_nand>;
 354 def atomic_load_min_local : local_binary_atomic_op<atomic_load_min>;
 355 def atomic_load_max_local : local_binary_atomic_op<atomic_load_max>;
 356 def atomic_load_umin_local : local_binary_atomic_op<atomic_load_umin>;
 357 def atomic_load_umax_local : local_binary_atomic_op<atomic_load_umax>;
 358
 359 def mskor_global : PatFrag<(ops node:$val, node:$ptr),
 360                             (AMDGPUstore_mskor node:$val, node:$ptr), [{
 361   return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
 362 }]>;
 363
 364
 365 def atomic_cmp_swap_32_local :
 366   PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
 367           (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
 368   AtomicSDNode *AN = cast<AtomicSDNode>(N);
 369   return AN->getMemoryVT() == MVT::i32 &&
 370          AN->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
 371 }]>;
 372
 373 def atomic_cmp_swap_64_local :
 374   PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
 375           (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
 376   AtomicSDNode *AN = cast<AtomicSDNode>(N);
 377   return AN->getMemoryVT() == MVT::i64 &&
 378          AN->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
 379 }]>;
 380
 381 def flat_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 382     return isFlatLoad(dyn_cast<LoadSDNode>(N));
 383 }]>;
 384
 385 def flat_store : PatFrag<(ops node:$val, node:$ptr),
 386                          (store node:$val, node:$ptr), [{
 387   return isFlatStore(dyn_cast<StoreSDNode>(N));
 388 }]>;
 389
 390 def mskor_flat : PatFrag<(ops node:$val, node:$ptr),
 391                             (AMDGPUstore_mskor node:$val, node:$ptr), [{
 392   return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::FLAT_ADDRESS;
 393 }]>;
 394
 395 class global_binary_atomic_op<SDNode atomic_op> : PatFrag<
 396   (ops node:$ptr, node:$value),
 397   (atomic_op node:$ptr, node:$value),
 398   [{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;}]
 399 >;
 400
 401 def atomic_swap_global : global_binary_atomic_op<atomic_swap>;
 402 def atomic_add_global : global_binary_atomic_op<atomic_load_add>;
 403 def atomic_and_global : global_binary_atomic_op<atomic_load_and>;
 404 def atomic_max_global : global_binary_atomic_op<atomic_load_max>;
 405 def atomic_min_global : global_binary_atomic_op<atomic_load_min>;
 406 def atomic_or_global : global_binary_atomic_op<atomic_load_or>;
 407 def atomic_sub_global : global_binary_atomic_op<atomic_load_sub>;
 408 def atomic_umax_global : global_binary_atomic_op<atomic_load_umax>;
 409 def atomic_umin_global : global_binary_atomic_op<atomic_load_umin>;
 410 def atomic_xor_global : global_binary_atomic_op<atomic_load_xor>;
 411
 412 //===----------------------------------------------------------------------===//
 413 // Misc Pattern Fragments
 414 //===----------------------------------------------------------------------===//
 415
 416 def fmad : PatFrag <
 417   (ops node:$src0, node:$src1, node:$src2),
 418   (fadd (fmul node:$src0, node:$src1), node:$src2)
 419 >;
 420
 421 class Constants {
 422 int TWO_PI = 0x40c90fdb;
 423 int PI = 0x40490fdb;
 424 int TWO_PI_INV = 0x3e22f983;
 425 int FP_UINT_MAX_PLUS_1 = 0x4f800000;    // 1 << 32 in floating point encoding
 426 int FP32_NEG_ONE = 0xbf800000;
 427 int FP32_ONE = 0x3f800000;
 428 }
 429 def CONST : Constants;
 430
 431 def FP_ZERO : PatLeaf <
 432   (fpimm),
 433   [{return N->getValueAPF().isZero();}]
 434 >;
 435
 436 def FP_ONE : PatLeaf <
 437   (fpimm),
 438   [{return N->isExactlyValue(1.0);}]
 439 >;
 440
 441 let isCodeGenOnly = 1, isPseudo = 1 in {
 442
 443 let usesCustomInserter = 1  in {
 444
 445 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
 446   (outs rc:$dst),
 447   (ins rc:$src0),
 448   "CLAMP $dst, $src0",
 449   [(set f32:$dst, (AMDGPUclamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
 450 >;
 451
 452 class FABS <RegisterClass rc> : AMDGPUShaderInst <
 453   (outs rc:$dst),
 454   (ins rc:$src0),
 455   "FABS $dst, $src0",
 456   [(set f32:$dst, (fabs f32:$src0))]
 457 >;
 458
 459 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
 460   (outs rc:$dst),
 461   (ins rc:$src0),
 462   "FNEG $dst, $src0",
 463   [(set f32:$dst, (fneg f32:$src0))]
 464 >;
 465
 466 } // usesCustomInserter = 1
 467
 468 multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
 469                     ComplexPattern addrPat> {
 470 let UseNamedOperandTable = 1 in {
 471
 472   def RegisterLoad : AMDGPUShaderInst <
 473     (outs dstClass:$dst),
 474     (ins addrClass:$addr, i32imm:$chan),
 475     "RegisterLoad $dst, $addr",
 476     [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]
 477   > {
 478     let isRegisterLoad = 1;
 479   }
 480
 481   def RegisterStore : AMDGPUShaderInst <
 482     (outs),
 483     (ins dstClass:$val, addrClass:$addr, i32imm:$chan),
 484     "RegisterStore $val, $addr",
 485     [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]
 486   > {
 487     let isRegisterStore = 1;
 488   }
 489 }
 490 }
 491
 492 } // End isCodeGenOnly = 1, isPseudo = 1
 493
 494 /* Generic helper patterns for intrinsics */
 495 /* -------------------------------------- */
 496
 497 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
 498   : Pat <
 499   (fpow f32:$src0, f32:$src1),
 500   (exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
 501 >;
 502
 503 /* Other helper patterns */
 504 /* --------------------- */
 505
 506 /* Extract element pattern */
 507 class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
 508                        SubRegIndex sub_reg>
 509   : Pat<
 510   (sub_type (vector_extract vec_type:$src, sub_idx)),
 511   (EXTRACT_SUBREG $src, sub_reg)
 512 >;
 513
 514 /* Insert element pattern */
 515 class Insert_Element <ValueType elem_type, ValueType vec_type,
 516                       int sub_idx, SubRegIndex sub_reg>
 517   : Pat <
 518   (vector_insert vec_type:$vec, elem_type:$elem, sub_idx),
 519   (INSERT_SUBREG $vec, $elem, sub_reg)
 520 >;
 521
 522 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
 523 // can handle COPY instructions.
 524 // bitconvert pattern
 525 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
 526   (dt (bitconvert (st rc:$src0))),
 527   (dt rc:$src0)
 528 >;
 529
 530 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
 531 // can handle COPY instructions.
 532 class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
 533   (vt (AMDGPUdwordaddr (vt rc:$addr))),
 534   (vt rc:$addr)
 535 >;
 536
 537 // BFI_INT patterns
 538
 539 multiclass BFIPatterns <Instruction BFI_INT,
 540                         Instruction LoadImm32,
 541                         RegisterClass RC64> {
 542   // Definition from ISA doc:
 543   // (y & x) | (z & ~x)
 544   def : Pat <
 545     (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
 546     (BFI_INT $x, $y, $z)
 547   >;
 548
 549   // SHA-256 Ch function
 550   // z ^ (x & (y ^ z))
 551   def : Pat <
 552     (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
 553     (BFI_INT $x, $y, $z)
 554   >;
 555
 556   def : Pat <
 557     (fcopysign f32:$src0, f32:$src1),
 558     (BFI_INT (LoadImm32 0x7fffffff), $src0, $src1)
 559   >;
 560
 561   def : Pat <
 562     (f64 (fcopysign f64:$src0, f64:$src1)),
 563     (REG_SEQUENCE RC64,
 564       (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
 565       (BFI_INT (LoadImm32 0x7fffffff),
 566                (i32 (EXTRACT_SUBREG $src0, sub1)),
 567                (i32 (EXTRACT_SUBREG $src1, sub1))), sub1)
 568   >;
 569 }
 570
 571 // SHA-256 Ma patterns
 572
 573 // ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
 574 class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
 575   (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
 576   (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
 577 >;
 578
 579 // Bitfield extract patterns
 580
 581 /*
 582
 583 XXX: The BFE pattern is not working correctly because the XForm is not being
 584 applied.
 585
 586 def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>;
 587 def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}],
 588                             SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>;
 589
 590 class BFEPattern <Instruction BFE> : Pat <
 591   (and (srl i32:$x, legalshift32:$y), bfemask:$z),
 592   (BFE $x, $y, $z)
 593 >;
 594
 595 */
 596
 597 // rotr pattern
 598 class ROTRPattern <Instruction BIT_ALIGN> : Pat <
 599   (rotr i32:$src0, i32:$src1),
 600   (BIT_ALIGN $src0, $src0, $src1)
 601 >;
 602
 603 // 24-bit arithmetic patterns
 604 def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
 605
 606 /*
 607 class UMUL24Pattern <Instruction UMUL24> : Pat <
 608   (mul U24:$x, U24:$y),
 609   (UMUL24 $x, $y)
 610 >;
 611 */
 612
 613 class IMad24Pat<Instruction Inst> : Pat <
 614   (add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2),
 615   (Inst $src0, $src1, $src2)
 616 >;
 617
 618 class UMad24Pat<Instruction Inst> : Pat <
 619   (add (AMDGPUmul_u24 i32:$src0, i32:$src1), i32:$src2),
 620   (Inst $src0, $src1, $src2)
 621 >;
 622
 623 multiclass Expand24IBitOps<Instruction MulInst, Instruction AddInst> {
 624   def _expand_imad24 : Pat <
 625     (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2),
 626     (AddInst (MulInst $src0, $src1), $src2)
 627   >;
 628
 629   def _expand_imul24 : Pat <
 630     (AMDGPUmul_i24 i32:$src0, i32:$src1),
 631     (MulInst $src0, $src1)
 632   >;
 633 }
 634
 635 multiclass Expand24UBitOps<Instruction MulInst, Instruction AddInst> {
 636   def _expand_umad24 : Pat <
 637     (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2),
 638     (AddInst (MulInst $src0, $src1), $src2)
 639   >;
 640
 641   def _expand_umul24 : Pat <
 642     (AMDGPUmul_u24 i32:$src0, i32:$src1),
 643     (MulInst $src0, $src1)
 644   >;
 645 }
 646
 647 class RcpPat<Instruction RcpInst, ValueType vt> : Pat <
 648   (fdiv FP_ONE, vt:$src),
 649   (RcpInst $src)
 650 >;
 651
 652 multiclass RsqPat<Instruction RsqInst, ValueType vt> {
 653   def : Pat <
 654     (fdiv FP_ONE, (fsqrt vt:$src)),
 655     (RsqInst $src)
 656   >;
 657
 658   def : Pat <
 659     (AMDGPUrcp (fsqrt vt:$src)),
 660     (RsqInst $src)
 661   >;
 662 }
 663
 664 include "R600Instructions.td"
 665 include "R700Instructions.td"
 666 include "EvergreenInstructions.td"
 667 include "CaymanInstructions.td"
 668
 669 include "SIInstrInfo.td"
 670