src/llvm/lib/Target/R600/AMDGPUSubtarget.h

   1 //=====-- AMDGPUSubtarget.h - Define Subtarget for the AMDIL ---*- C++ -*-====//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //==-----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 /// \brief AMDGPU specific subclass of TargetSubtarget.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
  16 #define LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
  17 #include "AMDGPU.h"
  18 #include "AMDGPUFrameLowering.h"
  19 #include "AMDGPUInstrInfo.h"
  20 #include "AMDGPUIntrinsicInfo.h"
  21 #include "AMDGPUSubtarget.h"
  22 #include "R600ISelLowering.h"
  23 #include "llvm/ADT/StringExtras.h"
  24 #include "llvm/ADT/StringRef.h"
  25 #include "llvm/IR/DataLayout.h"
  26 #include "llvm/Target/TargetSubtargetInfo.h"
  27
  28 #define GET_SUBTARGETINFO_HEADER
  29 #include "AMDGPUGenSubtargetInfo.inc"
  30
  31 namespace llvm {
  32
  33 class SIMachineFunctionInfo;
  34
  35 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
  36
  37 public:
  38   enum Generation {
  39     R600 = 0,
  40     R700,
  41     EVERGREEN,
  42     NORTHERN_ISLANDS,
  43     SOUTHERN_ISLANDS,
  44     SEA_ISLANDS,
  45     VOLCANIC_ISLANDS,
  46   };
  47
  48 private:
  49   std::string DevName;
  50   bool Is64bit;
  51   bool DumpCode;
  52   bool R600ALUInst;
  53   bool HasVertexCache;
  54   short TexVTXClauseSize;
  55   Generation Gen;
  56   bool FP64;
  57   bool FP64Denormals;
  58   bool FP32Denormals;
  59   bool CaymanISA;
  60   bool FlatAddressSpace;
  61   bool EnableIRStructurizer;
  62   bool EnablePromoteAlloca;
  63   bool EnableIfCvt;
  64   bool EnableLoadStoreOpt;
  65   unsigned WavefrontSize;
  66   bool CFALUBug;
  67   int LocalMemorySize;
  68   bool EnableVGPRSpilling;
  69
  70   const DataLayout DL;
  71   AMDGPUFrameLowering FrameLowering;
  72   std::unique_ptr<AMDGPUTargetLowering> TLInfo;
  73   std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
  74   InstrItineraryData InstrItins;
  75   Triple TargetTriple;
  76
  77 public:
  78   AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS, TargetMachine &TM);
  79   AMDGPUSubtarget &initializeSubtargetDependencies(StringRef GPU, StringRef FS);
  80
  81   const AMDGPUFrameLowering *getFrameLowering() const override {
  82     return &FrameLowering;
  83   }
  84   const AMDGPUInstrInfo *getInstrInfo() const override {
  85     return InstrInfo.get();
  86   }
  87   const AMDGPURegisterInfo *getRegisterInfo() const override {
  88     return &InstrInfo->getRegisterInfo();
  89   }
  90   AMDGPUTargetLowering *getTargetLowering() const override {
  91     return TLInfo.get();
  92   }
  93   const DataLayout *getDataLayout() const override { return &DL; }
  94   const InstrItineraryData *getInstrItineraryData() const override {
  95     return &InstrItins;
  96   }
  97
  98   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
  99
 100   bool is64bit() const {
 101     return Is64bit;
 102   }
 103
 104   bool hasVertexCache() const {
 105     return HasVertexCache;
 106   }
 107
 108   short getTexVTXClauseSize() const {
 109     return TexVTXClauseSize;
 110   }
 111
 112   Generation getGeneration() const {
 113     return Gen;
 114   }
 115
 116   bool hasHWFP64() const {
 117     return FP64;
 118   }
 119
 120   bool hasCaymanISA() const {
 121     return CaymanISA;
 122   }
 123
 124   bool hasFP32Denormals() const {
 125     return FP32Denormals;
 126   }
 127
 128   bool hasFP64Denormals() const {
 129     return FP64Denormals;
 130   }
 131
 132   bool hasFlatAddressSpace() const {
 133     return FlatAddressSpace;
 134   }
 135
 136   bool hasBFE() const {
 137     return (getGeneration() >= EVERGREEN);
 138   }
 139
 140   bool hasBFI() const {
 141     return (getGeneration() >= EVERGREEN);
 142   }
 143
 144   bool hasBFM() const {
 145     return hasBFE();
 146   }
 147
 148   bool hasBCNT(unsigned Size) const {
 149     if (Size == 32)
 150       return (getGeneration() >= EVERGREEN);
 151
 152     if (Size == 64)
 153       return (getGeneration() >= SOUTHERN_ISLANDS);
 154
 155     return false;
 156   }
 157
 158   bool hasMulU24() const {
 159     return (getGeneration() >= EVERGREEN);
 160   }
 161
 162   bool hasMulI24() const {
 163     return (getGeneration() >= SOUTHERN_ISLANDS ||
 164             hasCaymanISA());
 165   }
 166
 167   bool hasFFBL() const {
 168     return (getGeneration() >= EVERGREEN);
 169   }
 170
 171   bool hasFFBH() const {
 172     return (getGeneration() >= EVERGREEN);
 173   }
 174
 175   bool IsIRStructurizerEnabled() const {
 176     return EnableIRStructurizer;
 177   }
 178
 179   bool isPromoteAllocaEnabled() const {
 180     return EnablePromoteAlloca;
 181   }
 182
 183   bool isIfCvtEnabled() const {
 184     return EnableIfCvt;
 185   }
 186
 187   bool loadStoreOptEnabled() const {
 188     return EnableLoadStoreOpt;
 189   }
 190
 191   unsigned getWavefrontSize() const {
 192     return WavefrontSize;
 193   }
 194
 195   unsigned getStackEntrySize() const;
 196
 197   bool hasCFAluBug() const {
 198     assert(getGeneration() <= NORTHERN_ISLANDS);
 199     return CFALUBug;
 200   }
 201
 202   int getLocalMemorySize() const {
 203     return LocalMemorySize;
 204   }
 205
 206   unsigned getAmdKernelCodeChipID() const;
 207
 208   bool enableMachineScheduler() const override {
 209     return getGeneration() <= NORTHERN_ISLANDS;
 210   }
 211
 212   void overrideSchedPolicy(MachineSchedPolicy &Policy,
 213                            MachineInstr *begin, MachineInstr *end,
 214                            unsigned NumRegionInstrs) const override;
 215
 216   // Helper functions to simplify if statements
 217   bool isTargetELF() const {
 218     return false;
 219   }
 220
 221   StringRef getDeviceName() const {
 222     return DevName;
 223   }
 224
 225   bool dumpCode() const {
 226     return DumpCode;
 227   }
 228   bool r600ALUEncoding() const {
 229     return R600ALUInst;
 230   }
 231   bool isAmdHsaOS() const {
 232     return TargetTriple.getOS() == Triple::AMDHSA;
 233   }
 234   bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const;
 235
 236   unsigned getMaxWavesPerCU() const {
 237     if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
 238       return 10;
 239
 240     // FIXME: Not sure what this is for other subtagets.
 241     llvm_unreachable("do not know max waves per CU for this subtarget.");
 242   }
 243 };
 244
 245 } // End namespace llvm
 246
 247 #endif