src/llvm/lib/Target/R600/SIInstrFormats.td

   1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // SI Instruction format definitions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
  15     AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
  16
  17   field bits<1> VM_CNT = 0;
  18   field bits<1> EXP_CNT = 0;
  19   field bits<1> LGKM_CNT = 0;
  20
  21   field bits<1> SALU = 0;
  22   field bits<1> VALU = 0;
  23
  24   field bits<1> SOP1 = 0;
  25   field bits<1> SOP2 = 0;
  26   field bits<1> SOPC = 0;
  27   field bits<1> SOPK = 0;
  28   field bits<1> SOPP = 0;
  29
  30   field bits<1> VOP1 = 0;
  31   field bits<1> VOP2 = 0;
  32   field bits<1> VOP3 = 0;
  33   field bits<1> VOPC = 0;
  34
  35   field bits<1> MUBUF = 0;
  36   field bits<1> MTBUF = 0;
  37   field bits<1> SMRD = 0;
  38   field bits<1> DS = 0;
  39   field bits<1> MIMG = 0;
  40   field bits<1> FLAT = 0;
  41
  42   // These need to be kept in sync with the enum in SIInstrFlags.
  43   let TSFlags{0} = VM_CNT;
  44   let TSFlags{1} = EXP_CNT;
  45   let TSFlags{2} = LGKM_CNT;
  46
  47   let TSFlags{3} = SALU;
  48   let TSFlags{4} = VALU;
  49
  50   let TSFlags{5} = SOP1;
  51   let TSFlags{6} = SOP2;
  52   let TSFlags{7} = SOPC;
  53   let TSFlags{8} = SOPK;
  54   let TSFlags{9} = SOPP;
  55
  56   let TSFlags{10} = VOP1;
  57   let TSFlags{11} = VOP2;
  58   let TSFlags{12} = VOP3;
  59   let TSFlags{13} = VOPC;
  60
  61   let TSFlags{14} = MUBUF;
  62   let TSFlags{15} = MTBUF;
  63   let TSFlags{16} = SMRD;
  64   let TSFlags{17} = DS;
  65   let TSFlags{18} = MIMG;
  66   let TSFlags{19} = FLAT;
  67
  68   // Most instructions require adjustments after selection to satisfy
  69   // operand requirements.
  70   let hasPostISelHook = 1;
  71   let SchedRW = [Write32Bit];
  72 }
  73
  74 class Enc32 {
  75
  76   field bits<32> Inst;
  77   int Size = 4;
  78 }
  79
  80 class Enc64 {
  81
  82   field bits<64> Inst;
  83   int Size = 8;
  84 }
  85
  86 let Uses = [EXEC] in {
  87
  88 class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
  89     InstSI <outs, ins, asm, pattern> {
  90
  91   let mayLoad = 0;
  92   let mayStore = 0;
  93   let hasSideEffects = 0;
  94   let UseNamedOperandTable = 1;
  95   let VALU = 1;
  96 }
  97
  98 class VOPCCommon <dag ins, string asm, list<dag> pattern> :
  99     VOPAnyCommon <(outs VCCReg:$dst), ins, asm, pattern> {
 100
 101   let DisableEncoding = "$dst";
 102   let VOPC = 1;
 103   let Size = 4;
 104 }
 105
 106 class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> :
 107     VOPAnyCommon <outs, ins, asm, pattern> {
 108
 109   let VOP1 = 1;
 110   let Size = 4;
 111 }
 112
 113 class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> :
 114     VOPAnyCommon <outs, ins, asm, pattern> {
 115
 116   let VOP2 = 1;
 117   let Size = 4;
 118 }
 119
 120 class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
 121     VOPAnyCommon <outs, ins, asm, pattern> {
 122
 123   // Using complex patterns gives VOP3 patterns a very high complexity rating,
 124   // but standalone patterns are almost always prefered, so we need to adjust the
 125   // priority lower.  The goal is to use a high number to reduce complexity to
 126   // zero (or less than zero).
 127   let AddedComplexity = -1000;
 128
 129   let VOP3 = 1;
 130   int Size = 8;
 131 }
 132
 133 } // End Uses = [EXEC]
 134
 135 //===----------------------------------------------------------------------===//
 136 // Scalar operations
 137 //===----------------------------------------------------------------------===//
 138
 139 class SOP1e <bits<8> op> : Enc32 {
 140
 141   bits<7> SDST;
 142   bits<8> SSRC0;
 143
 144   let Inst{7-0} = SSRC0;
 145   let Inst{15-8} = op;
 146   let Inst{22-16} = SDST;
 147   let Inst{31-23} = 0x17d; //encoding;
 148 }
 149
 150 class SOP2e <bits<7> op> : Enc32 {
 151
 152   bits<7> SDST;
 153   bits<8> SSRC0;
 154   bits<8> SSRC1;
 155
 156   let Inst{7-0} = SSRC0;
 157   let Inst{15-8} = SSRC1;
 158   let Inst{22-16} = SDST;
 159   let Inst{29-23} = op;
 160   let Inst{31-30} = 0x2; // encoding
 161 }
 162
 163 class SOPCe <bits<7> op> : Enc32 {
 164
 165   bits<8> SSRC0;
 166   bits<8> SSRC1;
 167
 168   let Inst{7-0} = SSRC0;
 169   let Inst{15-8} = SSRC1;
 170   let Inst{22-16} = op;
 171   let Inst{31-23} = 0x17e;
 172 }
 173
 174 class SOPKe <bits<5> op> : Enc32 {
 175
 176   bits <7> SDST;
 177   bits <16> SIMM16;
 178
 179   let Inst{15-0} = SIMM16;
 180   let Inst{22-16} = SDST;
 181   let Inst{27-23} = op;
 182   let Inst{31-28} = 0xb; //encoding
 183 }
 184
 185 class SOPPe <bits<7> op> : Enc32 {
 186
 187   bits <16> simm16;
 188
 189   let Inst{15-0} = simm16;
 190   let Inst{22-16} = op;
 191   let Inst{31-23} = 0x17f; // encoding
 192 }
 193
 194 class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
 195
 196   bits<7> SDST;
 197   bits<7> SBASE;
 198   bits<8> OFFSET;
 199
 200   let Inst{7-0} = OFFSET;
 201   let Inst{8} = imm;
 202   let Inst{14-9} = SBASE{6-1};
 203   let Inst{21-15} = SDST;
 204   let Inst{26-22} = op;
 205   let Inst{31-27} = 0x18; //encoding
 206 }
 207
 208 let SchedRW = [WriteSALU] in {
 209 class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
 210     InstSI<outs, ins, asm, pattern> {
 211   let mayLoad = 0;
 212   let mayStore = 0;
 213   let hasSideEffects = 0;
 214   let SALU = 1;
 215   let SOP1 = 1;
 216 }
 217
 218 class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> :
 219     InstSI <outs, ins, asm, pattern> {
 220
 221   let mayLoad = 0;
 222   let mayStore = 0;
 223   let hasSideEffects = 0;
 224   let SALU = 1;
 225   let SOP2 = 1;
 226
 227   let UseNamedOperandTable = 1;
 228 }
 229
 230 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
 231   InstSI<outs, ins, asm, pattern>, SOPCe <op> {
 232
 233   let DisableEncoding = "$dst";
 234   let mayLoad = 0;
 235   let mayStore = 0;
 236   let hasSideEffects = 0;
 237   let SALU = 1;
 238   let SOPC = 1;
 239
 240   let UseNamedOperandTable = 1;
 241 }
 242
 243 class SOPK <dag outs, dag ins, string asm, list<dag> pattern> :
 244    InstSI <outs, ins , asm, pattern> {
 245
 246   let mayLoad = 0;
 247   let mayStore = 0;
 248   let hasSideEffects = 0;
 249   let SALU = 1;
 250   let SOPK = 1;
 251
 252   let UseNamedOperandTable = 1;
 253 }
 254
 255 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
 256                 InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
 257
 258   let mayLoad = 0;
 259   let mayStore = 0;
 260   let hasSideEffects = 0;
 261   let isCodeGenOnly = 0;
 262   let SALU = 1;
 263   let SOPP = 1;
 264
 265   let UseNamedOperandTable = 1;
 266 }
 267
 268 } // let SchedRW = [WriteSALU]
 269
 270 class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
 271     InstSI<outs, ins, asm, pattern> {
 272
 273   let LGKM_CNT = 1;
 274   let SMRD = 1;
 275   let mayStore = 0;
 276   let mayLoad = 1;
 277   let hasSideEffects = 0;
 278   let UseNamedOperandTable = 1;
 279   let SchedRW = [WriteSMEM];
 280 }
 281
 282 //===----------------------------------------------------------------------===//
 283 // Vector ALU operations
 284 //===----------------------------------------------------------------------===//
 285
 286 class VOP1e <bits<8> op> : Enc32 {
 287
 288   bits<8> VDST;
 289   bits<9> SRC0;
 290
 291   let Inst{8-0} = SRC0;
 292   let Inst{16-9} = op;
 293   let Inst{24-17} = VDST;
 294   let Inst{31-25} = 0x3f; //encoding
 295 }
 296
 297 class VOP2e <bits<6> op> : Enc32 {
 298
 299   bits<8> VDST;
 300   bits<9> SRC0;
 301   bits<8> VSRC1;
 302
 303   let Inst{8-0} = SRC0;
 304   let Inst{16-9} = VSRC1;
 305   let Inst{24-17} = VDST;
 306   let Inst{30-25} = op;
 307   let Inst{31} = 0x0; //encoding
 308 }
 309
 310 class VOP3e <bits<9> op> : Enc64 {
 311
 312   bits<8> dst;
 313   bits<2> src0_modifiers;
 314   bits<9> src0;
 315   bits<2> src1_modifiers;
 316   bits<9> src1;
 317   bits<2> src2_modifiers;
 318   bits<9> src2;
 319   bits<1> clamp;
 320   bits<2> omod;
 321
 322   let Inst{7-0} = dst;
 323   let Inst{8} = src0_modifiers{1};
 324   let Inst{9} = src1_modifiers{1};
 325   let Inst{10} = src2_modifiers{1};
 326   let Inst{11} = clamp;
 327   let Inst{25-17} = op;
 328   let Inst{31-26} = 0x34; //encoding
 329   let Inst{40-32} = src0;
 330   let Inst{49-41} = src1;
 331   let Inst{58-50} = src2;
 332   let Inst{60-59} = omod;
 333   let Inst{61} = src0_modifiers{0};
 334   let Inst{62} = src1_modifiers{0};
 335   let Inst{63} = src2_modifiers{0};
 336 }
 337
 338 class VOP3be <bits<9> op> : Enc64 {
 339
 340   bits<8> dst;
 341   bits<2> src0_modifiers;
 342   bits<9> src0;
 343   bits<2> src1_modifiers;
 344   bits<9> src1;
 345   bits<2> src2_modifiers;
 346   bits<9> src2;
 347   bits<7> sdst;
 348   bits<2> omod;
 349
 350   let Inst{7-0} = dst;
 351   let Inst{14-8} = sdst;
 352   let Inst{25-17} = op;
 353   let Inst{31-26} = 0x34; //encoding
 354   let Inst{40-32} = src0;
 355   let Inst{49-41} = src1;
 356   let Inst{58-50} = src2;
 357   let Inst{60-59} = omod;
 358   let Inst{61} = src0_modifiers{0};
 359   let Inst{62} = src1_modifiers{0};
 360   let Inst{63} = src2_modifiers{0};
 361 }
 362
 363 class VOPCe <bits<8> op> : Enc32 {
 364
 365   bits<9> SRC0;
 366   bits<8> VSRC1;
 367
 368   let Inst{8-0} = SRC0;
 369   let Inst{16-9} = VSRC1;
 370   let Inst{24-17} = op;
 371   let Inst{31-25} = 0x3e;
 372 }
 373
 374 class VINTRPe <bits<2> op> : Enc32 {
 375
 376   bits<8> VDST;
 377   bits<8> VSRC;
 378   bits<2> ATTRCHAN;
 379   bits<6> ATTR;
 380
 381   let Inst{7-0} = VSRC;
 382   let Inst{9-8} = ATTRCHAN;
 383   let Inst{15-10} = ATTR;
 384   let Inst{17-16} = op;
 385   let Inst{25-18} = VDST;
 386   let Inst{31-26} = 0x32; // encoding
 387 }
 388
 389 class DSe <bits<8> op> : Enc64 {
 390
 391   bits<8> vdst;
 392   bits<1> gds;
 393   bits<8> addr;
 394   bits<8> data0;
 395   bits<8> data1;
 396   bits<8> offset0;
 397   bits<8> offset1;
 398
 399   let Inst{7-0} = offset0;
 400   let Inst{15-8} = offset1;
 401   let Inst{17} = gds;
 402   let Inst{25-18} = op;
 403   let Inst{31-26} = 0x36; //encoding
 404   let Inst{39-32} = addr;
 405   let Inst{47-40} = data0;
 406   let Inst{55-48} = data1;
 407   let Inst{63-56} = vdst;
 408 }
 409
 410 class MUBUFe <bits<7> op> : Enc64 {
 411
 412   bits<12> offset;
 413   bits<1> offen;
 414   bits<1> idxen;
 415   bits<1> glc;
 416   bits<1> addr64;
 417   bits<1> lds;
 418   bits<8> vaddr;
 419   bits<8> vdata;
 420   bits<7> srsrc;
 421   bits<1> slc;
 422   bits<1> tfe;
 423   bits<8> soffset;
 424
 425   let Inst{11-0} = offset;
 426   let Inst{12} = offen;
 427   let Inst{13} = idxen;
 428   let Inst{14} = glc;
 429   let Inst{15} = addr64;
 430   let Inst{16} = lds;
 431   let Inst{24-18} = op;
 432   let Inst{31-26} = 0x38; //encoding
 433   let Inst{39-32} = vaddr;
 434   let Inst{47-40} = vdata;
 435   let Inst{52-48} = srsrc{6-2};
 436   let Inst{54} = slc;
 437   let Inst{55} = tfe;
 438   let Inst{63-56} = soffset;
 439 }
 440
 441 class MTBUFe <bits<3> op> : Enc64 {
 442
 443   bits<8> VDATA;
 444   bits<12> OFFSET;
 445   bits<1> OFFEN;
 446   bits<1> IDXEN;
 447   bits<1> GLC;
 448   bits<1> ADDR64;
 449   bits<4> DFMT;
 450   bits<3> NFMT;
 451   bits<8> VADDR;
 452   bits<7> SRSRC;
 453   bits<1> SLC;
 454   bits<1> TFE;
 455   bits<8> SOFFSET;
 456
 457   let Inst{11-0} = OFFSET;
 458   let Inst{12} = OFFEN;
 459   let Inst{13} = IDXEN;
 460   let Inst{14} = GLC;
 461   let Inst{15} = ADDR64;
 462   let Inst{18-16} = op;
 463   let Inst{22-19} = DFMT;
 464   let Inst{25-23} = NFMT;
 465   let Inst{31-26} = 0x3a; //encoding
 466   let Inst{39-32} = VADDR;
 467   let Inst{47-40} = VDATA;
 468   let Inst{52-48} = SRSRC{6-2};
 469   let Inst{54} = SLC;
 470   let Inst{55} = TFE;
 471   let Inst{63-56} = SOFFSET;
 472 }
 473
 474 class MIMGe <bits<7> op> : Enc64 {
 475
 476   bits<8> VDATA;
 477   bits<4> DMASK;
 478   bits<1> UNORM;
 479   bits<1> GLC;
 480   bits<1> DA;
 481   bits<1> R128;
 482   bits<1> TFE;
 483   bits<1> LWE;
 484   bits<1> SLC;
 485   bits<8> VADDR;
 486   bits<7> SRSRC;
 487   bits<7> SSAMP;
 488
 489   let Inst{11-8} = DMASK;
 490   let Inst{12} = UNORM;
 491   let Inst{13} = GLC;
 492   let Inst{14} = DA;
 493   let Inst{15} = R128;
 494   let Inst{16} = TFE;
 495   let Inst{17} = LWE;
 496   let Inst{24-18} = op;
 497   let Inst{25} = SLC;
 498   let Inst{31-26} = 0x3c;
 499   let Inst{39-32} = VADDR;
 500   let Inst{47-40} = VDATA;
 501   let Inst{52-48} = SRSRC{6-2};
 502   let Inst{57-53} = SSAMP{6-2};
 503 }
 504
 505 class FLATe<bits<7> op> : Enc64 {
 506   bits<8> addr;
 507   bits<8> data;
 508   bits<8> vdst;
 509   bits<1> slc;
 510   bits<1> glc;
 511   bits<1> tfe;
 512
 513   // 15-0 is reserved.
 514   let Inst{16} = glc;
 515   let Inst{17} = slc;
 516   let Inst{24-18} = op;
 517   let Inst{31-26} = 0x37; // Encoding.
 518   let Inst{39-32} = addr;
 519   let Inst{47-40} = data;
 520   // 54-48 is reserved.
 521   let Inst{55} = tfe;
 522   let Inst{63-56} = vdst;
 523 }
 524
 525 class EXPe : Enc64 {
 526   bits<4> EN;
 527   bits<6> TGT;
 528   bits<1> COMPR;
 529   bits<1> DONE;
 530   bits<1> VM;
 531   bits<8> VSRC0;
 532   bits<8> VSRC1;
 533   bits<8> VSRC2;
 534   bits<8> VSRC3;
 535
 536   let Inst{3-0} = EN;
 537   let Inst{9-4} = TGT;
 538   let Inst{10} = COMPR;
 539   let Inst{11} = DONE;
 540   let Inst{12} = VM;
 541   let Inst{31-26} = 0x3e;
 542   let Inst{39-32} = VSRC0;
 543   let Inst{47-40} = VSRC1;
 544   let Inst{55-48} = VSRC2;
 545   let Inst{63-56} = VSRC3;
 546 }
 547
 548 let Uses = [EXEC] in {
 549
 550 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
 551     VOP1Common <outs, ins, asm, pattern>,
 552     VOP1e<op>;
 553
 554 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
 555     VOP2Common <outs, ins, asm, pattern>, VOP2e<op>;
 556
 557 class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
 558     VOP3Common <outs, ins, asm, pattern>, VOP3be<op>;
 559
 560 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
 561     VOPCCommon <ins, asm, pattern>, VOPCe <op>;
 562
 563 class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
 564     InstSI <outs, ins, asm, pattern> {
 565   let mayLoad = 1;
 566   let mayStore = 0;
 567   let hasSideEffects = 0;
 568 }
 569
 570 } // End Uses = [EXEC]
 571
 572 //===----------------------------------------------------------------------===//
 573 // Vector I/O operations
 574 //===----------------------------------------------------------------------===//
 575
 576 let Uses = [EXEC] in {
 577
 578 class DS <dag outs, dag ins, string asm, list<dag> pattern> :
 579     InstSI <outs, ins, asm, pattern> {
 580
 581   let LGKM_CNT = 1;
 582   let DS = 1;
 583   let UseNamedOperandTable = 1;
 584   let DisableEncoding = "$m0";
 585   let SchedRW = [WriteLDS];
 586 }
 587
 588 class DS_si <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
 589     DS <outs, ins, asm, pattern>, DSe<op>;
 590
 591 class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
 592     InstSI<outs, ins, asm, pattern> {
 593
 594   let VM_CNT = 1;
 595   let EXP_CNT = 1;
 596   let MUBUF = 1;
 597
 598   let hasSideEffects = 0;
 599   let UseNamedOperandTable = 1;
 600   let SchedRW = [WriteVMEM];
 601 }
 602
 603 class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> :
 604     InstSI<outs, ins, asm, pattern> {
 605
 606   let VM_CNT = 1;
 607   let EXP_CNT = 1;
 608   let MTBUF = 1;
 609
 610   let hasSideEffects = 0;
 611   let UseNamedOperandTable = 1;
 612   let SchedRW = [WriteVMEM];
 613 }
 614
 615 class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
 616     InstSI<outs, ins, asm, pattern>, FLATe <op> {
 617   let FLAT = 1;
 618   // Internally, FLAT instruction are executed as both an LDS and a
 619   // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
 620   // and are not considered done until both have been decremented.
 621   let VM_CNT = 1;
 622   let LGKM_CNT = 1;
 623
 624   let Uses = [EXEC, FLAT_SCR]; // M0
 625
 626   let UseNamedOperandTable = 1;
 627   let hasSideEffects = 0;
 628 }
 629
 630 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
 631     InstSI <outs, ins, asm, pattern>, MIMGe <op> {
 632
 633   let VM_CNT = 1;
 634   let EXP_CNT = 1;
 635   let MIMG = 1;
 636
 637   let hasSideEffects = 0; // XXX ????
 638 }
 639
 640
 641 } // End Uses = [EXEC]