src/llvm/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp

   1 //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file includes code for rendering MCInst instances as AT&T-style
  11 // assembly.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "X86ATTInstPrinter.h"
  16 #include "MCTargetDesc/X86BaseInfo.h"
  17 #include "MCTargetDesc/X86MCTargetDesc.h"
  18 #include "X86InstComments.h"
  19 #include "llvm/MC/MCAsmInfo.h"
  20 #include "llvm/MC/MCExpr.h"
  21 #include "llvm/MC/MCInst.h"
  22 #include "llvm/MC/MCInstrInfo.h"
  23 #include "llvm/MC/MCRegisterInfo.h"
  24 #include "llvm/Support/ErrorHandling.h"
  25 #include "llvm/Support/Format.h"
  26 #include "llvm/Support/FormattedStream.h"
  27 #include <map>
  28 using namespace llvm;
  29
  30 #define DEBUG_TYPE "asm-printer"
  31
  32 // Include the auto-generated portion of the assembly writer.
  33 #define PRINT_ALIAS_INSTR
  34 #include "X86GenAsmWriter.inc"
  35
  36 void X86ATTInstPrinter::printRegName(raw_ostream &OS,
  37                                      unsigned RegNo) const {
  38   OS << markup("<reg:")
  39      << '%' << getRegisterName(RegNo)
  40      << markup(">");
  41 }
  42
  43 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
  44                                   StringRef Annot) {
  45   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
  46   uint64_t TSFlags = Desc.TSFlags;
  47
  48   // If verbose assembly is enabled, we can print some informative comments.
  49   if (CommentStream)
  50     HasCustomInstComment =
  51         EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
  52
  53   if (TSFlags & X86II::LOCK)
  54     OS << "\tlock\n";
  55
  56   // Output CALLpcrel32 as "callq" in 64-bit mode.
  57   // In Intel annotation it's always emitted as "call".
  58   //
  59   // TODO: Probably this hack should be redesigned via InstAlias in
  60   // InstrInfo.td as soon as Requires clause is supported properly
  61   // for InstAlias.
  62   if (MI->getOpcode() == X86::CALLpcrel32 &&
  63       (getAvailableFeatures() & X86::Mode64Bit) != 0) {
  64     OS << "\tcallq\t";
  65     printPCRelImm(MI, 0, OS);
  66   }
  67   // Try to print any aliases first.
  68   else if (!printAliasInstr(MI, OS))
  69     printInstruction(MI, OS);
  70
  71   // Next always print the annotation.
  72   printAnnotation(OS, Annot);
  73 }
  74
  75 static void printSSEAVXCC(int64_t Imm, raw_ostream &O) {
  76   switch (Imm) {
  77   default: llvm_unreachable("Invalid ssecc/avxcc argument!");
  78   case    0: O << "eq"; break;
  79   case    1: O << "lt"; break;
  80   case    2: O << "le"; break;
  81   case    3: O << "unord"; break;
  82   case    4: O << "neq"; break;
  83   case    5: O << "nlt"; break;
  84   case    6: O << "nle"; break;
  85   case    7: O << "ord"; break;
  86   case    8: O << "eq_uq"; break;
  87   case    9: O << "nge"; break;
  88   case  0xa: O << "ngt"; break;
  89   case  0xb: O << "false"; break;
  90   case  0xc: O << "neq_oq"; break;
  91   case  0xd: O << "ge"; break;
  92   case  0xe: O << "gt"; break;
  93   case  0xf: O << "true"; break;
  94   case 0x10: O << "eq_os"; break;
  95   case 0x11: O << "lt_oq"; break;
  96   case 0x12: O << "le_oq"; break;
  97   case 0x13: O << "unord_s"; break;
  98   case 0x14: O << "neq_us"; break;
  99   case 0x15: O << "nlt_uq"; break;
 100   case 0x16: O << "nle_uq"; break;
 101   case 0x17: O << "ord_s"; break;
 102   case 0x18: O << "eq_us"; break;
 103   case 0x19: O << "nge_uq"; break;
 104   case 0x1a: O << "ngt_uq"; break;
 105   case 0x1b: O << "false_os"; break;
 106   case 0x1c: O << "neq_os"; break;
 107   case 0x1d: O << "ge_oq"; break;
 108   case 0x1e: O << "gt_oq"; break;
 109   case 0x1f: O << "true_us"; break;
 110   }
 111 }
 112
 113 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
 114                                    raw_ostream &O) {
 115   int64_t Imm = MI->getOperand(Op).getImm();
 116   assert((Imm & 0x7) == Imm); // Ensure valid immediate.
 117   printSSEAVXCC(Imm, O);
 118 }
 119
 120 void X86ATTInstPrinter::printAVXCC(const MCInst *MI, unsigned Op,
 121                                    raw_ostream &O) {
 122   int64_t Imm = MI->getOperand(Op).getImm();
 123   assert((Imm & 0x1f) == Imm); // Ensure valid immediate.
 124   printSSEAVXCC(Imm, O);
 125 }
 126
 127 void X86ATTInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op,
 128                                    raw_ostream &O) {
 129   int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
 130   switch (Imm) {
 131   case 0: O << "{rn-sae}"; break;
 132   case 1: O << "{rd-sae}"; break;
 133   case 2: O << "{ru-sae}"; break;
 134   case 3: O << "{rz-sae}"; break;
 135   }
 136 }
 137 /// printPCRelImm - This is used to print an immediate value that ends up
 138 /// being encoded as a pc-relative value (e.g. for jumps and calls).  These
 139 /// print slightly differently than normal immediates.  For example, a $ is not
 140 /// emitted.
 141 void X86ATTInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
 142                                       raw_ostream &O) {
 143   const MCOperand &Op = MI->getOperand(OpNo);
 144   if (Op.isImm())
 145     O << formatImm(Op.getImm());
 146   else {
 147     assert(Op.isExpr() && "unknown pcrel immediate operand");
 148     // If a symbolic branch target was added as a constant expression then print
 149     // that address in hex.
 150     const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
 151     int64_t Address;
 152     if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
 153       O << formatHex((uint64_t)Address);
 154     } else {
 155       // Otherwise, just print the expression.
 156       O << *Op.getExpr();
 157     }
 158   }
 159 }
 160
 161 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
 162                                      raw_ostream &O) {
 163   const MCOperand &Op = MI->getOperand(OpNo);
 164   if (Op.isReg()) {
 165     printRegName(O, Op.getReg());
 166   } else if (Op.isImm()) {
 167     // Print X86 immediates as signed values.
 168     O << markup("<imm:")
 169       << '$' << formatImm((int64_t)Op.getImm())
 170       << markup(">");
 171
 172     // If there are no instruction-specific comments, add a comment clarifying
 173     // the hex value of the immediate operand when it isn't in the range
 174     // [-256,255].
 175     if (CommentStream && !HasCustomInstComment &&
 176         (Op.getImm() > 255 || Op.getImm() < -256))
 177       *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
 178
 179   } else {
 180     assert(Op.isExpr() && "unknown operand kind in printOperand");
 181     O << markup("<imm:")
 182       << '$' << *Op.getExpr()
 183       << markup(">");
 184   }
 185 }
 186
 187 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
 188                                           raw_ostream &O) {
 189   const MCOperand &BaseReg  = MI->getOperand(Op+X86::AddrBaseReg);
 190   const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
 191   const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
 192   const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg);
 193
 194   O << markup("<mem:");
 195
 196   // If this has a segment register, print it.
 197   if (SegReg.getReg()) {
 198     printOperand(MI, Op+X86::AddrSegmentReg, O);
 199     O << ':';
 200   }
 201
 202   if (DispSpec.isImm()) {
 203     int64_t DispVal = DispSpec.getImm();
 204     if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
 205       O << formatImm(DispVal);
 206   } else {
 207     assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
 208     O << *DispSpec.getExpr();
 209   }
 210
 211   if (IndexReg.getReg() || BaseReg.getReg()) {
 212     O << '(';
 213     if (BaseReg.getReg())
 214       printOperand(MI, Op+X86::AddrBaseReg, O);
 215
 216     if (IndexReg.getReg()) {
 217       O << ',';
 218       printOperand(MI, Op+X86::AddrIndexReg, O);
 219       unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
 220       if (ScaleVal != 1) {
 221         O << ','
 222           << markup("<imm:")
 223           << ScaleVal // never printed in hex.
 224           << markup(">");
 225       }
 226     }
 227     O << ')';
 228   }
 229
 230   O << markup(">");
 231 }
 232
 233 void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
 234                                     raw_ostream &O) {
 235   const MCOperand &SegReg = MI->getOperand(Op+1);
 236
 237   O << markup("<mem:");
 238
 239   // If this has a segment register, print it.
 240   if (SegReg.getReg()) {
 241     printOperand(MI, Op+1, O);
 242     O << ':';
 243   }
 244
 245   O << "(";
 246   printOperand(MI, Op, O);
 247   O << ")";
 248
 249   O << markup(">");
 250 }
 251
 252 void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
 253                                     raw_ostream &O) {
 254   O << markup("<mem:");
 255
 256   O << "%es:(";
 257   printOperand(MI, Op, O);
 258   O << ")";
 259
 260   O << markup(">");
 261 }
 262
 263 void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
 264                                        raw_ostream &O) {
 265   const MCOperand &DispSpec = MI->getOperand(Op);
 266   const MCOperand &SegReg = MI->getOperand(Op+1);
 267
 268   O << markup("<mem:");
 269
 270   // If this has a segment register, print it.
 271   if (SegReg.getReg()) {
 272     printOperand(MI, Op+1, O);
 273     O << ':';
 274   }
 275
 276   if (DispSpec.isImm()) {
 277     O << formatImm(DispSpec.getImm());
 278   } else {
 279     assert(DispSpec.isExpr() && "non-immediate displacement?");
 280     O << *DispSpec.getExpr();
 281   }
 282
 283   O << markup(">");
 284 }