src/llvm/lib/Target/X86/X86InstrInfo.h

   1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the X86 implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
  15 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
  16
  17 #include "MCTargetDesc/X86BaseInfo.h"
  18 #include "X86RegisterInfo.h"
  19 #include "llvm/ADT/DenseMap.h"
  20 #include "llvm/Target/TargetInstrInfo.h"
  21
  22 #define GET_INSTRINFO_HEADER
  23 #include "X86GenInstrInfo.inc"
  24
  25 namespace llvm {
  26   class X86RegisterInfo;
  27   class X86Subtarget;
  28
  29 namespace X86 {
  30   // X86 specific condition code. These correspond to X86_*_COND in
  31   // X86InstrInfo.td. They must be kept in synch.
  32   enum CondCode {
  33     COND_A  = 0,
  34     COND_AE = 1,
  35     COND_B  = 2,
  36     COND_BE = 3,
  37     COND_E  = 4,
  38     COND_G  = 5,
  39     COND_GE = 6,
  40     COND_L  = 7,
  41     COND_LE = 8,
  42     COND_NE = 9,
  43     COND_NO = 10,
  44     COND_NP = 11,
  45     COND_NS = 12,
  46     COND_O  = 13,
  47     COND_P  = 14,
  48     COND_S  = 15,
  49     LAST_VALID_COND = COND_S,
  50
  51     // Artificial condition codes. These are used by AnalyzeBranch
  52     // to indicate a block terminated with two conditional branches to
  53     // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
  54     // which can't be represented on x86 with a single condition. These
  55     // are never used in MachineInstrs.
  56     COND_NE_OR_P,
  57     COND_NP_OR_E,
  58
  59     COND_INVALID
  60   };
  61
  62   // Turn condition code into conditional branch opcode.
  63   unsigned GetCondBranchFromCond(CondCode CC);
  64
  65   /// \brief Return a set opcode for the given condition and whether it has
  66   /// a memory operand.
  67   unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
  68
  69   /// \brief Return a cmov opcode for the given condition, register size in
  70   /// bytes, and operand type.
  71   unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
  72                            bool HasMemoryOperand = false);
  73
  74   // Turn CMov opcode into condition code.
  75   CondCode getCondFromCMovOpc(unsigned Opc);
  76
  77   /// GetOppositeBranchCondition - Return the inverse of the specified cond,
  78   /// e.g. turning COND_E to COND_NE.
  79   CondCode GetOppositeBranchCondition(CondCode CC);
  80 }  // end namespace X86;
  81
  82
  83 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
  84 /// a reference to a stub for a global, not the global itself.
  85 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
  86   switch (TargetFlag) {
  87   case X86II::MO_DLLIMPORT: // dllimport stub.
  88   case X86II::MO_GOTPCREL:  // rip-relative GOT reference.
  89   case X86II::MO_GOT:       // normal GOT reference.
  90   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:        // Normal $non_lazy_ptr ref.
  91   case X86II::MO_DARWIN_NONLAZY:                 // Normal $non_lazy_ptr ref.
  92   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
  93     return true;
  94   default:
  95     return false;
  96   }
  97 }
  98
  99 /// isGlobalRelativeToPICBase - Return true if the specified global value
 100 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg).  If this
 101 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
 102 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
 103   switch (TargetFlag) {
 104   case X86II::MO_GOTOFF:                         // isPICStyleGOT: local global.
 105   case X86II::MO_GOT:                            // isPICStyleGOT: other global.
 106   case X86II::MO_PIC_BASE_OFFSET:                // Darwin local global.
 107   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:        // Darwin/32 external global.
 108   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
 109   case X86II::MO_TLVP:                           // ??? Pretty sure..
 110     return true;
 111   default:
 112     return false;
 113   }
 114 }
 115
 116 inline static bool isScale(const MachineOperand &MO) {
 117   return MO.isImm() &&
 118     (MO.getImm() == 1 || MO.getImm() == 2 ||
 119      MO.getImm() == 4 || MO.getImm() == 8);
 120 }
 121
 122 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
 123   if (MI->getOperand(Op).isFI()) return true;
 124   return Op+X86::AddrSegmentReg <= MI->getNumOperands() &&
 125     MI->getOperand(Op+X86::AddrBaseReg).isReg() &&
 126     isScale(MI->getOperand(Op+X86::AddrScaleAmt)) &&
 127     MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
 128     (MI->getOperand(Op+X86::AddrDisp).isImm() ||
 129      MI->getOperand(Op+X86::AddrDisp).isGlobal() ||
 130      MI->getOperand(Op+X86::AddrDisp).isCPI() ||
 131      MI->getOperand(Op+X86::AddrDisp).isJTI());
 132 }
 133
 134 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
 135   if (MI->getOperand(Op).isFI()) return true;
 136   return Op+X86::AddrNumOperands <= MI->getNumOperands() &&
 137     MI->getOperand(Op+X86::AddrSegmentReg).isReg() &&
 138     isLeaMem(MI, Op);
 139 }
 140
 141 class X86InstrInfo final : public X86GenInstrInfo {
 142   X86Subtarget &Subtarget;
 143   const X86RegisterInfo RI;
 144
 145   /// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
 146   /// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps.
 147   ///
 148   typedef DenseMap<unsigned,
 149                    std::pair<unsigned, unsigned> > RegOp2MemOpTableType;
 150   RegOp2MemOpTableType RegOp2MemOpTable2Addr;
 151   RegOp2MemOpTableType RegOp2MemOpTable0;
 152   RegOp2MemOpTableType RegOp2MemOpTable1;
 153   RegOp2MemOpTableType RegOp2MemOpTable2;
 154   RegOp2MemOpTableType RegOp2MemOpTable3;
 155   RegOp2MemOpTableType RegOp2MemOpTable4;
 156
 157   /// MemOp2RegOpTable - Load / store unfolding opcode map.
 158   ///
 159   typedef DenseMap<unsigned,
 160                    std::pair<unsigned, unsigned> > MemOp2RegOpTableType;
 161   MemOp2RegOpTableType MemOp2RegOpTable;
 162
 163   static void AddTableEntry(RegOp2MemOpTableType &R2MTable,
 164                             MemOp2RegOpTableType &M2RTable,
 165                             unsigned RegOp, unsigned MemOp, unsigned Flags);
 166
 167   virtual void anchor();
 168
 169 public:
 170   explicit X86InstrInfo(X86Subtarget &STI);
 171
 172   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
 173   /// such, whenever a client has an instance of instruction info, it should
 174   /// always be able to get register info as well (through this method).
 175   ///
 176   const X86RegisterInfo &getRegisterInfo() const { return RI; }
 177
 178   /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
 179   /// extension instruction. That is, it's like a copy where it's legal for the
 180   /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
 181   /// true, then it's expected the pre-extension value is available as a subreg
 182   /// of the result register. This also returns the sub-register index in
 183   /// SubIdx.
 184   bool isCoalescableExtInstr(const MachineInstr &MI,
 185                              unsigned &SrcReg, unsigned &DstReg,
 186                              unsigned &SubIdx) const override;
 187
 188   unsigned isLoadFromStackSlot(const MachineInstr *MI,
 189                                int &FrameIndex) const override;
 190   /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
 191   /// stack locations as well.  This uses a heuristic so it isn't
 192   /// reliable for correctness.
 193   unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
 194                                      int &FrameIndex) const override;
 195
 196   unsigned isStoreToStackSlot(const MachineInstr *MI,
 197                               int &FrameIndex) const override;
 198   /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
 199   /// stack locations as well.  This uses a heuristic so it isn't
 200   /// reliable for correctness.
 201   unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
 202                                     int &FrameIndex) const override;
 203
 204   bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
 205                                          AliasAnalysis *AA) const override;
 206   void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
 207                      unsigned DestReg, unsigned SubIdx,
 208                      const MachineInstr *Orig,
 209                      const TargetRegisterInfo &TRI) const override;
 210
 211   /// Given an operand within a MachineInstr, insert preceding code to put it
 212   /// into the right format for a particular kind of LEA instruction. This may
 213   /// involve using an appropriate super-register instead (with an implicit use
 214   /// of the original) or creating a new virtual register and inserting COPY
 215   /// instructions to get the data into the right class.
 216   ///
 217   /// Reference parameters are set to indicate how caller should add this
 218   /// operand to the LEA instruction.
 219   bool classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
 220                       unsigned LEAOpcode, bool AllowSP,
 221                       unsigned &NewSrc, bool &isKill,
 222                       bool &isUndef, MachineOperand &ImplicitOp) const;
 223
 224   /// convertToThreeAddress - This method must be implemented by targets that
 225   /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
 226   /// may be able to convert a two-address instruction into a true
 227   /// three-address instruction on demand.  This allows the X86 target (for
 228   /// example) to convert ADD and SHL instructions into LEA instructions if they
 229   /// would require register copies due to two-addressness.
 230   ///
 231   /// This method returns a null pointer if the transformation cannot be
 232   /// performed, otherwise it returns the new instruction.
 233   ///
 234   MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
 235                                       MachineBasicBlock::iterator &MBBI,
 236                                       LiveVariables *LV) const override;
 237
 238   /// commuteInstruction - We have a few instructions that must be hacked on to
 239   /// commute them.
 240   ///
 241   MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const override;
 242
 243   bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
 244                              unsigned &SrcOpIdx2) const override;
 245
 246   // Branch analysis.
 247   bool isUnpredicatedTerminator(const MachineInstr* MI) const override;
 248   bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
 249                      MachineBasicBlock *&FBB,
 250                      SmallVectorImpl<MachineOperand> &Cond,
 251                      bool AllowModify) const override;
 252   unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
 253   unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 254                         MachineBasicBlock *FBB,
 255                         const SmallVectorImpl<MachineOperand> &Cond,
 256                         DebugLoc DL) const override;
 257   bool canInsertSelect(const MachineBasicBlock&,
 258                        const SmallVectorImpl<MachineOperand> &Cond,
 259                        unsigned, unsigned, int&, int&, int&) const override;
 260   void insertSelect(MachineBasicBlock &MBB,
 261                     MachineBasicBlock::iterator MI, DebugLoc DL,
 262                     unsigned DstReg,
 263                     const SmallVectorImpl<MachineOperand> &Cond,
 264                     unsigned TrueReg, unsigned FalseReg) const override;
 265   void copyPhysReg(MachineBasicBlock &MBB,
 266                    MachineBasicBlock::iterator MI, DebugLoc DL,
 267                    unsigned DestReg, unsigned SrcReg,
 268                    bool KillSrc) const override;
 269   void storeRegToStackSlot(MachineBasicBlock &MBB,
 270                            MachineBasicBlock::iterator MI,
 271                            unsigned SrcReg, bool isKill, int FrameIndex,
 272                            const TargetRegisterClass *RC,
 273                            const TargetRegisterInfo *TRI) const override;
 274
 275   void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
 276                       SmallVectorImpl<MachineOperand> &Addr,
 277                       const TargetRegisterClass *RC,
 278                       MachineInstr::mmo_iterator MMOBegin,
 279                       MachineInstr::mmo_iterator MMOEnd,
 280                       SmallVectorImpl<MachineInstr*> &NewMIs) const;
 281
 282   void loadRegFromStackSlot(MachineBasicBlock &MBB,
 283                             MachineBasicBlock::iterator MI,
 284                             unsigned DestReg, int FrameIndex,
 285                             const TargetRegisterClass *RC,
 286                             const TargetRegisterInfo *TRI) const override;
 287
 288   void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
 289                        SmallVectorImpl<MachineOperand> &Addr,
 290                        const TargetRegisterClass *RC,
 291                        MachineInstr::mmo_iterator MMOBegin,
 292                        MachineInstr::mmo_iterator MMOEnd,
 293                        SmallVectorImpl<MachineInstr*> &NewMIs) const;
 294
 295   bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
 296
 297   /// foldMemoryOperand - If this target supports it, fold a load or store of
 298   /// the specified stack slot into the specified machine instruction for the
 299   /// specified operand(s).  If this is possible, the target should perform the
 300   /// folding and return true, otherwise it should return false.  If it folds
 301   /// the instruction, it is likely that the MachineInstruction the iterator
 302   /// references has been changed.
 303   MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
 304                                       MachineInstr* MI,
 305                                       const SmallVectorImpl<unsigned> &Ops,
 306                                       int FrameIndex) const override;
 307
 308   /// foldMemoryOperand - Same as the previous version except it allows folding
 309   /// of any load and store from / to any address, not just from a specific
 310   /// stack slot.
 311   MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
 312                                       MachineInstr* MI,
 313                                       const SmallVectorImpl<unsigned> &Ops,
 314                                       MachineInstr* LoadMI) const override;
 315
 316   /// canFoldMemoryOperand - Returns true if the specified load / store is
 317   /// folding is possible.
 318   bool canFoldMemoryOperand(const MachineInstr*,
 319                             const SmallVectorImpl<unsigned> &) const override;
 320
 321   /// unfoldMemoryOperand - Separate a single instruction which folded a load or
 322   /// a store or a load and a store into two or more instruction. If this is
 323   /// possible, returns true as well as the new instructions by reference.
 324   bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
 325                          unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
 326                          SmallVectorImpl<MachineInstr*> &NewMIs) const override;
 327
 328   bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
 329                            SmallVectorImpl<SDNode*> &NewNodes) const override;
 330
 331   /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
 332   /// instruction after load / store are unfolded from an instruction of the
 333   /// specified opcode. It returns zero if the specified unfolding is not
 334   /// possible. If LoadRegIndex is non-null, it is filled in with the operand
 335   /// index of the operand which will hold the register holding the loaded
 336   /// value.
 337   unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
 338                               bool UnfoldLoad, bool UnfoldStore,
 339                               unsigned *LoadRegIndex = nullptr) const override;
 340
 341   /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
 342   /// to determine if two loads are loading from the same base address. It
 343   /// should only return true if the base pointers are the same and the
 344   /// only differences between the two addresses are the offset. It also returns
 345   /// the offsets by reference.
 346   bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
 347                                int64_t &Offset2) const override;
 348
 349   /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
 350   /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
 351   /// be scheduled togther. On some targets if two loads are loading from
 352   /// addresses in the same cache line, it's better if they are scheduled
 353   /// together. This function takes two integers that represent the load offsets
 354   /// from the common base address. It returns true if it decides it's desirable
 355   /// to schedule the two loads together. "NumLoads" is the number of loads that
 356   /// have already been scheduled after Load1.
 357   bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
 358                                int64_t Offset1, int64_t Offset2,
 359                                unsigned NumLoads) const override;
 360
 361   bool shouldScheduleAdjacent(MachineInstr* First,
 362                               MachineInstr *Second) const override;
 363
 364   void getNoopForMachoTarget(MCInst &NopInst) const override;
 365
 366   bool
 367   ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
 368
 369   /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
 370   /// instruction that defines the specified register class.
 371   bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
 372
 373   /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha
 374   /// would clobber the EFLAGS condition register. Note the result may be
 375   /// conservative. If it cannot definitely determine the safety after visiting
 376   /// a few instructions in each direction it assumes it's not safe.
 377   bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
 378                              MachineBasicBlock::iterator I) const;
 379
 380   static bool isX86_64ExtendedReg(const MachineOperand &MO) {
 381     if (!MO.isReg()) return false;
 382     return X86II::isX86_64ExtendedReg(MO.getReg());
 383   }
 384
 385   /// getGlobalBaseReg - Return a virtual register initialized with the
 386   /// the global base register value. Output instructions required to
 387   /// initialize the register in the function entry block, if necessary.
 388   ///
 389   unsigned getGlobalBaseReg(MachineFunction *MF) const;
 390
 391   std::pair<uint16_t, uint16_t>
 392   getExecutionDomain(const MachineInstr *MI) const override;
 393
 394   void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override;
 395
 396   unsigned
 397     getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
 398                                  const TargetRegisterInfo *TRI) const override;
 399   unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
 400                                 const TargetRegisterInfo *TRI) const override;
 401   void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
 402                                  const TargetRegisterInfo *TRI) const override;
 403
 404   MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
 405                                       MachineInstr* MI,
 406                                       unsigned OpNum,
 407                                       const SmallVectorImpl<MachineOperand> &MOs,
 408                                       unsigned Size, unsigned Alignment,
 409                                       bool AllowCommute) const;
 410
 411   void
 412   getUnconditionalBranch(MCInst &Branch,
 413                          const MCSymbolRefExpr *BranchTarget) const override;
 414
 415   void getTrap(MCInst &MI) const override;
 416
 417   unsigned getJumpInstrTableEntryBound() const override;
 418
 419   bool isHighLatencyDef(int opc) const override;
 420
 421   bool hasHighOperandLatency(const InstrItineraryData *ItinData,
 422                              const MachineRegisterInfo *MRI,
 423                              const MachineInstr *DefMI, unsigned DefIdx,
 424                              const MachineInstr *UseMI,
 425                              unsigned UseIdx) const override;
 426
 427   /// analyzeCompare - For a comparison instruction, return the source registers
 428   /// in SrcReg and SrcReg2 if having two register operands, and the value it
 429   /// compares against in CmpValue. Return true if the comparison instruction
 430   /// can be analyzed.
 431   bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
 432                       unsigned &SrcReg2, int &CmpMask,
 433                       int &CmpValue) const override;
 434
 435   /// optimizeCompareInstr - Check if there exists an earlier instruction that
 436   /// operates on the same source operands and sets flags in the same way as
 437   /// Compare; remove Compare if possible.
 438   bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
 439                             unsigned SrcReg2, int CmpMask, int CmpValue,
 440                             const MachineRegisterInfo *MRI) const override;
 441
 442   /// optimizeLoadInstr - Try to remove the load by folding it to a register
 443   /// operand at the use. We fold the load instructions if and only if the
 444   /// def and use are in the same BB. We only look at one load and see
 445   /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
 446   /// defined by the load we are trying to fold. DefMI returns the machine
 447   /// instruction that defines FoldAsLoadDefReg, and the function returns
 448   /// the machine instruction generated due to folding.
 449   MachineInstr* optimizeLoadInstr(MachineInstr *MI,
 450                                   const MachineRegisterInfo *MRI,
 451                                   unsigned &FoldAsLoadDefReg,
 452                                   MachineInstr *&DefMI) const override;
 453
 454 private:
 455   MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
 456                                               MachineFunction::iterator &MFI,
 457                                               MachineBasicBlock::iterator &MBBI,
 458                                               LiveVariables *LV) const;
 459
 460   /// isFrameOperand - Return true and the FrameIndex if the specified
 461   /// operand and follow operands form a reference to the stack frame.
 462   bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
 463                       int &FrameIndex) const;
 464 };
 465
 466 } // End llvm namespace
 467
 468 #endif