src/llvm/lib/Target/X86/X86InstrVMX.td

   1 //===-- X86InstrVMX.td - VMX Instruction Set Extension -----*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the instructions that make up the Intel VMX instruction
  11 // set.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 //===----------------------------------------------------------------------===//
  16 // VMX instructions
  17
  18 // 66 0F 38 80
  19 def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
  20                "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
  21                Requires<[Not64BitMode]>;
  22 def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
  23                "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
  24                Requires<[In64BitMode]>;
  25 // 66 0F 38 81
  26 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
  27                 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
  28                 Requires<[Not64BitMode]>;
  29 def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
  30                 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
  31                 Requires<[In64BitMode]>;
  32 // 0F 01 C1
  33 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
  34 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
  35   "vmclear\t$vmcs", []>, PD;
  36 // OF 01 D4
  37 def VMFUNC : I<0x01, MRM_D4, (outs), (ins), "vmfunc", []>, TB;
  38 // 0F 01 C2
  39 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
  40 // 0F 01 C3
  41 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
  42 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
  43   "vmptrld\t$vmcs", []>, PS;
  44 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
  45   "vmptrst\t$vmcs", []>, TB;
  46 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
  47   "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>;
  48 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
  49   "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>;
  50 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
  51   "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>;
  52 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
  53   "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>;
  54 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
  55   "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>;
  56 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
  57   "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>;
  58 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
  59   "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>;
  60 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
  61   "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>;
  62 // 0F 01 C4
  63 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
  64 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
  65   "vmxon\t$vmxon", []>, XS;
  66