src/llvm/lib/Target/XCore/XCoreISelLowering.h

   1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that XCore uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H
  16 #define LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H
  17
  18 #include "XCore.h"
  19 #include "llvm/CodeGen/SelectionDAG.h"
  20 #include "llvm/Target/TargetLowering.h"
  21
  22 namespace llvm {
  23
  24   // Forward delcarations
  25   class XCoreSubtarget;
  26   class XCoreTargetMachine;
  27
  28   namespace XCoreISD {
  29     enum NodeType {
  30       // Start the numbering where the builtin ops and target ops leave off.
  31       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  32
  33       // Branch and link (call)
  34       BL,
  35
  36       // pc relative address
  37       PCRelativeWrapper,
  38
  39       // dp relative address
  40       DPRelativeWrapper,
  41
  42       // cp relative address
  43       CPRelativeWrapper,
  44
  45       // Load word from stack
  46       LDWSP,
  47
  48       // Store word to stack
  49       STWSP,
  50
  51       // Corresponds to retsp instruction
  52       RETSP,
  53
  54       // Corresponds to LADD instruction
  55       LADD,
  56
  57       // Corresponds to LSUB instruction
  58       LSUB,
  59
  60       // Corresponds to LMUL instruction
  61       LMUL,
  62
  63       // Corresponds to MACCU instruction
  64       MACCU,
  65
  66       // Corresponds to MACCS instruction
  67       MACCS,
  68
  69       // Corresponds to CRC8 instruction
  70       CRC8,
  71
  72       // Jumptable branch.
  73       BR_JT,
  74
  75       // Jumptable branch using long branches for each entry.
  76       BR_JT32,
  77
  78       // Offset from frame pointer to the first (possible) on-stack argument
  79       FRAME_TO_ARGS_OFFSET,
  80
  81       // Exception handler return. The stack is restored to the first
  82       // followed by a jump to the second argument.
  83       EH_RETURN,
  84
  85       // Memory barrier.
  86       MEMBARRIER
  87     };
  88   }
  89
  90   //===--------------------------------------------------------------------===//
  91   // TargetLowering Implementation
  92   //===--------------------------------------------------------------------===//
  93   class XCoreTargetLowering : public TargetLowering
  94   {
  95   public:
  96
  97     explicit XCoreTargetLowering(const TargetMachine &TM);
  98
  99     using TargetLowering::isZExtFree;
 100     bool isZExtFree(SDValue Val, EVT VT2) const override;
 101
 102
 103     unsigned getJumpTableEncoding() const override;
 104     MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
 105
 106     /// LowerOperation - Provide custom lowering hooks for some operations.
 107     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 108
 109     /// ReplaceNodeResults - Replace the results of node with an illegal result
 110     /// type with new values built out of custom code.
 111     ///
 112     void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
 113                             SelectionDAG &DAG) const override;
 114
 115     /// getTargetNodeName - This method returns the name of a target specific
 116     //  DAG node.
 117     const char *getTargetNodeName(unsigned Opcode) const override;
 118
 119     MachineBasicBlock *
 120       EmitInstrWithCustomInserter(MachineInstr *MI,
 121                                   MachineBasicBlock *MBB) const override;
 122
 123     bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
 124
 125   private:
 126     const TargetMachine &TM;
 127     const XCoreSubtarget &Subtarget;
 128
 129     // Lower Operand helpers
 130     SDValue LowerCCCArguments(SDValue Chain,
 131                               CallingConv::ID CallConv,
 132                               bool isVarArg,
 133                               const SmallVectorImpl<ISD::InputArg> &Ins,
 134                               SDLoc dl, SelectionDAG &DAG,
 135                               SmallVectorImpl<SDValue> &InVals) const;
 136     SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
 137                            CallingConv::ID CallConv, bool isVarArg,
 138                            bool isTailCall,
 139                            const SmallVectorImpl<ISD::OutputArg> &Outs,
 140                            const SmallVectorImpl<SDValue> &OutVals,
 141                            const SmallVectorImpl<ISD::InputArg> &Ins,
 142                            SDLoc dl, SelectionDAG &DAG,
 143                            SmallVectorImpl<SDValue> &InVals) const;
 144     SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
 145     SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
 146                                     SelectionDAG &DAG) const;
 147     SDValue lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain,
 148                                                    SDValue Base, int64_t Offset,
 149                                                    SelectionDAG &DAG) const;
 150
 151     // Lower Operand specifics
 152     SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
 153     SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
 154     SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
 155     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 156     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
 157     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
 158     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 159     SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
 160     SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
 161     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
 162     SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
 163     SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
 164     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
 165     SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
 166     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
 167     SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
 168     SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
 169     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
 170     SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
 171     SDValue LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
 172     SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
 173
 174     // Inline asm support
 175     std::pair<unsigned, const TargetRegisterClass*>
 176     getRegForInlineAsmConstraint(const std::string &Constraint,
 177                                  MVT VT) const override;
 178
 179     // Expand specifics
 180     SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
 181     SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
 182
 183     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 184
 185     void computeKnownBitsForTargetNode(const SDValue Op,
 186                                        APInt &KnownZero,
 187                                        APInt &KnownOne,
 188                                        const SelectionDAG &DAG,
 189                                        unsigned Depth = 0) const override;
 190
 191     SDValue
 192       LowerFormalArguments(SDValue Chain,
 193                            CallingConv::ID CallConv,
 194                            bool isVarArg,
 195                            const SmallVectorImpl<ISD::InputArg> &Ins,
 196                            SDLoc dl, SelectionDAG &DAG,
 197                            SmallVectorImpl<SDValue> &InVals) const override;
 198
 199     SDValue
 200       LowerCall(TargetLowering::CallLoweringInfo &CLI,
 201                 SmallVectorImpl<SDValue> &InVals) const override;
 202
 203     SDValue
 204       LowerReturn(SDValue Chain,
 205                   CallingConv::ID CallConv, bool isVarArg,
 206                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 207                   const SmallVectorImpl<SDValue> &OutVals,
 208                   SDLoc dl, SelectionDAG &DAG) const override;
 209
 210     bool
 211       CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
 212                      bool isVarArg,
 213                      const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
 214                      LLVMContext &Context) const override;
 215   };
 216 }
 217
 218 #endif