src/llvm/test/CodeGen/SystemZ/Large/branch-range-05.py

   1 # Test 32-bit COMPARE IMMEDIATE AND BRANCH in cases where the sheer number of
   2 # instructions causes some branches to be out of range.
   3 # RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
   4
   5 # Construct:
   6 #
   7 # before0:
   8 #   conditional branch to after0
   9 #   ...
  10 # beforeN:
  11 #   conditional branch to after0
  12 # main:
  13 #   0xffcc bytes, from MVIY instructions
  14 #   conditional branch to main
  15 # after0:
  16 #   ...
  17 #   conditional branch to main
  18 # afterN:
  19 #
  20 # Each conditional branch sequence occupies 12 bytes if it uses a short
  21 # branch and 16 if it uses a long one.  The ones before "main:" have to
  22 # take the branch length into account, which is 6 for short branches,
  23 # so the final (0x34 - 6) / 12 == 3 blocks can use short branches.
  24 # The ones after "main:" do not, so the first 0x34 / 12 == 4 blocks
  25 # can use short branches.  The conservative algorithm we use makes
  26 # one of the forward branches unnecessarily long, as noted in the
  27 # check output below.
  28 #
  29 # CHECK: lb [[REG:%r[0-5]]], 0(%r3)
  30 # CHECK: chi [[REG]], 50
  31 # CHECK: jgl [[LABEL:\.L[^ ]*]]
  32 # CHECK: lb [[REG:%r[0-5]]], 0(%r3)
  33 # CHECK: chi [[REG]], 51
  34 # CHECK: jgl [[LABEL]]
  35 # CHECK: lb [[REG:%r[0-5]]], 0(%r3)
  36 # CHECK: chi [[REG]], 52
  37 # CHECK: jgl [[LABEL]]
  38 # CHECK: lb [[REG:%r[0-5]]], 0(%r3)
  39 # CHECK: chi [[REG]], 53
  40 # CHECK: jgl [[LABEL]]
  41 # CHECK: lb [[REG:%r[0-5]]], 0(%r3)
  42 # CHECK: chi [[REG]], 54
  43 # CHECK: jgl [[LABEL]]
  44 # ...as mentioned above, the next one could be a CIJL instead...
  45 # CHECK: lb [[REG:%r[0-5]]], 0(%r3)
  46 # CHECK: chi [[REG]], 55
  47 # CHECK: jgl [[LABEL]]
  48 # CHECK: lb [[REG:%r[0-5]]], 0(%r3)
  49 # CHECK: cijl [[REG]], 56, [[LABEL]]
  50 # CHECK: lb [[REG:%r[0-5]]], 0(%r3)
  51 # CHECK: cijl [[REG]], 57, [[LABEL]]
  52 # ...main goes here...
  53 # CHECK: lb [[REG:%r[0-5]]], 0(%r3)
  54 # CHECK: cijl [[REG]], 100, [[LABEL:\.L[^ ]*]]
  55 # CHECK: lb [[REG:%r[0-5]]], 0(%r3)
  56 # CHECK: cijl [[REG]], 101, [[LABEL]]
  57 # CHECK: lb [[REG:%r[0-5]]], 0(%r3)
  58 # CHECK: cijl [[REG]], 102, [[LABEL]]
  59 # CHECK: lb [[REG:%r[0-5]]], 0(%r3)
  60 # CHECK: cijl [[REG]], 103, [[LABEL]]
  61 # CHECK: lb [[REG:%r[0-5]]], 0(%r3)
  62 # CHECK: chi [[REG]], 104
  63 # CHECK: jgl [[LABEL]]
  64 # CHECK: lb [[REG:%r[0-5]]], 0(%r3)
  65 # CHECK: chi [[REG]], 105
  66 # CHECK: jgl [[LABEL]]
  67 # CHECK: lb [[REG:%r[0-5]]], 0(%r3)
  68 # CHECK: chi [[REG]], 106
  69 # CHECK: jgl [[LABEL]]
  70 # CHECK: lb [[REG:%r[0-5]]], 0(%r3)
  71 # CHECK: chi [[REG]], 107
  72 # CHECK: jgl [[LABEL]]
  73
  74 branch_blocks = 8
  75 main_size = 0xffcc
  76
  77 print 'define void @f1(i8 *%base, i8 *%stop) {'
  78 print 'entry:'
  79 print '  br label %before0'
  80 print ''
  81
  82 for i in xrange(branch_blocks):
  83     next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
  84     print 'before%d:' % i
  85     print '  %%bcur%d = load i8 *%%stop' % i
  86     print '  %%bext%d = sext i8 %%bcur%d to i32' % (i, i)
  87     print '  %%btest%d = icmp slt i32 %%bext%d, %d' % (i, i, i + 50)
  88     print '  br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
  89     print ''
  90
  91 print '%s:' % next
  92 a, b = 1, 1
  93 for i in xrange(0, main_size, 6):
  94     a, b = b, a + b
  95     offset = 4096 + b % 500000
  96     value = a % 256
  97     print '  %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset)
  98     print '  store volatile i8 %d, i8 *%%ptr%d' % (value, i)
  99
 100 for i in xrange(branch_blocks):
 101     print '  %%acur%d = load i8 *%%stop' % i
 102     print '  %%aext%d = sext i8 %%acur%d to i32' % (i, i)
 103     print '  %%atest%d = icmp slt i32 %%aext%d, %d' % (i, i, i + 100)
 104     print '  br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
 105     print ''
 106     print 'after%d:' % i
 107
 108 print '  ret void'
 109 print '}'